Unit-2

CPU and Micro Progarmmed Control

Introduction:

● The main part of the computer that performs the bulk of data-processing
operations is called the central processing unit and is referred to as the CPU.
● The CPU is made up of three major parts, as shown in Fig. 8-1.
● The register set stores intermediate data used during the execution of the
instructions. The arithmetic logic unit (ALU) performs the required
microoperations for executing the instructions.
● The control unit supervises the transfer of information among the registers and
instructs the ALU as to which operation to perform.

Instruction Formats:

● The format of an instruction is usually depicted in a rectangular box symbolizing the bits
of the instruction as they appear in memory words or in a control register.
● The bits of the instruction are divided into groups called fields.
The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be perform
2. An address field that designates a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is determined.
 ● Computers may have instructions of several different lengths containing varying number
of addresses.
● The number of address fields in the instruct format of a computer depends on the
internal organization of its registers.
Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.

1. Single Accumulator Organization:

● In an accumulator type organization all the operations are performed with an implied
accumulator register.
● The instruction format in this type of computer uses one address field.
● For example, the instruction that specifies an arithmetic addition defined by an assembly
language instruction as
ADD X
Where X is the address of the operand. The ADD instruction in this case results in the operation
AC ← AC+M[X]
is the accumulator register and M[X] symbolizes the memory word located at address X.

2. General register organization:

● The instruction format in this type of computer needs three register address fields.
● Thus the instruction for an arithmetic addition may be written in an assembly language
as
● ADD R1, R2, R3 to denote the operation R1←R2 + R3.
● The number of address fields in the instruction can be reduced from three to two if the
destination register is the same as one of the source registers.
● Thus the instruction ADD R1, R2 would denote the operation R1← R1 + R2. Only
register addresses for R1 and R2 need be specified in this instruction.
● General register-type computers employ two or three address fields in their instruction
format.
● Each address field may specify a processor register or a memory word.
● An instruction symbolized by ADD R1, X would specify the operation R1← R1 + M[X].
● It has two address fields, one for register R1 and the other for the memory address X.

3. Stack organization:

● The stack-organized CPU has PUSH and POP instructions which require an address
field.
● Thus the instruction PUSH X will push the word at address X to the top of the stack.
 ● The stack pointer is updated automatically.
● Operation-type instructions do not need an address field in stack-organized computers.
● This is because the operation is performed on the two items that are on top of the stack.
● The instruction ADD in a stack computer consists of an operation code only with no
address field.
● This operation has the effect of popping the two top numbers from the stack, adding the
numbers, and pushing the sum into the stack.
● There is no need to specify operands with an address field since all operands are
implied to be in the stack.
● Most computers fall into one of the three types of organizations.
● Some computers combine features from more than one organizational structure.
● The influence of the number of addresses on computer programs, we will evaluate the
arithmetic statement

X= (A+B) * (C+D)

● Using zero, one, two, or three address instructions and using the symbols ADD, SUB,
MUL and DIV for four arithmetic operations; MOV for the transfer type operations; and
LOAD and STORE for transfer to and from memory and AC register.
● Assuming that the operands are in memory addresses A, B, C, and D and the result
must be stored in memory ar address X and also the CPU has general purpose registers
R1, R2, R3 and R4.

Three Address Instructions:

● Three-address instruction formats can use each address field to specify either a
processor register or a memory operand.
● The program assembly language that evaluates X = (A+B) * (C+D) is shown below,
together with comments that explain the register transfer operation of each instruction.

● The symbol M [A] denotes the operand at memory address symbolized by A.

● The advantage of the three-address format is that it results in short programs when
evaluating arithmetic expressions.
● The disadvantage is that the binary-coded instructions require too many bits to specify
three addresses.

Two Address Instructions:

● Two-address instructions formats use each address field can specify either a processor
register or memory word.
 ● The program to evaluate X = (A+B) * (C+D) is as follows

● The MOV instruction moves or transfers the operands to and from memory and
processor registers.
● The first symbol listed in an instruction is assumed be both a source and the destination
where the result of the operation transferred.

One Address Instructions:

● One-address instructions use an implied accumulator (AC) register for all data
manipulation.
● For multiplication and division there is a need for a second register. But for the basic
discussion we will neglect the second register and assume that the AC contains the
result of all operations.
● The program to evaluate X=(A+B) * (C+D) is

● All operations are done between the AC register and a memory operand.
● T is the address of a temporary memory location required for storing the intermediate
result.

Zero Address Instructions:

● A stack-organized computer does not use an address field for the instructions ADD and
MUL.
● The PUSH and POP instructions, however, need an address field to specify the operand
that communicates with the stack.
● The following program shows how X = (A+B) * (C+D) will be written for a
stack-organized computer.(TOS stands for top of stack).
 ● To evaluate arithmetic expressions in a stack computer, it is necessary to convert the
expression into reverse Polish notation.
● The name "zero-address” is given to this type of computer because of the absence of an
address field in the computational instructions.

RISC Instructions:

● The instruction set of a typical RISC processor is use only load and store instructions for
communicating between memory and CPU.
● All other instructions are executed within the registers of CPU without referring to
memory.
● LOAD and STORE instructions that have one memory and one register address, and
computational type instructions that have three addresses with all three specifying
processor registers.
● The following is a program to evaluate X=(A+B)*(C+D)

● The load instructions transfer the operands from memory to CPU register.
● The add and multiply operations are executed with data in the register without accessing
memory.
● The result of the computations is then stored memory with a store in instruction.
Addressing Modes:

● The way the operands are chosen during program execution is dependent on the
addressing mode of the instruction.
● Computers use addressing mode techniques for the purpose of accommodating one or
both of the following provisions:
1. To give programming versatility to the user by providing such facilities as pointers
to memory, counters for loop control, indexing of data, and program relocation.
2. To reduce the number of bits in the addressing field of the instruction
● Most addressing modes modify the address field of the instruction; there are two modes
that need no address field at all. These are implied and immediate modes.

Implied Mode:
● In this mode the operands are specified implicitly in the definition of the instruction.
● For example, the instruction "complement accumulator" is an implied-mode instruction
because the operand in the accumulator register is implied in the definition of the
instruction.
● All register reference instructions that use an accumulator are implied mode instructions.
● Zero address in a stack organization computer is implied mode instructions.

Immediate Mode:
● In this mode the operand is specified in the instruction itself.
● In other words an immediate-mode instruction has an operand rather than an address
field.
● Immediate-mode instructions are useful for initializing registers to a constant value.
● The address field of an instruction may specify either a memory word or a processor
register.
● When the address specifies a processor register, the instruction is said to be in the
register mode.

Register Mode:

● In this mode the operands are in registers that reside within the CPU.
● The particular register is selected from a register field in the instruction.

Register Indirect Mode:

● In this mode the instruction specifies a register in CPU whose contents give the address
of the operand in memory.
● In other words, the selected register contains the address of the operand rather than the
operand itself.
● The advantage of a register indirect mode instruction is that the address field of the
instruction uses few bits to select a register than would have been required to specify a
memory address directly.
Auto-increment or Auto-Decrement Mode:

● This is similar to the register indirect mode except that the register is incremented or
decremented after (or before) its value is used to access memory.
● The address field of an instruction is used by the control unit in the CPU to obtain the
operand from memory.
● Sometimes the value given in the address field is the address of the operand, but
sometimes it is just an address from which the address of the operand is calculated.
● The basic two mode of addressing used in CPU are direct and indirect address mode.

Direct Address Mode:

● In this mode the effective address is equal to the address part of the instruction.
● The operand resides in memory and its address is given directly by the address field of
the instruction.
● In a branch-type instruction the address field specifies the actual branch address.

Indirect Address Mode:

● In this mode the address field of the instruction gives the address where the effective
address is stored in memory.
● Control fetches the instruction from memory and uses its address part to access memory
again to read the effective address.
● A few addressing modes require that the address field of the instruction be added to the
content of a specific register in the CPU.
● The effective address in these modes is obtained from the following computation:
● Effective address =address part of instruction + content of CPU register
● The CPU register used in the computation may be the program counter, an index
register, or a base register.
● We have a different addressing mode which is used for a different application.

Relative Address Mode:

● In this mode the content of the program counter is added to the address part of the
instruction in order to obtain the effective address.

Indexed Addressing Mode:

● In this mode the content of an index register is added to the address part of the
instruction to obtain the effective address.
● An index register is a special CPU register that contains an index value.
Base Register Addressing Mode:

● In this mode the content of a base register is added to the address part of the instruction
to obtain the effective address.
● This is similar to the indexed addressing mode except that the register is now called a
base register instead of an index register.

Numerical Example:
● To show the differences between the various modes, we will show the effect of the
addressing modes on the instruction defined in Fig. 8-7.

● The two-word instruction at address 200 and 201 is a "load to AC" instruction with an
address field equal to 500.
● The first word of the instruction specifies the operation code and mode, and the second
word specifies the address part.
● PC has the value 200 for fetching this instruction. The content of processor register R1 is
400, and the content of an index register XR is 100.
● AC receives the operand after the instruction is executed.
● In the direct address mode the effective address is the address part of the instruction
500 and the operand to be loaded into AC is 500.
● In the immediate mode the second word of the instruction is taken as the operand rather
than an address, so 500 is loaded into AC.
● In the indirect mode the effective address is stored in memory at address 500.
Therefore, the effective address is 800 and the operand is 300.
● In the relative mode the effective address is 500 + 202 =702 and the operand is 325.
(the value in PC after the fetch phase and during the execute phase is 202.)
● In the index mode the effective address is XR+ 500 = 100 + 500 = 600 and the operand
is 900.
● In the register mode the operand is in R1 and 400 is loaded into AC.
● In the register indirect mode the effective address is 400, equal to the content of R1 and
the operand loaded into AC is 700.
● The auto-increment mode is the same as the register indirect mode except that R1 is
incremented to 401 after the execution of the instruction.
● The auto-decrement mode decrements R1 to 399 prior to the execution of the
instruction. The operand loaded into AC is now 450.
● Table 8-4 lists the values of the effective address and the operand loaded into AC for the
nine addressing modes.
Control Memory:

● The general configuration of a micro-programmed control unit is demonstrated in the

block diagram of Figure 4.1.
● The control memory is assumed to be a ROM, within which all control information is
permanently stored.
● The control memory address register specifies the address of the microinstruction, and
the control data register holds the microinstruction read from memory.
● The microinstruction contains a control word that specifies one or more microoperations
● for the data processor. Once these operations are executed, the control must determine
the next address.
● The location of the next microinstruction may be the one next in sequence, or it may be
located somewhere else in the control memory.
● While the microoperations are being executed, the next address is computed in the next
address generator circuit and then transferred into the control address register to read
the next microinstruction.
● Thus a microinstruction contains bits for initiating microoperations in the data processor
part and bits that determine the address sequence for the control memory.
● The next address generator is sometimes called a micro-program sequencer, as it
determines the address sequence that is read from control memory.
● Typical functions of a micro-program sequencer are incrementing the control address
register by one, loading into the control address register an address from control
memory, transferring an external address, or loading an initial address to start the control
operations.
● The control data register holds the present microinstruction while the next address is
computed and read from memory.
● The data register is sometimes called a pipeline register.
● It allows the execution of the microoperations specified by the control word
simultaneously with the generation of the next microinstruction.
● This configuration requires a two-phase clock, with one clock applied to the address
register and the other to the data register.
● The main advantage of the micro programmed control is the fact that once the hardware
configuration is established; there should be no need for further hardware or wiring
changes.
 ● If we want to establish a different control sequence for the system, all we need to do is
specify a different set of microinstructions for control memory.

Address Sequencing:

Microinstructions are stored in control memory in groups, with each group specifying a
routine.
To appreciate the address sequencing in a microprogram control unit, let us specify the
steps that the control must undergo during the execution of a single computer instruction.

Step-1:
● An initial address is loaded into the control address register when power is turned on in
the computer.
● This address is usually the address of the first microinstruction that activates the
instruction fetch routine.
● The fetch routine may be sequenced by incrementing the control address register
through the rest of its microinstructions.
● At the end of the fetch routine, the instruction is in the instruction register of the
computer.
Step-2:
● The control memory next must go through the routine that determines the effective
address of the operand.
● A machine instruction may have bits that specify various addressing modes, such as
indirect address and index registers.
● The effective address computation routine in control memory can be reached through a
branch microinstruction, which is conditioned on the status of the mode bits of the
instruction.
● When the effective address computation routine is completed, the address of the
operand is available in the memory address register.

Step-3:
● The next step is to generate the microoperations that execute the instruction fetched
from memory.
● The microoperation steps to be generated in processor registers depend on the
operation code part of the instruction.
● Each instruction has its own micro-program routine stored in a given location of control
memory.
● The transformation from the instruction code bits to an address in control memory where
the routine is located is referred to as a mapping process.
● A mapping procedure is a rule that transforms the instruction code into a control
memory address.

Step-4:
● Once the required routine is reached, the microinstructions that execute the instruction
may be sequenced by incrementing the control address register.
● Micro-programs that employ subroutines will require an external register for storing the
return address.
● Return addresses cannot be stored in ROM because the unit has no writing capability.
● When the execution of the instruction is completed, control must return to the fetch
routine.
● This is accomplished by executing an unconditional branch microinstruction to the first
address of the fetch routine.

Explanation:

● Above figure 4.2 shows a block diagram of a control memory and the associated
hardware needed for selecting the next microinstruction address.
● The microinstruction in control memory contains a set of bits to initiate microoperations
in computer registers and other bits to specify the method by which the next address is
obtained.
● The diagram shows four different paths from which the control address register (CAR)
receives the address.
 ● The incrementer increments the content of the control address register by one, to select
the next microinstruction in sequence.
● Branching is achieved by specifying the branch address in one of the fields of the
microinstruction.
● Conditional branching is obtained by using part of the microinstruction to select a specific
status bit in order to determine its condition.
● An external address is transferred into control memory via a mapping logic circuit.
● The return address for a subroutine is stored in a special register whose value is then
used when the micro-program wishes to return from the subroutine.
● The branch logic of figure 4.2 provides decision-making capabilities in the control unit.
● The status conditions are special bits in the system that provide parameter information
such as the carry-out of an adder, the sign bit of a number, the mode bits of an
instruction, and input or output status conditions.
● The status bits, together with the field in the microinstruction that specifies a branch
address, control the conditional branch decisions generated in the branch logic.
● A 1 output in the multiplexer generates a control signal to transfer the branch address
from the microinstruction into the control address register.
● A 0 output in the multiplexer causes the address register to be incremented.

Design of Control unit:

Hardwired Control Unit:

● In this implementation, CU is essentially a combinational circuit. Its i/p signals are
transformed into set of o/p logic signal which are control signals.
● Control unit inputs
Flags and control bus
● Each bit means something
Instruction register
● Op-code causes different control signals for each different instruction
● Unique logic for each op-code
● Decoder takes encoded input and produces single output
● Each decoder i/p will activate a single unique o/p
Clock
● Repetitive sequence of pulses
● Useful for measuring duration of micro-ops
● Must be long enough tallow signal propagation along data paths and through processor
circuitry
● Different control signals at different times within instruction cycle
● Need a counter as i/p tcontrol unit with different control signals being used for t1, t2 etc.
● At end of instruction cycle, counter is re-initialised
The bits of the micro instruction are usually divided into fields, with each field defining a distinct,
separate function.

Mainly we can design control unit in two ways:

1. Hardwired Control
2. Microprogrammed Control

Implementation
Hardwired Control:
It means the control logic is implemented with the help of hardwired components

Microprogrammed Control:
It means the control logic is implemented with the help of software program

● Here, microprogram means a collection of micro instructions each micro instructions

mainly contains 3 micro-operation filed they are F1,F2 and F3
● Here the size of F1 is 3 bits, size of F2 and F3 is also 3 bits. So it is decoded with a 3x8
decoder.
● The advantage of decoder it accepts n inputs and it produces 2 power n outputs
● Here, 3 inputs are there for 3 inputs is produces 2 power 3 that is 8 pitputs, but out of 8
outputs, one does not perform any operation. One output and remaining are 7 outputs
● So, from F1 microoperation field we can perform 7 operations likewise some process for
F2
● So, from the F3 microoperation field one doesnt perform any operation as well as one
more that is reserved perform for further purpose. So F3 field perform only 6 operations.
● F1=7 F2=7 F3=6 totally we have 20 operations.
● Out of 20 operations we can demonstrate 5 operations with help of above diagram. If we
draw 20 operations on these diagram, the diagram become complicated so only we draw
5 operations.
● Here, we are no taking any operations on F3. We are taking operations on F2 and F3.
● Let us condider F2 operation, here the output 3 of F2 is connected to arithmetic logic
shift unit (ALU). It performs AND operation by default operation performed on the
accumulator (AC). AND operation will be performed on AC and data register (F2) and
the corresponding result is transferred to the AC

AC ←AC^DR
● Here, we are applying a clock pulses on the corresponding accumulator.
● Whenever load control input is enable ten the corresponding result will be loaded into
the AC
● Actually, F2 produces 7 operations, but out of 7 operations we are showing only one
operation. But internally In the computer what will happen is the remaining 6 connections
will also be established internally in the computer to perform all the logical operations
● Let us consider F1, here we are showing 3 operations.
● The output 1 of F1 is applied to ALU, here output is nothing but add operation. Add
operation will be performed on AC and data register and the content/ result will be
transferred to the AC

AC ←AC+DR
● Whenever load control input is enabled then the corresponding result will be loaded into
the AC by applying some clock pulses
● The output 5 DRTAR transfers the content of the address register to the data register.
● The Output 6 PCTAR stand for transfer of the content of the address register to the
program counter
● Whenever the output 6 (110) is activated then the address register address will be
transferred to the program counter
● Here, we have a multiplexer so whenever output 6 enable then the multiplexer transfers
the PC to AR. For that purpose we are enabling the load control input of the address
register (AR), so here also we should apply some clock pulses to the AR
● Likewise, 5 (101) data register (DR) content is transferred to the AR (Address register),
but the size of the DR is 16 bits whereas the size of AR is only 12 bits so the right most
significant 12 bits of the DR (0-11) are transferred to the address register (AR)
● Whenever the output (101) same for 5, 4 outputs.
Hardwired Control Unit vs Microprogrammed Control Unit:

Hardwired Control Unit Microprogrammed Control Unit

● Hardwired control unit ● Microprogrammed control unit

generates the control signals generates the control signals
needed for the processor using with the help of micro
logic circuits instructions stored in control
memory

● Hardwired control unit is faster ● This is slower than the other

when compared to as micro instructions are used
microprogrammed control unit for generating signals here
as the required control signals
are generated with the help of
hardwares

● Difficult to modify as the control ● Easy to modify as the

signals that need to be modification need to be done
generated are hard wired only at the instruction level

● More costlier as everything has ● Less costlier than hardwired

to be realized in terms of logic control as only micro
gates instructions are used for
generating control signals

● It cannot handle complex ● It can handle complex

instructions as the circuit design instructions
for it becomes complex

● Only limited number of ● Control signals for many

instructions are used due to the instructions can be generated
hardware implementation

● Used in computer that makes ● Used in computer that makes

use of Reduced Instruction Set use of Complex Instruction Set
Computers(RISC) Computers(CISC)