Lecture 6:

Circuit design
– part 2

6.1 Combinational circuit

design
6.2 Sequential circuit design
6.3 Circuit simulation
6.4. Hardware description
language

Sequential Circuit Design 1

2. Sequential circuit design

 Combinational logic
– output depends on current inputs
 Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state or tokens
– Ex: FSM, pipeline
clk clk clk clk

in out
CL CL CL

Finite State Machine Pipeline

Sequential Circuit Design CMOS VLSI Design 4th Ed. 2

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 Sequencing Cont.
 If tokens moved through pipeline at constant speed,
no sequencing elements would be necessary
 Ex: fiber-optic cable
– Light pulses (tokens) are sent down cable
– Next pulse sent before first reaches end of cable
– No need for hardware to separate pulses
– But dispersion sets min time between pulses
 This is called wave pipelining in circuits
 In most circuits, dispersion is high
– Delay fast tokens so they don’t catch slow ones.

Sequential Circuit Design CMOS VLSI Design 4th Ed. 3

Sequencing Overhead
 Use flip-flops to delay fast tokens so they move
through exactly one stage each cycle.
 Inevitably adds some delay to the slow tokens
 Makes circuit slower than just the logic delay
– Called sequencing overhead
 Some people call this clocking overhead
– But it applies to asynchronous circuits too
– Inevitable side effect of maintaining sequence

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 Sequencing Elements
 Latch: Level sensitive
– a.k.a. (also known as) transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
clk clk
 Timing Diagrams clk clk

Latch

Flop
– Transparent

Latch
DD Q D Q

Flop
Q D Q

– Opaque
– Edge-trigger clk
clk

DD

QQ(latch)
(latch)

QQ(flop)
(flop)

Sequential Circuit Design CMOS VLSI Design 4th Ed. 5

Sequencing Methods
Tc
Flip-flops
2-Phase Latches
Flip-Flops

c lk

Pulsed Latches c lk c lk
Flop

Flop

C o m b in a t i o n a l L o g ic
2-Phase Transparent Latches

1
t n o n o v e r la p t n o n o v e r la p
T c/2
2

1 2 1
Latch

Latch

Latch

C o m b i n a t io n a l C o m b i n a t io n a l
L o g ic L o g ic
H a lf-C y c le 1 H a lf - C y c l e 1
Pulsed Latches

p tp w

p p
Latch

Latch

C o m b in a t io n a l L o g ic

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 Timing Diagrams
Contamination and
Propagation Delays A tpd
Combinational
A Y
tpd Logic Prop. Delay Logic
Y tcd

tcd Logic Cont. Delay

clk clk tsetup
thold
tpcq Latch/Flop Clk->Q Prop. Delay

Flop
D Q D
tccq Latch/Flop Clk->Q Cont. Delay tpcq
Q tccq
tpdq Latch D->Q Prop. Delay

tcdq Latch D->Q Cont. Delay clk tsetup thold

clk
tccq tpcq
tsetup Latch/Flop Setup Time

Latch
D Q D tpdq
tcdq
thold Latch/Flop Hold Time Q

Sequential Circuit Design CMOS VLSI Design 4th Ed. 7

Max-Delay Constraints: Flip-Flops

• If the combination logic delay is too great, the receiving element will
miss its setup time and sample the wrong value.
• This is called a setup time failure or max-delay failure.
• It can be solved by redesigning the logic to be faster or by increasing the
clock period.

t pd  Tc   tsetup  t pcq 
clk clk

 Q1 D2
Combinational Logic
F1

F2

sequencing overhead

Tc

tsetup
clk
tpcq

Q1 tpd

D2

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 Max Delay Constraints : 2-Phase Latches
1 2 1

t pd  t pd 1  t pd 2  Tc  2
t  D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
pdq
Logic 1 Logic 2
sequencing overhead

1

2
Tc

D1 tpdq1

Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

Sequential Circuit Design CMOS VLSI Design 4th Ed. 9

Max Delay: Pulsed Latches

t pd  Tc  max  t pdq , t pcq  tsetup  t pw  p p

 D1 Q1
Combinational Logic
D2 Q2
L1

L2

sequencing overhead
Tc

D1 tpdq

(a) tpw > tsetup

Q1 tpd

D2

p

tpcq Tc tpw
Q1 tpd tsetup
(b) tpw < tsetup
D2

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5
 Min-Delay Constraints: Flip-Flops
• If the hold time is large and the contamination delay is small, data can
incorrectly propagate through two successive elements on one clock edge,
corrupting the state of the system.
• This is called a race condition, hold-time failure, or min-delay failure.
• It can only be fixed by redesigning the logic, not by slowing the clock.
clk

tcd  thold  tccq Q1

CL

F1
clk

D2

F2
clk

Q1 tccq tcd

D2 thold

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Min-Delay Constraints : 2-Phase Latches

1
tcd 1,tcd 2  thold  tccq  tnonoverlap Q1
CL
L1

Hold time reduced 2

by nonoverlap D2
L2

Paradox: hold
tnonoverlap
applies twice each 1

cycle, vs. only 2

tccq

once for flops.

Q1 tcd
But a flop is made
D2 thold
of two latches!
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 Min-Delay Constraints: Pulsed Latches

p
tcd  thold  tccq  t pw
Q1
CL

L1
Hold time p
increased by
D2
pulse width

L2
p
tpw
thold

Q1 tccq tcd

D2

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Time Borrowing
 In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
 In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

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 Time Borrowing Example
1

2
1 2 1

Latch

Latch

Latch
Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
1 2
Latch

Latch
Combinational
(b) Combinational Logic Logic

Loops may borrow time internally but must complete within the cycle

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How Much Borrowing?

2-Phase Latches 1 2

Tc D1 Q1 D2 Q2
  tsetup  tnonoverlap 
Combinational Logic 1
L1

L2

tborrow 
2
1

Pulsed Latches 2
Tc
tnonoverlap

tsetup
tborrow  t pw  tsetup Tc/2
Nominal Half-Cycle 1 Delay
tborrow

D2

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 Clock Skew
 Clock skew is a phenomenon in which the same
sourced clock signal arrives at different components
(generally latches or flip-flops) at different times
 We have assumed ideal clocks with zero skew
 Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing

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Skew: Flip-Flops
clk clk

t pd  Tc   t pcq  tsetup  tskew 

Q1 D2
Combinational Logic
F1

F2

   Tc

sequencing overhead
clk

tcd  thold  tccq  tskew

tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1
CL
F1

clk

D2
F2

t skew

clk
thold

Q1 tccq

D2 tcd

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 Skew: Latches
2-Phase Latches 1 2 1

2
t 
D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
t pd  Tc  Logic 1 Logic 2

pdq

sequencing overhead 1

tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew 2

Tc
tborrow    tsetup  tnonoverlap  tskew 
2
Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  tskew 

sequencing overhead

tcd  thold  t pw  tccq  tskew

tborrow  t pw   tsetup  tskew 

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Two-Phase Clocking
 If setup times are violated, reduce clock speed
 If hold times are violated, chip fails at any speed
 In this class, working chips are most important
– No tools to analyze clock skew
 An easy way to guarantee hold times is to use 2-
phase latches with big nonoverlap times
 Call these clocks 1, 2 (ph1, ph2)

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10
 Safe Flip-Flop
 Past years used flip-flop with nonoverlapping clocks
– Slow – nonoverlap adds to setup time
– But no hold times
 In industry, use a better timing analyzer
– Add buffers to slow signals if hold time is at risk
  Q

X
D Q
 
 

 

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Adaptive Sequencing
p

 Designers include timing margin X

ERR
– Voltage D Q

– Temperature
– Process variation p

D
– Data dependency Q
X
– Tool inaccuracies ERR

 Alternative: run faster and check for near failures

– Idea introduced as “Razor”
• Increase frequency until at the verge of error
• Can reduce cycle time by ~30%

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 Latch Design
 Pass Transistor Latch
 Pros 
+ Tiny
+ Low clock load D Q
 Cons
– Vt drop Used in 1970’s
– nonrestoring
– backdriving
– output noise sensitivity
– dynamic
– diffusion input

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Latch Design
 Transmission gate

+ No Vt drop
- Requires inverted clock D Q

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 Latch Design
 Inverting buffer 
+ Restoring D
X
Q
+ No backdriving

+ Fixes either 

• Output noise sensitivity D Q

• Or diffusion input

– Inverted output

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Latch Design
 Tristate feedback

+ Static
X
– Backdriving risk D Q



 Static latches are now essential

because of leakage 

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 Latch Design
 Buffered input

+ Fixes diffusion input
X
D Q
+ Noninverting



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Latch Design
 Buffered output  Q

+ No backdriving D
X




 Widely used in standard cells 

+ Very robust (most important)
- Rather large
- Rather slow (1.5 – 2 FO4 delays)
- High clock loading

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 Latch Design
 Datapath latch Q

+ smaller X
D
+ faster


- unbuffered input

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Flip-Flop Design
 Flip-flop is built as pair of back-to-back latches
 
X
D Q

 

  Q

X
D Q
 
 

 

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 Enable
 Enable: ignore clock when en = 0
– Mux: increase latch D-Q delay
– Clock Gating: increase en setup time, skew
Symbol Multiplexer Design Clock Gating Design
 en

 

D 1
Latch

Latch

Latch
D Q Q D Q
0

en en

 en


 D 1
Flop

Q
0
Flop

Flop
D Q D Q
en
en

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Reset
 Force output low when reset asserted
 Synchronous vs. asynchronous
 
Symbol

Latch

Flop

D Q D Q

reset reset
Synchronous Reset

 Q   Q

reset reset
Q
D D
 

  

 


Q
Q 
Asynchronous Reset

 
reset
reset
D
D 
 

 
reset
reset




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 Set / Reset
 Set forces output high when enabled

 Flip-flop with asynchronous set and reset



reset
set Q
D




set
reset



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Summary
 Flip-Flops:
– Very easy to use, supported by all tools
 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
 Pulsed Latches:
– Fast, some skew tol & borrow, hold time risk

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 Review
1. Distinguish combinational circuits and sequential circuits?
2. What are tokens in sequential circuits? Why are tokens
needed?
3. What are propagation delay and contamination delay?
4. Explain setup time, hold time.
5. Explain max-delay constraints, min-delay constraints, time
borrowing, and clock skew.
6. What are pros and cons of latches using pass transistors,
transmission gates, inverting buffers, three state feedback,
buffered input, datapath?

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