IC OVERVIEW
RTL DESIGN AND VERIFICATION
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COURSE INTRODUCTION
Khóa Học Thiết Kế Vi Mạch Cơ Bản - Trung Tâm Đào Tạo Thiết Kế Vi Mạch ICTC
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COURSE INTRODUCTION
SUMMARY
HOMEWORK
QUESTION
SELF-LEARNING
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Session 9: Verilog
Fundamental – Part 4 1. Sequential logic design
Sequential Logic 2. Non-blocking assignment
Design 3. Latch
.
4. Flip-flop
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SEQUENTIAL LOGIC DESIGN
▪ A RTL design is incomplete without any register logic, need an
element to store value, so the sequential logic holds the binary data.
▪ Sequential logic elements are latches and flip-flops and are used to
design the sequential circuits for the given design functionality
▪ Sequential logic are used to non-blocking assignment ( <= ).
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NON-BLOCKING ASSIGNMENT
▪ Non-blocking assignment are primarily used in sequential logic generation.
▪ LHS of non-blocking assignment must be reg type.
▪ All assignments in RHS run in parallel. Than means all variables within the same clock cycle are
updated simultaneously.
▪ Syntax: y <= expression;
▪ Example: (1) b <= a + 1;
(2) c <= b + 2;
Assume that a = 1, b = 1 → (1) and (2) are executed in parallel, then b = 2, c = 3
Always make sure that bit-width of LHS and RHS are equal to avoid unexpected issues
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LATCH
▪ A latch is a type of sequential logic circuit used to store information.
▪ There are many kinds of latch: SR Latch, JK Latch, D Latch, T Latch. We will focus
on D-latch only in this course.
▪ D-latch has a single data input D and an enable input “enable”.
o When EN is active, output Q follows the input D
o When EN is inactive, the output retains its last update
input
output
D latch
enable
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LATCH
//code to generate a latch
always @ (a or en)
a
begin
if( en == 1’b1) begin
en y = a;
end
y end
a y
D Q
D latch
en EN
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LATCH
▪ Avoid using latch in synchronous design as much as possible because the data
changed asynchronously with clock.
▪ Take care of all branch conditions in if-else or case statements to avoid creating
un-intentional latches.
//4:2 encoder //4:2 encoder
always @ (In_A) begin always @ (In_A) begin
case(In_A) case(In_A)
4’b0001 : Out_Y = 2’b00; 4’b0001 : Out_Y = 2’b00;
4’b0010 : Out_Y = 2’b01; 4’b0010 : Out_Y = 2’b01;
4’b0100 : Out_Y = 2’b10;
4’b0100 : Out_Y = 2’b10;
This code will 4’b1000 : Out_Y = 2’b11;
4’b1000 : Out_Y = 2’b11;
generate latches default : Out_Y = 2’b00;
endcase
endcase
end end
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FLIP-FLOP
▪ A flip-flop is a type of sequential logic circuit used to store information.
▪ A flip-flop responds to the input level change at clock edge.
▪ There are 2 types of flip-flop:
o Positive edge triggered
o Negative edge triggered
input Rising edge
output
Flip-Flop
clock
Falling edge
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FLIP-FLOP
rising edge triggered
//code to generate a rising edge F.F
always @ (posedge clk)
a
begin
y <= a; //non-blocking assignment
clk
end
a D Q y
D F.F
clk
CK
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FLIP-FLOP
falling edge triggered
//code to generate a falling edge F.F
always @ (negedge clk)
a
begin
y <= a; //non-blocking assignment
clk
end
a D Q y
D F.F
clk
CK
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FLIP-FLOP SETUP & HOLD TIME
▪ Setup time: the time duration that the input should remain stable before the
arrival of the clock edge.
▪ Hold time: the time duration that the input should remain stable after the clock D Q
edge.
D F.F
hold time setup time
violation violation CK
D D D
tsetup thold tsetup thold tsetup thold
CLK CLK CLK
We may not get the correct output of Flip-flop (can not sample data correctly) when violation occurs !!!
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FLIP-FLOP PROPAGATION DELAY
a a y
D Q
D F.F
clk clk
CK
So far, we assumed that at clock edge, the F.F samples the input and changes its value
immediately. But actually, the FF requires a certain time to response to the input change.
Therefore, the change in the output of FF will appear after a certain delay.
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FLIP-FLOP PROPAGATION DELAY
But actually, the FF requires a certain time to response to the input change.
Therefore, the change in the output of FF will appear after a certain delay.
T0 T1 T2 T0 T1 T2
1 2
a a
clk clk
tprop tprop
y y
When you see (2), it’s (1)
sig T0 T1 T2 actually. (2) is just the ideal a D Q y
a 0 1 0 case. D F.F
y 0 0 1 The EDA tool also understands clk
(2) same as (1). CK
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FLIP-FLOP PROPAGATION DELAY
You will see some waveform in document like below, where signals do not change on
clock edges due to propagation delay
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FLIP-FLOP PROPAGATION DELAY
Example: for the below circuit, you will see (1) in the simulation waveform, but
actually it is (2). That means, if you read the value of b at the first clock edge, the
returned value is 0. If you read b on the second clock edge, b is 1.
a b c
D Q D Q
D F.F D F.F Let confirm this in the practice session later !!!
CK CK
1 2
clk clk
a a
b b
c c
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ASYNCHRONOUS SET/RESET
The output of F.F can be set to 1 or reset to 0 asynchronously to clock signal.
Below is the active high asynchronous reset.
//code to generate a rising edge F.F with
positive edge asyn. reset
always @ (posedge clk or posedge rst)
a begin
if( rst == 1’b1)
y <= 1’b0;
clk else
y <= a;
end
rst
rst
y a y
clk
D F.F
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ASYNCHRONOUS SET/RESET
The output of F.F can be set to 1 or reset to 0 asynchronously to clock signal.
Below is the active low asynchronous reset.
//code to generate a rising edge F.F with
negative edge asyn. reset
always @ (posedge clk or negedge rst_n)
a
begin
if( rst_n == 1’b0)
clk y <= 1’b0;
else
y <= a;
rst_n
end
a y
y
D F.F
clk
We often use active low asynchronous reset in actual design !!!
rst_n
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SYNCHRONOUS SET/RESET
F.F can use synchronous reset to initialize the data pin, the reset need to be
synchronized with clk. //code to generate a rising edge F.F with low
active sync. reset
always @ (posedge clk) begin
a if( rst_n == 1’b0)
y <= 1’b0;
else
clk y <= a;
end
rst_n
rst_n
a 1 y
y
1’b0 0
D F.F
clk
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PRACTICE
Practice: Design a delay circuit as below, and confirm the previous example.
“If you read the value of b at the first clock edge, the returned value is 0. If you read b
on the second clock edge, b is 1.”
Copy 09_ss9/delay_ff in /ictc/student-data/share/teacher folder and create delay_ff.v
under rtl.
delay_ff
a D Q b D Q c
D F.F D F.F
clk CK clk CK
rst_n
After running, the log should appears like this. Open waveform for checking.
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PRACTICE
Practice: Design a 8-bit counter
▪ 8-bit counter using D-FF, low active async reset, init value = 0.
▪ When counter reach max value, it overflowed (count_overflow = 1) and count
again.
▪ Count_overflow is assert only when counter is overflowed and negate after that
▪ Draw waveform and logic diagram first
▪ Use the /ictc/student-data/share/teacher/09_ss9/counter for testing and create
counter.v under rtl folder.
clk overflow
counter count[7:0]
rst_n
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SESSION 9
SUMMARY
SUMMARY:
❑ Sequential logic elements are latches and flip-flops, can hold data.
❑ Need to use non-blocking assignment to generate sequential logic.
❑ Need to design carefully when coding for combinational logic so that not to generate
un-intentional latches.
❑ Flip-flop has setup/hold time and propagation delay.
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HOMEWORK
Homework1: Add more functions to 8bit counter
▪ 8-bit counter using D-FF, low active async reset.
▪ Reset (initial) value is 8’h00
▪ When counter reach max value, it overflowed (overflow = 1) and count again.
▪ “overflow” is assert only when counter is overflowed and negate after that
▪ Counter only start counting when input “count_en” is High. Otherwise, keep current value.
▪ Counter is cleared to its initial value (8’h00) when “count_clr” is High regardless of count_en. Note
that count_clr is not a reset signal, it’s just a data signal.
▪ Draw waveform and logic diagram first
▪ Use the /ictc/student-data/share/teacher/09_ss9/counter_hw for testing and create counter.v
under rtl folder. clk
rst_n overflow
count_en counter count[7:0]
count_clr
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HOMEWORK
Homework2(*): Design a rising edge detector and falling endge detector following below waveform
pulse_out_p: indicates rising edge on sig_in signal.
pulse_out_n: indicates falling edge on sig_in signal
Draw logic diagram and design this module.
Create edge_detector folder under your 09_ss9 folder. Copy any rtl/sim/tb folder from any previous practice.
Draw logic diagram (2points), design the edge_detector.v (3points) and write testbench to verify for it (5points).
clk pulse_out_p
rst_n
edge_detector
pulse_out_n
sig_in
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