DESIGN OF A CLOCK AND DATA RECOVERY CIRCUIT IN FDSOI

TECHNOLOGY FOR HIGH SPEED SERIAL LINKS

A Master Thesis
Submitted to the Faculty of the
Escola Tècnica d’Enginyeria de Telecomunicació de Barcelona
Universitat Politècnica de Catalunya
by
Hugo Ernesto Safadi Figueroa

In partial fulfillment
of the requirements for the degree in
MASTER IN ELECTRONIC ENGINEERING

Advisors: Diego Mateo Peña and Francesc Moll Echeto

Barcelona, March 2021
Abstract
The purpose of this thesis is to design an 8 Gbps clock and data recovery circuit intended
to work in the receiver of a high-speed Serializer-Deserializer interface (SerDes). The
proposed architecture is based on a phase-locked loop operation (PLL) that integrates a
linear phase detector, a charge pump, a wide-tuning range voltage-controlled ring oscillator
(2.5- 12 GHz), and a third order low pass filter that achieves a bandwidth of 150 MHz. A
wide loop bandwidth is considered in the design to achieve a high input jitter tolerance
and a fast locking time. Implemented in 22 nm FDSOI, the overall circuit draws 1.38mW
from a 0.8V power supply, exhibits a recovery clock RMS jitter of 0.970 fs and and requires
a locking time of 22 ns.
A Monte Carlo analysis has been performed applying temperature and voltage corners
of -40◦ C to 125◦ C and 0.72 V to 0.88 V respectively. The results indicated a 95.6%
success rate. By using an external voltage that has been implemented to adjust the phase
detector’s flip-flops bias current, 100% success rate is achieved.

Keywords
CDR, PLL, FDSOI, VCO, jitter, phase noise.

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Acknowledgements
I would like to thank my supervisors Diego Mateo and Francesc Moll, for all the help and
support that they gave me during this work.

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Revision history and approval record

Revision Date Purpose

0 26/02/2021 Document creation
1 01/03/2021 Document revision
2 05/03/2021 Document revision

DOCUMENT DISTRIBUTION LIST

Name e-mail
Hugo Ernesto Safadi Figueroa hugo.safadi@estudiantat.upc.edu
Diego Mateo Peña diego.mateo@upc.edu
Francesc Moll Echeto francesc.moll@upc.edu

Written by: Reviewed and approved by:

Date 02/03/2021 Date 05/03/2021
Name Hugo Ernesto Safadi Figueroa Name Francesc Moll i Diego Mateo
Position Project Author Position Project Supervisors

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Contents
List of Figures 6

List of Tables 7

1 Introduction 8
1.1 Project Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 State of the art 9

2.1 Clock Recovery overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 PLL clock recovery architecture design 11

3.1 Clock recovery from a random data signal . . . . . . . . . . . . . . . . . . 11
3.2 CDR Phase detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Alexander (bang-bang) detector . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Hogge detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.1 Singled ended input- differential output ring oscillator . . . . . . . 18
3.5 CDR loop analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 Phase Noise and jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.7 Random jitter quantification . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Circuit Design 26
4.1 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 Charge Pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3.1 Frequency tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.3.2 Phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4 Control loop design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.4.1 Frequency and step response . . . . . . . . . . . . . . . . . . . . . . 37

5 Simulations and Results 39

5.1 CDR tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Phase noise and RMS random jitter measurement . . . . . . . . . . . . . . 40
5.2.1 Phase margin effect on noise and settling time . . . . . . . . . . . . 41
5.2.2 Phase detector gain trade-off with jitter and settling time . . . . . . 43
5.2.3 Transferred data input jitter . . . . . . . . . . . . . . . . . . . . . . 44
5.2.4 PRBS clock recovery . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3 Monte Carlo simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.1 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

6 Conclusions and future development 52

References 54

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List of Figures
1 CDR block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 NRZ encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Transmitted NRZ data power spectrum . . . . . . . . . . . . . . . . . . . . 12
4 Edge detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Alexander phase detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Alexander detector truth table . . . . . . . . . . . . . . . . . . . . . . . . . 13
7 Hogge detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9 (a) Cascode configuration, (b) Gain boosted simplified topology, (c) Gain
boosted circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
10 Gain-boosted Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . 16
11 VCO Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
12 Current starved ring oscillator . . . . . . . . . . . . . . . . . . . . . . . . . 18
13 Single ended to differential phasors. . . . . . . . . . . . . . . . . . . . . . . 19
14 Single ended to differential ring oscillator circuit. . . . . . . . . . . . . . . 19
15 CDR linear model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Second order Type 2 PLL bode plot . . . . . . . . . . . . . . . . . . . . . . 21
17 Third order Type II PLL bode plot . . . . . . . . . . . . . . . . . . . . . . 22
18 Plot of natural frequency over crossover point versus damping factor for a
Type 2 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
19 Random Jitter distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
20 Folded CML D-latch circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 26
21 DFF with current source control implemented in Virtuoso Schematic Editor 27
22 Latch Output peak to peak voltage in function of the current source values 28
23 Hogge Detector circuit implemented in Virtuoso Schematic Editor . . . . . 28
24 Clock Lagging the data signal . . . . . . . . . . . . . . . . . . . . . . . . . 29
25 Charge Pump schematic and test-bench . . . . . . . . . . . . . . . . . . . . 30
26 Charge pump DC Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
27 Open loop charge pump load capacitance voltage . . . . . . . . . . . . . . 31
28 Ring oscillator single stage inverter with dummy load . . . . . . . . . . . . 32
29 ROSC circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
30 Ring oscillator phase noise at 8GHz . . . . . . . . . . . . . . . . . . . . . 34
31 ROSC frequency range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
32 ROSC 8GHz propagation delay . . . . . . . . . . . . . . . . . . . . . . . . 35
33 Ring oscillator output differential signal simulation . . . . . . . . . . . . . 36
34 CDR Linear Model in Simulink . . . . . . . . . . . . . . . . . . . . . . . . 37
35 Open loop and closed loop frequency response . . . . . . . . . . . . . . . . 37
36 System’s step response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
37 CDR schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
38 PLL tracking the clock signal of the input data . . . . . . . . . . . . . . . 40
39 CDR frequency tracking period and steady state . . . . . . . . . . . . . . 41
40 Clock phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
41 CDR transient response for increasingly phase margin . . . . . . . . . . . 42
42 Clock phase noise for increasingly phase margin . . . . . . . . . . . . . . . 43

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 43 Clock phase noise in function of current gain . . . . . . . . . . . . . . . . 44
44 Transient response for increasingly detector gain . . . . . . . . . . . . . . 45
45 Phase noise transfered input jitter at BW=125 MHz . . . . . . . . . . . . 46
46 PRBS data eyediagram and jitter . . . . . . . . . . . . . . . . . . . . . . . 46
47 Clock recovery of PRBS stream . . . . . . . . . . . . . . . . . . . . . . . . 47
48 CDR locked state of PRBS signal . . . . . . . . . . . . . . . . . . . . . . . 48
49 PRBS clock eyediagram and jitter . . . . . . . . . . . . . . . . . . . . . . 48
50 clock signal Monte Carlo . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
51 Monte Carlo steady-state best and worse cases . . . . . . . . . . . . . . . 50
52 Monte Carlo settling best and worse cases . . . . . . . . . . . . . . . . . . 50
53 Monte Carlo simulation at corner VDD =0.88V, T=125◦ C where the clock
frequency goes beyond 8GHz. Vclatch is adjusted from (a) 700 mV to (b)
500 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
54 Monte Carlo simulation at corner VDD =0.72V, T=-40◦ C where the clock
frequency does not reach 8GHz. Vclatch is adjusted from (a) 700mV to (b)
770 mV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Listings

List of Tables
1 Comparison of CDR designs reported in literature . . . . . . . . . . . . . . 10
2 BER and RMS jitter multiplier factor . . . . . . . . . . . . . . . . . . . . . 25
3 Simulated phase noise of the ring oscillator . . . . . . . . . . . . . . . . . . 34
4 Loop filter calculated component values and frequencies . . . . . . . . . . . 36
5 CDR control loop parameters . . . . . . . . . . . . . . . . . . . . . . . . . 39
6 Phase margin and jitter trade-off . . . . . . . . . . . . . . . . . . . . . . . 43
7 Simulated phase noise and jitter values when current gain is reduced . . . . 44
8 Simulated clock RMS and peak to peak jitter(BER =10−12 ) applying a
input data with 0.01UI jitter . . . . . . . . . . . . . . . . . . . . . . . . . 45
9 Monte Carlo corner values . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10 Current and power consumption for each block of the CDR . . . . . . . . 50
11 Comparison of CDR designs reported in literature and this work . . . . . 52

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1 Introduction
1.1 Project Background
This work is part of a current project, named DRAC and lead by the Barcelona Supercom-
puting Center, which aims to develop a RISC-V microprocessor. Particularly, this work
deals with the design at schematic level of an analog PLL-based clock and data recovery
circuit that is expected to operate at the receiver of a high-speed serial interface to serve
as a data transfer between the ASIC and an FPGA containing a DDR3 RAM interface
for main memory access.
The CDR design takes into consideration the specifications of a serial link transmitter
developed in [1] that serializes 8 differential data inputs using an 8 GHz sampling clock.
The transmitted data reaches a bit-rate of 8 Gbps with a maximum transmission fre-
quency of 4 GHz. At the receiver, the CDR must recover the 8 GHz clock to achieve the
deserialization process.
A fully depleted silicon over insulator (FDSOI) 22 nm process [2] is employed for this
design. This technology is based on an ultra-thin insulator layer, called buried oxide
(BOX) placed between the base silicon and the transistor thin-film channel. The buried
oxide minimize the parasitic capacitance between the drain and source and reduce the
current leakage due to the electron confinement inside the channel. This allows to achieve
high-speed operations with low power consumption and lower area occupancy.

1.2 Organization
This work is organized as follows:
Chapter 2 briefly overview the fundamentals blocks of an analog PLL-based CDR and
presents a compilation of reported designs found in literature, including their specifica-
tions.
In Chapter 3 different architectures for the CDR blocks are discussed and chosen following
certain design specifications relating the loop bandwidth, speed, noise performance, power
consumption and area. A basic theory of jitter and phase noise is also introduced.
In Chapter 4 each of the CDR blocks are designed at transistor level and simulated
individually in open loop situation. The loop filter components are designed and the
linear model for the control in open loop and closed loop is simulated using Matlab.
Finally, in Chapter 5 the operation of the closed loop control of the designed CDR is
simulated. Some design parameters of the CDR blocks are adjusted to meet with the
specifications and a Monte Carlo analysis is performed to test the circuit for process and
mismatch variations and validate the operation of the proposed design.

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2 State of the art

2.1 Clock Recovery overview

A conventional PLL-based CDR is formed by the following components:

Figure 1: CDR block diagram

Phase detector (PD): It performs the data edge sampling usually employing flip flops
that are synchronized by the reference local clock signal. It provides the phase
error signal that controls the VCO frequency. There are two main approaches to
implement a phase detector [3]. The first uses a linear detector, where its output
pulses average is linearly proportional to the phase error between the data and
the clock. The second approach uses a sequential detector which produces a binary
output that contains the direction of the phase error excluding the magnitude.
Charge pump (CP): This block takes the phase error signal from the detector and
converts them into current pulses that are fed into the loop filter to charge or
discharge the capacitance of the filter, consequently providing the right controlled
voltage to lock the clock frequency.
Voltage-controlled oscillator (VCO): It generates the clock signal and provides the
frequency tuning range of the CDR. One common implementation is the ring os-
cillator, formed by a chain of current-starved inverters in which the clock period is
determined by the delay of each stage. This architecture is also called a voltage-
controlled delay line and presents high stability, wide tuning range, and relatively
low jitter accumulation [4]. Other CDR implementations include LC tank oscillators
[5]-[6] providing high frequencies operation but poor tuning.
Loop Filter: The loop filter, which is generally based on a low pass filter (LPF) provides
the stability to the control loop and noise attenuation for high-frequency harmonics.
The key parameters requirement in CDR includes the generation of jitter, power consump-
tion, frequency range, input data jitter rejection capability and the input jitter tolerance.
There are several CDR designs reported for high frequency applications with strict gen-
erated jitter specification, for instance, a 1-16 Gbps all-digital CDR employing 65 nm
CMOS process presented in [7] reported a clock jitter of 0.019 times the unit interval

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(0.019 UI) and a power consumption of 80 mW. A CDR implementation employing 22
nm SOI process has been reported in [8], intended to operate during NRZ/PAM4 decoding
at 16 Gbps. This design presents a generated jitter of 1.92 ps at 8 GHz clock (0.03 UI). A
high jitter tolerance CDR design presented by Razavi in [9] works at 20 Gbps, reports an
input jitter tolerance of 2 UIpp at 5 MHz and a recovered clock generated jitter of 459 fs
since it uses a wide bandwidth of 170 MHz. Table 1 summarizes some of the CDR designs
reported with their specifications:

[7] [8] [9] [10]

Technology 22 nm SOI 65 nm 65 nm 45 nm
Voltage supply 0.8 V 1.2 V 1V 1V
Data rate 16 Gbps 1-16 Gbps 20 Gbps 25 Gbps
Frequency tuning - 4-8 GHz 18.6-21.6 12.25-
GHz 13.59 GHz
Filter bandwidth - - 170 MHz 6 MHz
Clock RMS Jitter 0.03 UI 0.19 UI 0.018 UI 0.075 UI
Jitter Tolerance - 0.2 UIpp 0.7 UIpp 0.3 UIpp
(BER=10−12 )
Power consumption 80 mW 87 mW 3 mW 4.97 mW

Table 1: Comparison of CDR designs reported in literature

For this work, the CDR is designed to have a wide frequency tuning range that allows
the operation with multi-Gbps serial link protocols such as: Aurora 8b/10b [11], requiring
baud rates of 1.25Gbps, 2.5 Gbps and 3.25 Gbps; CEI-6G with baud rates from 4.9 Gbps
to 6.4 Gbps [12]; and CEI-11G, with baud rates from 9.9 Gbps to 11.2 Gbps [13].
The RMS jitter generated by the CDR should be around 0.01 UI (1 ps for 8GHz clock),
following the PLL-CDR design criteria of [14].
Although other specification values are not initially defined, the desired performance char-
acteristics for the CDR design also includes a fast locking time, high noise immunity that
ensures a stable operation and a low power consumption.

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3 PLL clock recovery architecture design
A clock recovery system implemented by a phase locked loop as depicted in Figure 1,
synchronizes a self-generated reference clock signal with an input data bit stream by a
unity negative feedback in order to extract its clock signal. It is conformed by a phase
detector, a charge pump, a loop filter and a VCO.
The design of the PLL-based clock recovery circuit meets with the following operation
requirements:
1. Detection of random bit sequences at the input by sampling each data transition.
2. Wide loop bandwidth to improve jitter tolerance.
3. Wide VCO frequency tuning.
4. Fast time response at locking the clock signal with minimum tracking error.
5. High local oscillator phase noise rejection
6. Low power consumption and efficient area occupancy.

3.1 Clock recovery from a random data signal

In most high-speed serial links, data is transmitted in a NRZ format which consists of a
pseudo-random binary sequence with a bit time equal to the clock period Tb = 1/fclk . In
this type of encoding each bit has the same probability of being ‘0’ or ‘1’, therefore, it
is possible to have a long pulse train of ‘1’ or ‘0’ making the clock detection difficult to
achieve. The maximum signal frequency happens when the sequence is a series of alternat-
ing ‘1’ and ‘0’ and is equal to half the clock frequency (fN RZmax = fclk /2), as is illustrated
in Figure 2. This property allows data transmission using less channel bandwidth.
To illustrate the frequency properties of an NRZ signal, Figure 3 shows its frequency
spectrum in which it can be seen that the signal doesn’t carry energy at the fclk , neither
at its integer multiples frequencies. This property of the NRZ encoding has the drawback
that it makes the PLL unable to track the clock signal. A non-linear transformation has
to be applied to the signal in order to generate the clock frequency. A differential operator
(d/dt) doubles the pulse frequency by generating pulses in each transition of the signal.
A squaring operation converts the signal in only positive pulses [15].

Figure 2: NRZ encoding

The phase detector of a CDR is capable of performing this operation by sampling the
positive and negative edges of the data signal using the reference clock from the VCO,

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 Figure 3: Transmitted NRZ data power spectrum

generating a pulse at each sample. Figure 4 shows the basic edge detection principle in
a CDR consisting of a delay block that generates a version of the data signal delayed
by a clock period Tb , an exclusive-OR gate compares the original data signal its delayed
version identifying each transition and generating a pulse at the output.

Figure 4: NRZ data edge detection

3.2 CDR Phase detectors

In PLL-based CDR there are two types of PDs: Non-linear (sequential) and linear detec-
tors. In linear detectors, the pulse width of the output is proportional to the magnitude
of the phase error between the clock and the data, while non-linear detectors generate a
sequence of pulses with a fixed width that contains information about the direction of the
phase error, but not the magnitude. The most common implementation for a non-linear
detector is the Alexander or bang-bang detector, while for linear detectors, the commonly
used implementation is the Hogge detector.

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3.2.1 Alexander (bang-bang) detector
The Alexander phase detector (bang-bang) schematic is shown in Figure 5. It consists on
four D-flip flops that retime the data signal and two exlusive-OR gates that generates the
pulses containing the phase error between clock and data. The output pulses T and E
indicate whether the clock is early or late to the data and change with each positive clock
edge. The data can be sampled using the positive and negative edges of the clock, doubling
the sampling frequency. The decision making of the circuit requires a data sample at the
rising edge along with two previous samples. D-flip flop U1 provides the first data sample
on the rising data edge, U2 samples the previous data rising edge, while U4 provides the
sample on the previous negative edge. The diference between the two outputs provides
the error phase information. Decision making is presented in truth table of Figure 6.

Figure 5: Alexander phase detector

Figure 6: Alexander detector truth table

3.2.2 Hogge detector

A Hogge detector is a linear phase detector that generates two output signals: A propor-
tional signal with a varying-pulse-width (U P ) and a reference fixed pulse-width signal
(DOW N ).
The input data Din is connected to the D-flip flop (U1) and to the exclusive-OR gate
(U2). U1 samples the data with the rising edge of the reference clock CK and generates a

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delayed input signal D1 . Din and D1 are compared by the exclusive-OR gate U2 producing
a pulse waveform on each transition of the bit stream. The phase difference, which can
be represented as the position in which the clock samples the data determines the width
of the pulses, have a range that goes from 0 to TCK /2 when the clock is leading the data
signal and TCK /2 to TCK when the clock lags the data signal.

Figure 7: Hogge detector

A second D-flip flop (U3) synchronized by the inverted clock signal samples the delayed
input data D1 and generates D2 . Since the phase difference between D1 and D2 will be
one half of the clock period TCK /2, the second exclusive-OR gate (U4) will generate a
waveform with a fixed TCK /2 pulse-width (DOW N ) at each data transition, being this
the reference signal regarding the varying pulse-width proportional signal.
Although non-linear detectors have good performance at high speeds, they occupy more
area and dissipate more power than linear detectors.
For this work, the Hogge linear detector is considered as it can work at the required speed
along with power and area efficiency. Moreover, a linear model for the control loop is
plausible.

3.3 Charge Pump

A charge pump is a pull-up pull-down circuit that converts the pulses generated by the
phase detector into current pulses that are fed by the loop filter capacitor whose output
voltage controls the VCO.
One of the challenges in designing a charge pump circuit is the current mismatch that
is produced during the current switching due to the transconductance difference between
the NMOS and PMOS devices, along with the drain-source voltage differences generated
by the filter’s capacitor charge and discharge.
One approach to decrease current mismatches is by using a CMOS gain-boosted technique
that increases the circuit’s output impedance using a cascode structure. Moreover, requires
low power dissipation and the bandwidth is not highly limited as it only uses one high
gain amplification stage, which is suitable for high speed applications [16].
A cascoded structure formed by M1 and M2 is depicted in Figure 9.a where the output
impedance across M1 drain is given by Rout = gm2 r02 r01 . An amplification stage (A1) is

14
 Figure 8: Charge pump

added to the circuit as it is shown in Figure 9.b where the transistor M1 is represented by
its resistance r01 . The M2 source node feeds the amplifier’s negative port while its output
feeds the gate of M2 . A1 amplifies and regulates Vx incurring in smaller deviations in the
output current across M1 increasing the output impedance without staking more cascoded
transistors which maintains a low power consumption. The resultant output impedance
for this topology is Rout = gm2 A1 r02 r01 .

Figure 9: (a) Cascode configuration, (b) Gain boosted simplified topology, (c) Gain boosted circuit

An implementation for A1 is given by a NMOS transistor M3 biased by an ideal current

source as is shown in Figure 9.c. The amplifier gain is A1 = −gm3 r03 thus, Rout =
gm2 gm3 r01 r02 r03 .
Finally, the charge pump circuit is formed by two cascode gain boosted NMOS and PMOS
amplifiers working complementary as depicted in Figure 10. The transistors M1 , M2 , M3
forms the negative feedback for PMOS path, while M4 , M5 , M6 forms negative feedback
for NMOS path. The current sources driving M3 and M6 are formed by the current mirrors
M7 and M8 .

15
 Figure 10: Gain-boosted Charge pump (From reference [16])

3.4 VCO
The VCO is a key component for the CDR since it determines the operation frequency
of the CDR. Some design considerations have to be taken in order to adapt the CDR
operation requirements, among them: Low power consumption, wide frequency tuning
(1 to 12 GHz), low area occupancy and low oscillation phase noise.
There are two types of VCO that are most commonly used for high speed applications:
LC-tank oscillators and ring oscillators.
LC-tank oscillators are resonators based on inductor-capacitance networks with a high
noise rejection and low jitter. In addition, it has a high quality factor and hence, it can
operate at very high frequencies. However, it has a narrow frequency tune and occupies
larger area than a CMOS ring oscillator.
Ring oscillators (ROSC) are composed of a chain of an odd number of CMOS inverters
that relies its operation in the charge and discharge of the output loads at each stage. The
output frequency generated can be tuned by an amount of delay of each stage: decreasing
the stage delay would increase the frequency. A ring oscillator presents a higher phase
noise than LC oscillators, due to leakage current at the delay cells and high static leakage
power [17]. Nevertheless, ring oscillators are capable of a wide frequency tuning, low power
consumption and less area occupancy than LC tanks.
There are several techniques that modify the ring oscillator frequency range performance,
one of them is the current starved ring oscillator which is convenient to be implemented
in CDR applications.

16
 Figure 11: (a) Differential LC-tank oscillator, (b) Single-ended 3-stage ring oscillator

A current starved ring oscillator (CSROSC) employs current mirrors at each delay stage
to control the current that charge and discharge the capacitive loads of each inverter
output, thus controlling the delay of each stage. This configuration allows to have a wider
and precise frequency tuning.
The control voltage acts as bias voltage for current mirror transistors which create a
variable bias current for each stage that controls the frequency of oscillation, as is depicted
in Figure 12. PMOS current mirror transistors P1, P3 and P5 operates as current sources
while the NMOS current mirror transistors N1, N3 and N5 operates as current sinks.
As mentioned before, the oscillation frequency is inversely proportional to the delay of
each stage, the total delay of the oscillation will depend on the number of inverters in the
ring, thus the frequency can be defined as:
1
fo = (1)
NT
Where N is the number of stages and T is the time delay.
The delay can be separated in charge time (t1 ) and discharge time (t2 ). If we defined Ct
as the total load capacitance, I as the bias current, then we can define the oscillation
frequency as:

1 I
fo = = (2)
N (t1 + t2) N CtVDD
Where VDD is the supply voltage

17
 Figure 12: Three-Stages Current starved ring oscillator

3.4.1 Singled ended input- differential output ring oscillator

As the input data coming from the transmission line is a differential signal, the phase
detector design considers differential D-flip flops. Hence, the clock signal generated by the
VCO must be also differential. The advantages of working with differential topologies are
their high rejection to common voltage noise, substrate and voltage supply noise, besides
their low noise transfer to external circuits. However, a differential ROSC dissipates more
power, occupies a larger area and its output voltage swing is more limited than single
ended circuits. Due to this trade-off, it is decided to maintain a single-ended configuration
adapted to have a differential output. The technique used for this adaptation is proposed
in [18]. To illustrate the operation principle of a single ended to differential converter, each
stage node waveforms can be approximated to sinusoidal signals in order to represent them
as phasors as its illustrated in Figure 13. The phase difference between them is given by
each stage inverter phase shift and its propagation delay (π − φp ). Assuming that the
propagation delay is same in each stage, these phasors are interpolated to generate two
resultant signals with the same amplitude and opposite direction.
Figure 14 shows the schematic of a five-stage differential output ring oscillator. A PMOS
differential couple acts as a comparator and level shifter that generates the differential
representation of the single ended signal Vo1 and Vo2 . The inputs Vin1 and Vin2 are coming
from the interpolated nodes through resistors R1 to R6 . An additional inverter stage is
short-circuited to generate a half amplitude reference Vref.
Assuming that we used the same value for each resistor, interpolated voltages are repre-
sented by:
1
Vin1 = (Vp1 + Vp2 + Vp4 ) (3)
3
1
Vin2 = (Vp3 + Vp5 + Vref ) (4)
3

18
 Figure 13: Inverter stage phasors

Figure 14: Single ended to differential circuit

Combining equation (3) with the sinusoidal versions of each node phasor, Vin1 and Vin2
can be defined as:

Vin1 = Vref + Va sin(ωt) Vin2 = Vref − Va sin(ωt + θ) (5)

3.5 CDR loop analysis

A linear model for a PLL-based CDR is depicted in Figure 15 where each component is
expressed in the frequency domain and the phase is the control variable.
The stability analysis of the system is given by the open loop transfer function between
the reference and input phase and is defined as:

φout (s) Kpd Kvco

T (s) = = F (s) (6)
φin (s) s

19
 Figure 15: CDR linear model

Where Kpd and Kvco are the phase detector gain and the VCO gain respectively.
Since the VCO works as a linear voltage/frequency converter, taking the control voltage
defined by the phase error and adjusting its frequency oscillation proportionally to the
phase, acts as an integrator, contributing with a pole at the origin.
The phase detector along with the charge pump transforms the phase error ∆φ from the
detector into current pulses Icp with proportional width following the expression:

∆φ
∆t = Tck (7)
2π
Where ∆t is the current pulse-width and Tck is the clock period.
If the loop filter is formed by a single capacitor Cp the relation between the increment in
voltage and the pulse-width ∆t is expressed as:
Icp Icp ∆φ
∆Vc = ∆t = Tck (8)
Cp 2πCp
Assuming that the phase error occurs at t=0, for each period of time a linear approxima-
tion is made to express Vc as a function of t as follows:
Icp φ
Vc (t) = u(t)t (9)
2πCp

Where the unit step response u(t) = 1 at t ≥ 0.

The frequency domain transfer function of the voltage is obtained by doing the Laplace
transform over the derivative of dVc (t)/dt resulting in:

Vc (s) Icp Kpd

H(s) = = = (10)
∆φ s2πCp s
We can obtain the current transfer function from Equation (10) defining the loop filter
impedance Z(s) = 1/sC:

20
 I(s) Vc (s) Icp
= = (11)
∆φ Z(s) 2π
With a single capacitor the open loop transfer function contains two poles at the origin
(Type II - 1st order PLL), making the system unstable since the phase angle will be -180◦
at the crossover frequency. Adding a resistor in series with the capacitor provides a zero
located at ωz = 1/Rp Cp, stabilizing the control operation with a phase margin of 90◦ (see
Figure 16).
Modifying the current transfer function for a 2nd order RC filter we obtain:

I(s) Icp Rp + sCp

= (12)
∆φ 2π sCp

Figure 16: Second order Type two PLL loop filter (a) circuit schematic (b) frequency response

A 2nd order type II PLL presents significant drawback: each time the charge pump injects
current towards the R − Cp network, the control voltage (Vc ) across Cp can’t change
instantaneously at each charge and discharge due to the voltage drop in R, incurring in
voltage jumps, even during locked condition [19]. This jumpy effect is worsened with the
mismatch between the U P and DOW N current pulses. The resulting ripple creates large
deviations in the VCO frequency, and it increases the clock jitter. In order to reduce that
effect, a second capacitor C2 is connected in parallel to the R − Cp network, as is depicted
in Figure 17, filtering the voltage ripple. Nevertheless, the drawback of adding a second
capacitor is the addition of a third pole to the loop control, putting the system stability
at risk, for this reason the components must be designed carefully.
Modifying the current transfer function for a 3rd order loop filter we obtain:

s
I(s) Icp (1 + ωz
)
= s (13)
∆φ 2πs(Cp + C2 ) (1 + ωp
)

21
Where the pole and zero frequencies are:

1
ωz = (14)
Cp Rp
Cp + C2
ωp = (15)
Cp C2 Rp

Thus, the open loop transfer function for a third order-type two PLL is defined as:
s
Kpd Kvco (1 + ωz
)
T (s) = s (16)
s(Cp + C2 ) (1 + ωp
)

The bode plots are shown in Figure 17: the 0-dB crossover frequency is placed between the
zero, located at lower frequencies, and the pole, located at higher frequencies in order to
have enough
q phase margin. A distance ”k” factor between the pole and the zero frequencies
ωp
(k = ωz
) can be related with the phase margin φP M following an approximation for
third order PLL defined in [20]-[21] :

  12
1 + sin(φP M )
k= (17)
1 − sin(φP M )

Figure 17: Third order Type two PLL loop filter (a) circuit schematic (b) frequency response

Another parameter to be analyzed is the damping factor represented by ξ. This parameter

is useful to set the settling time of the frequency step response and the stability of the
system. ξ can be determined by the relation between resonance frequency and the 0-dB
crossover frequency which can be approximated through a mathematical model presented
in [15] for type II PLLs which describes the curve depicted in Figure 18 where the reso-
nance frequency fn normalized to a crossover frequency f0dB versus the damping factor

22
ξ is plotted. From the curve, we can deduce that when the resonance and crossover fre-
quency are close to each other, the damping ratio decreases, and therefore the frequency
response will present more oscillations before the steady-state, increasing the settling time
and worsen the stability of the control (shorter phase margin). On the other hand, the
further apart these frequencies are between them, the damping ratio is increased, stabi-
lizing the system (larger phase margin) and decreasing the settling time. Nevertheless,
an overdamped system (values from 0.8 to 1.5) degrades the optimum control speed to a
slower response [22].

Figure 18: Plot of natural frequency over crossover point versus damping factor for a Type II PLL
(from reference [15])

For third order PLLs the damping ratio can be approximated as it is shown in [23] :

− ln Mp
ξ=q (18)
ln Mp 2 + π 2

Where Mp is the step response’s overshoot at the peak magnitude.

In PLL applications the loop filter used can be either active or passive. For clock recovery
applications it is more convenient to use a passive filter as it generates less jitter due to
the fact that the noise it contributes is only thermal due to the components. In an active
filter, in addition to thermal noise, the flicker noise (1/f ) of the transistors increases with
the gain of the circuit [24].

3.6 Phase Noise and jitter

Considering the spectral density of a signal modulated periodically in frequency, the
phase noise is defined as the signal’s sideband power in a 1-Hertz bandwidth at a certain
frequency offset from the signal’s carrier frequency. We can refer the signal side-band
as the noise power density. In the time domain the phase noise is represented as fast,
short term fluctuations on the periodicity of the waveform, commonly called jitter. These

23
deviation on the PLL-CDR output signal’s phase can be caused by self-generated random
and deterministic noise sources and by external noise present in the input data signal.
In clock recovery loops the output clock jitter is produced by the ripple in the control
voltage for the VCO caused by current mismatches in the charge-pump, the fluctuations
on the power supply lines, edge detection errors produced in the PD, the noise generated
by the substrate and so on. All these noise sources are considered deterministic since
their origin is located in the circuit. In addition, there are random fluctuations which
more difficult to determine. An example of this can be the thermal noise generated by
active components on the circuit.
Another jitter source that the CDR needs to deal with is found in the input data signal
as it is transmitted by a noisy medium before arriving to the receiver. The jitter embed-
ded in the input contains several frequency components, producing slow and fast phase
deviations. CDRs with narrowband loop filters will reject the high frequency component
of the input data. This property is called jitter transfer, representing the amount of jitter
capable of being suppressed by the clock recovery. A good jitter transfer will produce a
“clean” clock output.
Another effect to consider is the CDR’s jitter tolerance. As the low frequency components
are not suppressed, some of the input jitter is inherited by the output clock. When sam-
pling the data edges in the phase detector the clock keeps up with the input data as they
share the same jitter, this maintain a certain stability in the system by not incurring in
false detections. However, for a narrowband CDR high frequency jitter is not transferred
to the recovered clock which can incur in false edge detections. Having a wideband loop
filter increases the maximum amount of input jitter that can be tolerated by the CDR
before incurring in detection errors.

3.7 Random jitter quantification

The random periodic jitter (RJc ), given by uncorrelated noise sources, defines the vari-
ations of the periodic signal from its mean value. As the number of period samples in-
creases, the jitter value tends to increase following a normal distribution curve as is shown
in Figure 19.

Figure 19: Random jitter distribution. σ= RMS value.

24
The RMS jitter (RJRM S ) represents 1σ deviation of the probability distribution, which
occupies around 34.1% of the jitter samples, counting from each side of the mean value µ.
The the peak to peak jitter Jpp value represents the 100% of the normal curve. However, it
is an unbounded value since it may increase with the number of jitter samples. Therefore, it
is necessary to establish a range according to a system bit error rate (BER) specification.
This gives the total jitter budget of the CDR, where any sample that falls out of the
required range will incur in a bit error. The wider the jitter range, the more tolerance
the CDR shows to the various random jitter source in a communication link. In high
speed SerDes links, a usual BER of 10−12 is required, meaning that, in order to obtain the
maximum jitter budget it is necessary, in principle, to sample 1012 clock periods. However,
it is possible to approximate the jitter value by employing a factor that multiplies the
sigma at each side of the mean value (±N σ) according to the BER specification [25]. As
it is shown in Table 2 :

BER N
10−3 6.18
10−6 9.507
10−9 11.996
10−12 14.698

Table 2: BER and RMS jitter multiplier factor

The RMS and the peak to peak values are usually expressed as a fraction of a data bit
stream unit interval (UI), which is generally equal to the bit time.

25
4 Circuit Design
This chapter presents the design process of the CDR by describing the operation of each
component circuit and showing its isolated behavior. The simulations are done employing
the Cadence ADE simulator. For the control modeling, Matlab-Simulink is employed to
generate the frequency and step response of a third-order second type PLL control. All
the designs are made considering the FDSOI flipped well architecture [26].

4.1 Phase Detector

The Hogge detector is implemented using two differential D flip-flops based on current
mode logic D-latches proposed in [27]. This design allows the flip-flop to operate at voltages
lower than 1 V since its folded topology uses fewer stacked transistors. Moreover, it has
a good performance at high frequencies and low power consumption. Figure 20 shows
a folded CML latch. The clock signal is connected to the PMOS differential pair M1 -
M2 driving a current Iss towards the current mirrors formed by transistors M7 -M9 and
M8 -M10 . The NMOS pair M3 -M4 samples a data bit while the couple M5 -M6 holds the
data bit since their gates are cross-connected with M3 -M4 , creating positive feedback. The
loads represented by RD determines the voltage swing at the drain nodes of the NMOS
transistors.

Figure 20: Folded CML D-latch circuit [27]

As it shown in [28] the minimum voltage supply for this topology can be defined as:

Vswing
VDDmin = + VT H + 2VOV (19)
4
Where Vswing is the peak to peak output voltage:

Vswing = 2ISS RD (20)

VT H and VOV are the transistor’s threshold voltages and overdrive voltages respectively.

26
In FDSOI 22nm technology with a flipped-well body bias architecture, VT H value is around
0.25 V while the supply voltage is 0.8 V. To preserve a good performance of the latch,
the swing voltage should be set around 0.5 V [28].
In order to design a master-slave D-flip flop from the CML latch, two folded latches can
be combined by sharing the clock PMOS differential pair as depicted in Figure 21.
The latch current source is designed using a multiple current mirror circuit controlled by
an external voltage pin Vclatch that allows us to control the latch voltage swing and hence,
to adjust the sampling speed and power dissipation during the CDR circuit testing.

Figure 21: Master-slave DFF with current source control implemented in Virtuoso Schematic Editor

Figure 22 shows the DFF operation with different Vclatch voltages: 0.6, 0.7 and 0.8 V as
well as different generated ISS current values: 47.6 µA, 61.6 µA and 71.4 µA. For this
simulation RD was set with 12 kΩ. It can be seen that the voltage swing increases along
with ISS , going from 0.49 V to 0.6 V. Within this range the flip flop can operate correctly.
The glitches at the output Q0 are generated during the differential clock switching where
both signals coincide at a common voltage that does not reach the PMOS differential pair
threshold, which implies a drop in the current that feeds the current mirror transistors.
Consequently, the drain voltage of the NMOS that receive the data pulses tends to rise
towards VDD . However, since the clock signal crossovers happens in a short period of time
the NMOS drain voltage’s surges are not high enough to alter the operation of the circuit.
Figure 23 shows the implementation in Cadence of the Hogge detector schematic previ-
ously depicted in Figure 7.
The voltage applied on the Vclatch external pin is 0.75 V resulting in VQo1 peak−peak = 0.57
V and a ISS = 61.6 µA.

27
 Figure 22: Latch Output peak to peak voltage in function of the current source values

To simulate the pulse-width variation of the output signals U P and DOW N due to the
phase error between the input data and the reference clock, a periodic pulse waveform
with a period of TData =250 ps is phase-shifted from the clock signal who has half of the
data period TCK =125 ps.
Figure 24 shows the U P pulse-width variations in proportion to the magnitude and direc-
tion of phase error, while DOW N pulses is used as reference and maintains a fixed pulse
width equals to TCK /2.
When the data signal leads the clock by 20 ps (-0.16π phase shift) the pulse-width of
the U P output decreases to Tck /2 - 20 ps = 42.5 ps as it shows Figure 24.a. This leads
the charge pump to decrease the charging periods of the loop filter’s capacitor and con-

Figure 23: Hogge Detector circuit implemented in Virtuoso Schematic Editor

28
 Figure 24: (a) Data signal leads the clock by 20 ps , (b) Data signal lags the clock signal by 20 ps

sequently, it decreases the control voltage which slows down the clock frequency until the
phase difference is corrected.
In the other case shown in figure 24.b, the data signal lags the clock signal by 20 ps
(+0.16π phase shift), the U P output will increase to Tck /2 + 20 ps= 82.5 ps. Now, the
charging times longer than discharges, which increases the control voltage and hence,
speeds up the clock frequency until it reaches the data phase.
These open loop simulations of the designed phase detector describes the operation when
there are small phase shifts between the data input and the reference, which is equivalent
to the locked state of the PLL in closed loop. However, during the frequency tracking
period, the Hogge detector works as a frequency detector, and depending on the design
settings, one of the possible drawbacks is the detection of harmonics of the target fre-
quency. This can occur due to several causes: distortions on the output signal of the
latch, noise coupled from the supply lines or substrate lines or slow risings are falling
edges which incurs in failed edges samples.
In closed loop operation, which is analyzed in Chapter 5, these errors can be mitigated
by adjusting the Iss current employing the external control voltage Vclatch .

4.2 Charge Pump

Figure 25 shows the schematic for the proposed CDR’s charge pump based on a cascode
gain-boosted topology. The phase detector’s U P signal is connected to the gate of tran-
sistor P1, while DOW N is connected to the gate of N1. When U P pulses come out from
the detector, P1 starts steering a current towards the loop filter capacitor, charging it.
DOW N pulses out from the detector turn on the transistor N1, allowing the capacitor
to discharge. The single-stage amplifier P2 along with P5 form the gain-boosted circuit
that increases the output impedance and hence, improving the current matching as was

29
described in the previous chapter. The current sources for the amplification stage are
formed by P0-P3 and N0-N4 current mirrors.

Figure 25: (a) Charge-Pump schematic circuit, (b) block Test-bench

Figure 26 shows the DC simulation of the charge pump output currents sweeping the
output voltage from 0 to 800 mV. The width of the transistors P1, P5, N1, N3 are adjusted
to generate a maximum charge and discharge current of 70 µA, which will decrease during
the voltage swept until both currents intercept at 67 µA, when the output is 420 mV,
which is the steady-state voltage in open loop.

Figure 26: DC simulation of the charge pump output currents

The operation of the charge pump is tested in open loop by connecting two periodic
8GHz signals in phase with each other and with a 50% duty cycle, simulating the U P
and DOW N pulses of the phase detector. A load capacitance of 2.2 pF is connected at
the output.
By setting the initial condition of the capacitor voltage to 0 V, the PMOS path will
starts injecting current into the load until it reaches a threshold voltage of 420 mV as it

30
is depicted in Figure 27.a. At that instant, the NMOS path start draining current from
the capacitor during the discharge periods. As the difference between the charge and
discharge currents approaches zero, the output voltage will begin to reach steady state
value at around 0.6 µs. Figure 27.b. shows the steady-state from 0.698 µs to 0.7 µs, the
voltage across the capacitor presents a ripple due to the charge and discharge periods
with peak to peak magnitude that reaches 2 mV.

Figure 27: (a) Open loop charge pump load capacitance voltage (b) Voltage ripple in steady state

The amplitude of the output voltage ripple depends on the frequency of the input pulses,
its capacitive load and the output currents, following the equation:

IL ∆t
∆V = (21)
CL

Where IL is the current flowing through the load, ∆t is the charge and discharge period
determined by the U P and DOW N pulse-width and CL is the output capacitance. It
is convenient to have a low ripple at the output considering that in closed loop, the
feedback control take place on the CDR and the voltage ripple will generate variations
in the output frequency, and depending on the sensitivity of the VCO, this ripple can
be significant at the accumulation of jitter. Higher currents will generate a larger ripple,
and hence, more frequency variations. Nevertheless, it will reach the target voltage faster
(shorter settling time). On the other hand, smaller currents will produce less frequency
variations, improving the output jitter but it will take a longer time to reach the PLL
steady state (longer settling time).

4.3 VCO
A current starved five-stage ring oscillator with differential output is designed to have a
wide frequency tuning range and low phase noise, following the CDR requirements. Fig-

31
ure 28 presents a single inverter stage for the ROSC. The current starved VCO allows the
control of the propagation delay due to the charge and discharge of the gate capacitance
of each inverter’s output by adjusting the bias voltage of current source transistor P1 and
the current sink transistor N2. The devices were designed to provide a fixed current of
100 µA at each stage. An inverter dummy load is connected at the output to have a load
symmetry for all stages.

Figure 28: Ring oscillator single stage inverter with dummy load

As was mentioned in the previous chapter, a single-ended with differential output config-
uration its considered for the ring oscillator circuit. Figure 29 shows the final schematic
made in the Cadence editor. The resistances that form the interpolating network are set
to 11.5k Ω, while the load resistance of the PMOS differential pair which determines the
output voltage swing is set to 20k Ω. The bias voltage of the differential circuit’s current
source is controlled by a PMOS current mirror that generates a 90 µA bias current. Finally,
the differential output Vo1 and V02 are connected to CMOS inverter buffers which drives
a larger capacitive load that increases the voltage swing and minimizes the propagation
delay.
Figure 33 depicts the ring oscillator differential output signals simulation. The common-
mode voltage reference Vref is not constant since each inverter node signal is not exactly
sinusoidal as it was approximated in theory. This implies small variations on the interpo-
lated signals Vin1 and Vin2 . Nevertheless, the output voltage presents good symmetry and
a large voltage swing, around 0.65 V. Finally, the output buffers are made by two CMOS
inverters to amplify the output signals, generating the output clock signals.

32
 Figure 29: Ring oscillator circuit schematic

4.3.1 Frequency tuning

Figure 31 shows the VCO transfer function plot simulation. The linear region obtained in
the simulation determines the frequency tuning range, going from 2.5 GHz to 11.5 GHz.
The control voltage range goes from 250 mV to 400 mV. The linear factor of this region
describing the VCO gain is calculated by the slope of the line ∆f/∆V = 70 GHz/V.
The required oscillation frequency for synchronizing the clock is generated with 340 mV
control voltage. Figure 32 shows the propagation delay between two oscillator’s internal
node signals oscillating at 8 GHz, which was found to be tp =12.37 ps.

4.3.2 Phase noise

ROSC phase noise is generated mostly by the slow rising and falling edges at the nodes
of each inverter, increasing the jitter, the sensitivity to supply voltage variations, and
difficulties to maintain a 50% duty cycle. However, this effect can be minimized by resizing
the current starved transistors which control the speed of the rising and falling edges. The
increase of current injected by the current mirrors speed up the charge and discharge of
each inverter node, improving the jitter. Nevertheless, the power consumption area also
increases. In Figure 30, the simulation of the phase noise generated by the proposed
five-stage current starved ring oscillator is shown.
The measured phase-noise shows a slope of about 30-dB/dec at lower frequencies, pro-
duced by flicker noise (1/f noise) [15]. A break point offset frequency at around 10 MHz
(flicker corner frequency) drops the slope from 30 to 20-dB/dec until the curve flattens at
around 8 GHz defining the thermal white noise produced in the oscillator.
The jitter value, calculated from the phase noise plot within the integration limits from
1K to 10GHz, gives a value of 0.3ps RMS.

33
 Figure 30: Ring oscillator phase noise at f=8 GHz

Offset Phase Noise(dBc/Hz)

100kHz -32
1MHz -62.5
10MHz -88.6
100MHz -112

Table 3: Simulated phase noise of the ring oscillator

4.4 Control loop design

For the design of a linear control model for a third-order, type two PLL-CDR the following
process is considered:
1. Selection of the 0-dB crossover frequency of the system and the required phase
margin φP M , following the design criteria of chapter 3.
2. Obtaining the k factor derived from the phase margin, employing the Equation (17)
in order to estimate the distance between ωz and ωp .
3. Estimation of the filter component’s values using the open loop transfer function
T (s).
As a first attempt, we set the crossover frequency (f0−dB ) at 100MHz to have wide band-
width that allows the CDR to have a high jitter tolerance and fast signal tracking. How-
ever, this value is adjusted according to the phase noise simulations in chapter 5.
For the phase margin we define 35◦ , following the design criteria of [29] that suggests that
for PLL applications, phase margins greater than 30◦ ensure a stable operation. From the
defined phase, the pole and zero frequencies can be located using as reference the k factor

34
 Figure 31: Ring oscillator frequency tuning range

Figure 32: Propagation delay of one ring stage oscillating at fo=8 GHz

estimated in Equation (17). Giving a value of 1.92.

In order to obtain the filter’s component values, it is assumed that the crossover frequency
is located between the zero and pole to ensure the desired phase margin: ωz < ωc < ωp .
Then, the magnitude of the open loop gain T (s) is evaluated at the crossover frequency,
|T (jωc )|=1 as follows:
p
Icp Kvco 1 + (ωcRp Cp )2
|T (jωc )| = p =1 (22)
2π(Cp + C2 )ωc2 1 + (ωc/ωp)2

Since Cp + C2 ≈ Cp :
p
Icp Kvco (ωc Rp Cp )2 Icp Kvco Rp
|T (jωc )| ≈ ≈ =1 (23)
2πCp ωc2 2πωc

35
 Figure 33: Ring oscillator output differential signal simulation

From previous analysis of the phase detector gain (Kpd ), and the VCO gain (Kvco ) were
obtained:
Icp
Kpd = 2π
= 10.8µA/rad
∆V
Kvco = ∆f
= 7x1010 Hz/V
By calculating Rp from Equation (22) and if Cp is set arbitrary
q to an initial value of 2.2
wp
pF we can calculate C2 relating equation (14) with k = wz as follows:

Cp
C2 = (24)
k2−1

Then, the zero and pole frequencies are calculated employing equations (14) and (15).
Table 4 summarizes the calculated filter components and the obtained frequencies:

Cp 2.2 pF
C2 0.77 pF
Rp 1 kΩ
fc 100 MHz
fz 70.4 MHz
fp 211 MHz

Table 4: Loop filter calculated component values and frequencies

36
4.4.1 Frequency and step response
Given the parameters obtained from the equations of the 3rd order filter, a linear model
is created in Matlab employing the open loop transfer function T (s) to simulate the
frequency and step response of the loop control as it is shown in Figure 34.

Figure 34: CDR Linear Model in Simulink

Figure 35 (a) and (b) depicts the magnitude and phase bode plots for open loop and
closed loop operation respectively. The resonance frequency is located at about 80 MHz,
which represents 0.8 times the crossover frequency, resulting in a damping factor around
0.4 (according to the curve of Figure 18)

Figure 35: Frequency response simulation for (a) open loop, (b) closed loop

The step response presented in Figure 36 gives information about the settling time and

37
overshoot at the resonance frequency. This parameters are described by the damping ratio
ξ and it depends on the phase margin.

Figure 36: System’s step response Matlab simulation

For a 35 degree phase margin the simulation’s results shows an overshoot of 53% and
settling time of 19.3 ns. The damping ratio is calculated employing Equation (17) which
gives a value of 0.4, corroborating the previous estimation from the fn /f0 vs ξ curve.
In summary, the linear model defined in this chapter is intended to have a fast tracking
operation, keeping the control stability with an underdamped loop control. However, in
the next chapter, this theoretical model is simulated and the trade-offs between the phase
margin, settling time, area occupancy and noise performance will be analyzed, incurring
in the adjustment of the filter parameters to improve the system.

38
5 Simulations and Results
In this chapter, the closed-loop control of the proposed CDR circuit shown in Figure 37 is
verified by applying two types of input data signals: a 4 GHz pulse wave with 50% duty
cycle and a pseudo-random bit sequence (PRBS) with a bit rate of 8 Gbps. The simulation
results are focused on the analysis of the settling time, the recovered clock phase noise,
and the data input jitter rejection capability under different loop bandwidths. Circuit
design adjustments are implemented in order to have a generated RMS jitter in the clock
less than 1 ps (0.016UI) and an input tolerance jitter of at least 0.24 UIpp of the data
signal. Finally, a Monte Carlo simulation is performed to test the circuit under process
variation and mismatches.
The initial parameters of the CDR control loop are summarized in Table 5:

Bandwidth 122 MHz

Phase margin 35◦
Detector gain 10.8 µA/rad
VCO gain 70 GHz/V
Target frequency 8 GHz

Table 5: CDR control loop parameters

Figure 37: CDR schematic implemented in Cadence

5.1 CDR tracking

Figure 38 shows the CDR frequency tracking response of a 4 GHz input pulse-wave with a
50% duty cycle. An initial condition for the simulation is established by setting the voltage
at the filter’s capacitance node (Vosc ) to 0.25 V, which is the threshold voltage that drives

39
the ring oscillator’s current starved transistors, starting up the 3 GHz clock frequency
that feeds the input and samples the edges of the data signal pulses. The Hogge detector
produces the phase error signals (U P and DOW N ) between the sampled data edges and
the reference clock. Subsequently, the charge pump converts the error signals into current
pulses that adjust the charge of the filter’s capacitance increasing the control voltage until
the oscillator reach the 8 GHz target frequency at 347 mV. The CDR recovers the clock
frequency, requiring a settling time of approximately 30 ns.

Figure 38: CDR frequency tracking

Figure 39.a shows the CDR tracking period, where the detector’s DOW N signal keeps
a reference pulse-width equals to the clock’s half period, producing a 68 µA discharge
current, while the U P signal varies its pulse-width adjusting the charge current. When the
CDR locks the clock frequency, the charge and discharge pulses are balanced, producing
a 136 µA peak to peak current pulse-wave that flows through the loop filter. The filter’s
capacitance generates a control voltage peak to peak amplitude of 5 mV, leading to an
output frequency steady-state error of ∆fclock =1 MHz as it shows in Figure 39.b To
quantify the amount of jitter due this frequency variations at the locked state (among
other noise sources), phase noise simulations are performed in the following section.

5.2 Phase noise and RMS random jitter measurement

Since the input data stream is an ideal signal with no jitter, we can obtain the clock
phase noise generated exclusively by the CDR circuit, where the factors that contribute

40
 Figure 39: (a) Phase error pulses during the frequency tracking, (b) CDR during the locked state

predominantly to the noise generation are the phase deviations between the internal nodes
of the ring oscillator, the amplitude of the ripple in the control voltage given by the charge
pump current, the variations in the power and ground lines and the loop filter’s bandwidth.
Figure 40 shows the 8 GHz clock signal’s phase noise giving a value of -114 dBc/Hz at
10 MHz offset frequency. By using the ADE PNoise analysis and considering a frequency
range from 10 KHz to 10 GHz, a 1.14 ps RMS jitter is obtained.

Figure 40: Output clock phase noise

5.2.1 Phase margin effect on noise and settling time

By increasing the phase margin, the damping ratio of the transient response increases.
Hence, the settling time shortens as it is shown in Figure 41. Moreover, a larger margin
implies a wider separation between the pole and zero frequencies. When the pole is shifted

41
to higher frequencies, its distance from the natural frequency widens and the noise over-
shoot decreases as it is shown in Figure 42. Nevertheless, the filter noise bandwidth is also
increased, allowing higher frequencies noise sources to be transferred to the output clock.
The resulting jitter, settling time and filter components dimensions are summarized in
Table 6.

Figure 41: CDR transient response for increasingly phase margin

In summary, larger phase margins improves the CDR tracking speed and control stabi-
lization as the noise bandwidth increases (higher noise immunity). The drawback is the
addition of generated jitter in the output clock. Particularly, setting the phase margin
to 55◦ the clock jitter is increased up to 1.20ps (0.02UI) and the settling time decreases
from 30ns to 11.6ns which is reasonable operation trade-off. However, one approach to

42
 Figure 42: Clock phase noise for increasingly phase margin

φP M Settling time RJRM S R C2 Cp

35◦ 30 ns 1.14 ps 1.2KΩ 0.77 pF 2.2 pF
45◦ 27 ns 1.16 ps 1.2KΩ 0.65 pF 2.5 pF
55◦ 11.6 ns 1.20 ps 1.2 KΩ 0.5 pF 2.8 pF
65◦ 11 ns 1.25 ps 1.2 KΩ 0.1 pF 3 pF

Table 6: Phase margin and jitter trade-off

reduce the generated jitter without slowing significantly the CDR tracking speed is by
moderately reducing the phase detector gain.

5.2.2 Phase detector gain trade-off with jitter and settling time
The trade-off between phase detector gain over the clock jitter relies on the fact that
lowering Kpd the control voltage ripple reduces along with the clock frequency deviations,
reducing the generated jitter. Nevertheless, the settling time, as it was mentioned in
the chapter 5, is increased since that with less charge injection, maintaining the same
charge/discharge periods, the capacitor’s charge will take more time to reach the voltage
that locks the target frequency.
In the following simulations, the charge/discharge currents are dropped from 68 µA to 40
µA (Kpd from 10.8 µA/rad to 6.4 µA/rad), leading to a phase noise reduction of 4 dB over
the frequency range until the control loop crossover frequency as depicted in Figure 43
and a lightly slower frequency tracking with a settling time of 12.6 ns as Figure 44 shows.
Table 7 summarizes the generated jitter and settling time trade-off as the current is

43
 Figure 43: Clock phase noise in function of the current gain

decreased:
[Icp µA] φP M Kpd Phase noise@10MHz RJRM S Settling time
68 µA 55◦ 10.8 µA/rad -114 dBc/Hz 1.20 ps 11.6ns
40 µA 55◦ 6.4 µA/rad -118 dBc/Hz 970 fs 12.2ns

Table 7: Simulated phase noise and jitter values when current gain is reduced

The generated jitter in the recovered clock jitter could be reduced down to 970 fs (0.015
UI) lowering the current to 6.4 µA/rad. The settling time increases to 12.2 ns which
doesn’t affect significantly the CDR tracking speed.
Now, we will take into consideration the transfer of the input jitter to the output clock,
where the design trade-off will rely on the input rejection towards the input tolerance.

5.2.3 Transferred data input jitter

To observe the CDR input jitter rejection capability, the input pulse wave is distorted
with a 0.08 UI jitter (10 ps RMS).
Figure 45 shows the input data noise rejection tested for loop 3 dB cutoff frequencies
of 70 MHz, 122 MHz and 150 MHz (maintaining a 55◦ phase margin) within the offset
frequency range from 10 KHz to 10 GHz. The results shows a 3 dB input noise attenuation
for all bandwidths within the offset frequency region from 10 KHz to the cutoff frequency.
Table 8 summarizes the measured RMS and peak to peak jitter (BER =10−12 ) for each
case.
From the simulation results depicted in the table above, it can be concluded that as the
filter bandwidth increases it allows more jitter injection to the recovered clock. Neverthe-
less, letting the clock acquire part of the input jitter improves the immunity or tolerance

44
 Figure 44: Settling time for increasingly detector gain

BW RJRM S RJpp Settling time

70 MHz 1.27 ps 18.7 ps 52 ns
122 MHz 1.42 ps 20.8 ps 40 ns
150 MHz 1.59 ps 23.4 ps 22 ns

Table 8: Simulated clock RMS and peak to peak jitter(BER =10−12 ) applying a input
data with 0.01UI jitter

to noise, speeds up the locking time, and makes the system more stable. This is consistent
with the fact that by making the bandwidth larger, the pole is shifting to high frequencies,
increasing the phase margin, as was analyzed in the previous section. The jitter budget
of the clock (RJpp ), is measured for a BER = 10−12 and it represents the maximum jitter
transferred so that it does not incur a bit error. For the design to approach the perfor-
mance objectives, a bandwidth of 150 MHz is considered, allowing a settling time of 22
ns, a jitter budget of 23.4 ps.
With the selected bandwidth the filter component’s values are adjusted to: C2 = 430 fF,
Cp = 1.8 pF and R=880 Ω
To estimate the maximum jitter tolerance, a jitter mask should be generated [30]. A jitter
tolerance mask relates the input jitter sinusoidal frequency with the input jitter amplitude
(UI) that can be tolerated by the CDR. One approach to achieve this measurement is
defined in [31] that modulates the input data phase with a sinusoidal generator, employing
a range of jitter frequencies. In this work, we don’t include the calculation of the tolerance
jitter mask, leaving it as a future enhancement for design characterization.

45
Figure 45: Input data and output clock phase noise plots with CDR bandwidths of 70 MHz, 122 MHz
and 150 MHz

5.2.4 PRBS clock recovery

The CDR is now tested with a PRBS input with a data rate of 8 Gbps, 150 MHz loop
bandwidth and a 6.4 µA/rad phase detector gain. The input data is distorted with a jitter
of 10 ps RMS (0.08 UI). Figure 46 shows the eye diagram and the jitter histogram of the
input data signal where it can be observed a peak to peak value of approximately 30 ps
(±1.5σ) which represents 0.24 UIpp

Figure 46: (a) PRBS input data eye diagram using 400 period samples, (b) jitter histogram extracted
from the eye diagram

Figure 47.a shows the clock frequency recovered from the PRBS input, it can be noticed
that the settling time is increased to about 40 ns due to the variable duty cycle in a PRBS
stream. Knowing that the edge samples will catch the NRZ frequency when the data bit
stream is a periodic waveform with 50% duty cycle, a initial (”1010...”) sequence with

46
a duration equal to the maximum CDR settling time (22 ns) is applied before the data
transmission starts.

Figure 47: (a) Recovered clock frequency from PRBS input. Setling time 40 ns, (b) Recovered clock
frequency from PRBS input with initial periodic sequence. Setling time 22 ns

Once the CDR locks the clock frequency, the control voltage maintains the average 347
mV value with a 5 mV ripple. However, during long bit sequences of ’0’ or ’1’, the phase
detector output pulses are constant and ’shifted 180 degrees’ between them since there
is no data edge transitions during this time. The charge and discharge paths are off,
maintaining the control voltage roughly stable over 344 mV, resulting in a 7,9 GHz clock
frequency as it is shown in Figure 48. The output clock jitter is now measured in a
transient simulation where its eye diagram is obtained with period samples during the
locked time as seen in Figure 49.a. From the clock period samples the jitter histogram
shown in Figure 49.b the total peak to peak jitter can be approximated to 9.7 ps (0.16
UIpp ).

5.3 Monte Carlo simulation

The mismatch and process variation of the CDR final design applying Vclatch =700mV is
analyzed with 250 samples of a Monte Carlo simulation shown in Figure 50, bounded by
temperature and supply voltage corners described in Table 9:

Min Nominal Max

VDD [V] 0.72 0.8 0.88
T[◦ C] -40 27 125

Table 9: Monte Carlo corner values

47
 Figure 48: CDR locked state of a PRBS input

The output clock frequency is simulated applying a 4 GHz periodic pulse-wave connected
to the data input. Of the 250 samples, 11 did not achieve the 8GHz frequency locking
(4.4% error). Selecting the accomplished simulations, we can determine the CDR operation
constrains.
For the frequency response steady-state error, the best case simulation gives a frequency
variation of 20 MHz peak to peak, while in the worse case, the variation is around 300
MHz peak to peak as it is shown in Figure 51.
For the frequency response settling time, the best case simulation gives a result of 15 ns
(VDD =0.88 V, T=125◦ C), while the worse case simulation presents a settling time of 65
ns (VDD =0.72 V, T=-40◦ C), as it is depicted in Figure 52.

Figure 49: (a) Recovered clock data eye diagram using 975 period samples, (b) jitter histogram
extracted from the clock eye diagram

48
 Figure 50: Recovered clock Monte Carlo simulation. 250 samples

The circuit dependency on VDD variation relies on the fact that a higher supply voltage
will generate an increment on the saturation current of the NMOS and PMOS charge
pump branches, leading to a faster filter’s capacitance charge/discharge and hence, a
higher control voltage ripple. As consequence, the control is more likely to enter in an
unstable condition where the CDR can incur fake detections to lower frequencies. On the
other hand, a lower supply voltage will provoke the opposite effect: lower charge/discharge
currents makes the tracking slower, and so as the detector gain decreases the control loop
can incur fake detections at lower frequency.
The VDD and temperature variations can be overcome by adjusting the latch control
voltage which regulates the sampling speed; if a faster tracking leads to fake detection
to higher frequencies, Vclatch is decreased, compensating the detection speed as it shows
Figure 53. If a slower CDR tracking leads to fake detections to lower frequencies, Vclatch
is increased as it is shown in Figure 54.
From the above simulations, it can be concluded that controlling Vclatch allows us to avoid
detection errors. By decreasing V Vclatch , the CDR slows down, preventing detections to
higher harmonics of the target frequency detections while increasing Vclatch speeds up the
CDR, preventing detections to lower harmonics of the target frequency.

5.3.1 Power consumption

Table 10 lists the current and power consumption for each block of the CDR and the total
value:

49
 Figure 51: Steady-state worse and best cases

Block I (mA) P (mW)

Phase detector 0.43 0.34
Charge pump 0.14 0.11
VCO 1.17 0.94
TOTAL 1.73 1.38

Table 10: Current and power consumption for each block of the CDR

Figure 52: Settling time worse and best cases

50
Figure 53: Monte Carlo simulation at corner VDD =0.88 V, T=125◦ C where the clock frequency goes
beyond 8 GHz. Vclatch is adjusted from (a) 700 mV to (b) 500 mV

Figure 54: Monte Carlo simulation at corner (VDD =0.72 V T=-40◦ C) where the clock frequency does
not reach 8 GHz. Vclatch is adjusted from (a) 700 mV to (b) 770 mV

51
6 Conclusions and future development
In this work, we have designed an analog PLL-based clock recovery circuit implemented
in a 22 nm FDSOI technology that is able to track an 8 Gbps input data bit-stream
with a settling time of 22 ns and a generated jitter in the recovered clock that reaches a
maximum of 0.016 UI (970 fs RMS).
The CDR phase detector is implemented as a linear detector based on CML flip-flops
that, along with a gain-boosted charge pump, generates a current/error-phase gain of 6.4
µA/rad.
The VCO has been designed as a five-stage, current-starved ring oscillator with a singled
ended to differential output topology that achieves a frequency tuning range from 2.5
GHz to 12 GHz, allowing the operation with multi-Gbps systems protocols such as Xilinx-
Aurora, CEI-6G and CEI-11G.
The loop filter consists of a passive low pass filter for a 3rd order type II PLL with a
bandwidth of 150MHz. The simulation results indicates that the filter rejects the input
transferred jitter down to 9.7 ps RMS (0.16 UI) when an input data distorted with 0.24
U Ipp jitter is applied. Furthermore, the 150 MHz bandwidth allows a recovered clock jitter
budget of 23.4 ps for a BER = 10−12 .
Table 11 summarizes the operation characteristics of the proposed CDR in comparison to
the state of the art designs.

This work [7] [8] [9] [10]

Technology 22nm SOI 22nm SOI 65nm 65ns 45nm
Voltage supply 0.8 V 0.8 V 1.2 V 1V 1V
Data rate 8 Gbps 16 Gbps 1-16 Gbps 20 Gbps 25 Gbps
Frequency 2.5-12 GHz - 4-8 GHz 18.6-21.6 12.25-13.59
tuning GHz GHz
Filter 150 MHz - - 170 MHz 6 MHz
bandwidth
Clock RMS 0.016 UI 0.03 UI 0.19 UI 0.018 UI 0.075 UI
Jitter
Jitter Tolerance - - 0.2 UIpp 0.7 UIpp 0.3 UIpp
(BER=10−12 )
Power 1.38 mW 80 mW 87 mW 3 mW 4.97 mW
consumption

Table 11: Comparison of CDR designs reported in literature and this work

From this design, the following conclusions have been reached:

1. In a 3rd order type II PLL filter, as the separation between the pole (located at
higher frequencies) and the zero (located at lower frequencies) increases, the phase
margin, that defines the stability of the closed-loop operation, also increases. This
implies a more damped step response and shorter settling time. Therefore, the linear

52
 control model intended to work with a 35◦ phase margin was modified during the
simulations to work with a 55◦ phase margin, improving the system stability and
achieving a faster clock recovery with a settling time of 11.6 ns.
2. The recovered clock RMS jitter generated by the CDR could be attenuated down
to 970 fs by decreasing the charge pump output current from 68 µA to 40 µA. This
adjustment increased marginally the 11.6 ns settling time up to 12.2 ns.
3. The design of the loop filter’s 3-dB cutoff frequency determines the trade-off between
the input jitter transfer and input jitter tolerance. Narrow bandwidths will allow
having a stronger input noise attenuation. However, it slows down the frequency
tracking and the stability can be compromised when very noisy inputs make the
CDR increase its BER. If the input signal is expected to be a fairly clean signal, a
narrow bandwidth will be convenient. On the other hand, wider bandwidths allow
the CDR to have more immunity or tolerance to the noise embedded in the input
signal, as well as increasing the tracking speed. However, the output clock will
present more noisy behavior. For the final design, a wide bandwidth (150 MHz)
was implemented to achieve a clock jitter budget of 23.4 ps under a BER = 10−12
condition and a settling time of 22 ns, assuming an input signal with 0.024 UIpp
jitter.
4. The simulated power consumption shows an improvement from the state the art
design specifications. The circuit dissipates 1.38mW, two times less than the lowest
power consumption specified in the literature.
5. A Monte Carlo simulation of 250 samples has been performed employing 6 statistical
corners where the VDD and temperature were varying. 4.4% of the simulation failed
to recover the clock at the target frequency. Nevertheless, an external control voltage
for the phase detector has been implemented to adjust the current that feeds the
latches of the flip flops to regulate the detection speed and compensate the process,
power supply and temperature variations that lead to failed detections to lock in
the right frequency for all simulated cases.
As future development the CDR jitter tolerance will be characterized by implementing
a phase-modulated PRBS where a sinusoidal jitter signal with a defined frequency range
modulates the data. The tolerance will be obtained by the CDR response to the different
jitter frequencies.
The layout of the CDR will be designed. New simulations will be performed including
the parasitics extracted from the layout and some design parameters will be adjusted if
necessary to improve the circuit performance.

53
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List of terms and abbreviations
CDR: Clock and data recovery.
PLL: Phase locked loop.
VCO: Voltage controlled oscillator
ROSC: Ring oscillator
CSROSC: Current-starved ring oscillator.
RJ: Random jitter.
UI: Unit interval.
PRBS: Pseudo random bit sequence.
BER: Bit eror rate.
FDSOI: Fully-depleted silicon on insulator
CML: Current mode logic.
BW: Bandwidth.
RMS: Root mean square.
SERDES: Serializer-Deserializer
NRZ: Non return to zero.
CP: Charge pump.
PD: Phase detector.
FPGA: Field programmable gate array.
DDR: Double Data Rate.
RAM: Random access memory
ASIC: Application-specific integrated. circuit
ADE: Analog design environment.

57