Everything you wanted to

know about RISC-V

Paolo Bonzini
November June 2024
 What is RISC-V?
●
A new(ish) RISC-based instruction set and
architecture
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Started in 2010 at UC Berkeley
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Should simple, clean, easy to understand…
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… while supporting a wide range of applications
 Timeline
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2011: ISA specification published, now CC-BY
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2012: first physical processor tapeout
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2014: “Instruction sets should be free”
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2015: RISC-V Foundation formed
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2017: GCC and Linux port upstream
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2019-2020: basic and privileged ISA frozen
 Vendors
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SiFive (Berkeley)
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NVIDIA, Western Digital
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FPGA vendors, e.g. Xilinx (AMD)
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Rivos, Ventana
 What does it look like?
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Overall similar to MIPS or SPARC
– 3-operand instructions
– Limited size for immediates
– Memory operand available only for loads and stores
– No processor flags, including carry bit
– No 8- and 16-bit arithmetic and comparisons
●
Suitable for position independent code
 Hello, world!
.data
hello: .ascii "Hello world!\n"
.text
.globl _start
_start:
li a0, 1 # load immediate
lla a1, hello # load local address
li a2, 13
li a7, 64 # write
ecall
Li a0, 0
li a7, 93 # exit
ecall
 Hello, world!
.data
hello: .ascii "Hello world!\n"
.text
.globl _start
_start:
addi a0, zero, 1
auipc a1, %pcrel_hi(hello) # load high 20 bits
add a1, a1, %pcrel_lo(hello) # adjust low 12 bits
addi a2, zero, 13
addi a7, zero, 64 # write
ecall
addi a0, zero, 0
addi a7, zero, 93 # exit
ecall
 32 general purpose registers
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1 zero (zero, x0)
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12 callee-save (s0-s11, x8/x9/x18-x27)
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8 arguments (a0-a7, x10-x17)
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7 caller-save (t0-t6, x5-x7/x28-x31)
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4 “special” (ra, sp, gp, tp, x1-x4)
 Hello, world!
.data
hello: .ascii "Hello world!\n"
.text
.globl _start
_start:
addi x10, x0, 1
auipc x11, %pcrel_hi(hello) # load high 20 bits
add x11, x11, %pcrel_lo(hello) # adjust low 12 bits
addi x12, x0, 13
addi x17, x0, 64 # write
ecall
addi x10, x0, 0
addi x17, x0, 93 # exit
ecall
 Privileged architecture
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“Control and status registers” (CSR)
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Three operating modes (plus hypervisor)
– Machine, Supervisor, User
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Three interrupt sources
– Software interrupt, timer interrupt, external interrupt
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Each mode can delegate interrupts and
exceptions to the lower privilege
 Main privileged instructions
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CSR access
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EBREAK (breakpoint)
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ECALL (call higher level)
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MRET / SRET (return to S or U respectively)
 Important CSRs
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Processor information ●
Exception cause and
(M only) saved PC
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Processor status ●
Timer and cycle
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Interrupt state counter
(pending/enabled) ●
Page table address
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Scratch register
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Exception vector
 SBI (Supervisor Binary Interface)
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Standard interface to M mode
– Timers
– Power management
– IPIs
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Accessible with ECALL from supervisor mode
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Open source implementation: OpenSBI
 Kernel world switch
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Swap user tp with ●
Restore registers
sscratch (CSRRW) from stack (incl. sp)
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tp is now per-CPU base ●
Swap kernel tp with
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Load kernel stack sscratch
pointer ●
Execute SRET
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Save registers to kernel
stack
 Extensions
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Modular design with optional extensions
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Example: RV64IMAFD
– 64-bit, full Integer ISA
– M = Multiplication/division
– A = Atomic operations + LL/SC
– FD = Floating point support (32-/64-bit)
 Extensions
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1x RV64IMAC
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1x RV32IMFC
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4x RV64GC_Zba_Zbb
– G = IMAFD
– Zba / Zbb = bit manipulation
instructions
 More on extensions
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Zname – because 26 extensions are not enough
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Xname – vendor-specific
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Sname – privileged extensions
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Zicsr and Zifencei – almost universal
– CSRs might not be present on low-end hardware
– ifence.i added after ratifications
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C – compressed encoding
 Memory order
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s390, x86: total store ordering
– Store-load can appear reordered to other CPUs
– Load-load, load-store, store-store preserved
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ARM, PPC: relaxed memory order
– Manually specify acquire and release relationship
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RISC-V: relaxed unless Ztso is present
 Compressed encoding
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16-bit instructions for higher code density
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About half of the instructions can be
compressed
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8% fewer bytes than x86-64, 28% fewer bytes
than ARMv7
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But...
 Compressed encoding
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No instruction alignment
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Uses ¾ of the encoding space
11
31 0
00 01
10

15 0
 More extensions
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Packed SIMD in general purpose regs (P, Zp*)
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Vector (V, Zv*)
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Bit manipulation and crypto (Zb*)
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Control-flow integrity (Zicfi*)
 Why so many extensions?
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Original designers’ idea was to justify every
instruction quantitatively
– Also they didn’t know OSes very much
– Examples: Zacas (atomic compare-and-swap,
LL/SC was considered enough), Zihintpause
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New applications, e.g. BF16 floating point
 Why so many extensions?
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Original idea was to use macro-op fusion
– Detect pairs of compressed of instructions
– Decode them as a single instruction
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Didn’t quite work out
– Zba: address generation (shift-by-1-and-add)
– Zicond: rs2 != 0 ? rs1 : 0, rs2 == 0 ? rs1 : 0
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It can only get worse
 Enter profiles...
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Profiles describe a baseline set of extensions
– RVA22 = Application processors, 2022
– RVM23 = Microcontrollers
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Coming next: RVA23, RVB23
– RVA = General purpose OS (e.g., Fedora)
– RVB = Custom OS (e.g. Yocto)
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Example difference: H (hypervisor extension)
 How to try it?
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HiFive boards cost several $100
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Most cheap boards don’t run mainline kernel
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QEMU (also supports dozens of extensions)
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fedoraproject.org/wiki/Architectures/RISC-V
/Installing still in progress
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Contacts: Richard Jones, Andrea Bolognani