American International University- Bangladesh (AIUB)

Faculty of Engineering (EEE)

Course Name: Digital Logic and Circuits Lab Course Code: EEE 2210
Semester: Spring 2021-22 Sec: F
Experiment No 7
Experiment Name Implementation of Asynchronous and synchronous counters using flip-flops.
Submission March 29,
Group No. 3 Date: 2022

Sl. Student ID: Student Name:

1. 19-39512-1 Foisal Ahmed
2. 19-40142-1 Imrul Hasan Sabid
3. 19-40200-1 Iebho Mohajan
4. 19-40189-1 Suborna Sharmin Mishu
5. 19-40026-1 Asif Iqbal Anik
6. 19-40159-1 Jahid Hasan

Submitted to:
Dr. Md. Jahid Hasan
Faculty Member, EEE
American International University-Bangladesh
Title: Implementation of Asynchronous and synchronous counters using flip-flops.

Introduction:
Counters are combinations of flip-flops arranged so that they can remember how many clock
pulses have been applied over some specified interval. Counters are classified into two broad
categories according to the way they are clocked: asynchronous and synchronous. In
asynchronous counters, commonly called ripple counters, the first flip-flop is clocked by the
external clock pulse and then each successive flip flop is clocked by the output of the preceding
flip-flop. In synchronous counters, the clock input is connected to all of the flip-flops so that
they are clocked simultaneously. The objective of this experiment was to design the following
counters using J-K Flip-Flops (IC 74LS76)
(a) n-bit Binary Asynchronous Counter
(b) n-bit Binary Synchronous Counter

Theory and Methodology:

Asynchronous counter
A three-bit asynchronous counter is shown in the figure 1. The external clock is connected to
the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of
each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of
FF0. Because of the inherent propagation delay through a flip-flop, the transition of the input
clock pulse and a transition of the Q output of FF0 can never occur at exactly the same time.
Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous
operation.

Figure 1 shows a timing diagram for the counter. The value of Q0 toggles once each clock
cycle. The change takes place shortly after the positive edge of the Clock signal. The delay is
caused by the propagation delay through the flip-flop. Since the second flip-flop is clocked by
Q0, the value of Q1 changes shortly after the negative edge of the Q0 signal. Similarly, the
value of Q2 changes shortly after the negative edge of the Q1 signal. If we look at the values
Q2Q1Q0 as the count, then the timing diagram indicates that the counting sequence is 0, 1, 2,
3, 4, 5, 6, 7, 0, 1, and so on. This circuit is a modulo-8 counter. Because it counts in the upward
direction, we call it an up-counter.

Figure 1: 3-bit Asynchronous counter and its timing diagram

A 3-bit flip-flop arrangement counter can count the states up to 23 – 1 i.e., 8-1 = 7. The process
of counting can be understood with the help of the step-by-step table given below:
 Table 1: Truth table of step-by-step counting process of a 3-bit asynchronous flip-flop

Synchronous counter
In synchronous counters, the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).
The most important advantage of synchronous counters is that there is no cumulative time
delay because all flip-flops are triggered in parallel. Thus, the maximum operating frequency
for this counter will be significantly higher than for the corresponding ripple counter.

Table 2 shows the contents of a four-bit up-counter for eight consecutive clock cycles,
assuming that the count is initially 0. Observing the pattern of bits in each row of the table, it
is apparent that bit Q0 changes on each clock cycle. Bit Q1 changes only when Q0 = 1. Bit Q2
changes only when both Q1 and Q0 are equal to 1. In general, for an n-bit up-counter, a given
flip-flop changes its state only when all the preceding flip-flops are in the state Q = 1.

Table 2: contents of a four-bit up-counter for eight consecutive clock cycles

T0 = 1

T1 = Q0
T2 = Q0Q1
T3 = Q0Q1Q2
T4= Q0Q1Q2Q3
·
·
·
Tn = Q0Q1 ···Qn−1

The Circuit diagram of a four-bit counter based on these expressions is given in Figure 2 (a).
Figure 2 (b) gives a timing diagram. It shows that the circuit behaves as a modulo-16 up-
counter. Because all changes take place with the same delay after the active edge of the Clock
signal, the circuit is called a synchronous counter.
 Figure 2 (a): A four-bit Synchronous Up Counter

Figure 2 (b): The timing diagram of a four-bit Synchronous Up Counter

Apparatus:

• IC 74LS76 (JK Flip Flop)

• IC 7408 (AND Gate)
• LED Lamps or Display
• Trainer Board
• Oscilloscope
• Connecting Wires
Simulation and Measurement:
Part 1: 3-bit Asynchronous Counter

Figure 3: Simulation circuit diagram of a 3-bit Asynchronous counter

Output of the Counter:

Figure 4 (a): Simulation output of the running 3-bit Asynchronous counter

Figure 4 (b): Simulation output of the running 3-bit Asynchronous counter

Part 2: 3-bit Synchronous Counter

Figure 5: Simulation circuit diagram of a 3-bit synchronous counter

Figure 5 (a): Simulation output of the running 3-bit synchronous counter

Figure 5 (a): Simulation output of the running 3-bit synchronous counter

 Questions with answers for report writing:

1. Design of a 4-bit Asynchronous Up- Counter.

Figure 6: Simulation circuit of 4-bit Asynchronous Up- Counter

2. Design of a 4-bit Synchronous Up- Counter.

Figure 7: Simulation circuit of 4-bit Synchronous Up- Counter

Output:

Figure 8: Output of the simulated circuit of 4-bit synchronous Up- Counter

Bonus Question Answers:
1. Design of a 3-bit Asynchronous down counter.

Figure 9: Simulation circuit of 3-bit Asynchronous Down- Counter

2. Design of a Mod 10 Synchronous up counter.

Figure 10: Simulation circuit of Mod 10 Synchronous up counter

Output:

Figure 11: Output of the simulated circuit of Mod 10 Synchronous up counter

Discussion and conclusion:
The main objectives of this experiment were to be familiar with J-K flip-flop, to know the
working principle of J-K flip-flop and to know how flip-flop can be used to design a counter.
At the very beginning of this experiment the core concept of flip-flop was discussed. The
difference between asynchronous and synchronous counter was also distinguished. After that
the timing diagram and clock cycle table was explained for both asynchronous and
synchronous counter. Then the hardware implementation part started.

In the hardware implementation part, we faced difficulties to generate the clock pulses from
the trainer board. We implemented the circuit but because of not having a clock generator we
could not bring out the output of the implemented circuits. We kept trying doing this and that
but nothing changed. At the end it was decided not to include the hardware part in the report.

In the simulation part 3-bit asynchronous and synchronous counter was designed following the
lab manual and by running the circuit the output was checked. Besides, 4-bit asynchronous and
synchronous up counter was also simulated using MULTISIM online version as toggling the
logic state in MULTISIM online version is easy and efficient. 3-bit asynchronous down
counter and MOD 10 synchronous up counter was also designed as well. All the simulation
circuit were run and the output were matched with the theoretical knowledge. No discrepancy
was found in the output values.

As we now know about flip-flop and how they can be used to design counter, also we were
able to design the 3-bit and 4-bit asynchronous and synchronous counter and also the Mod 10
synchronous up counter using flip-flop; it can be said that the objectives of this experiment
have been accomplished successfully.

Reference(s):

[1] Thomas L. Floyd, “Digital Fundamentals”, Ninth Edition.

[2] “Asynchronous Counter” Source: https://electronicscoach.com/asynchronous-counter.html

[3] “Synchronous Counter” Source: https://www.electronics-tutorials.ws/counter/count_3.htm

[4] “MOD 10 Synchronous Counter” Source: https://www.geeksforgeeks.org/design-mod-n-

synchronous-counter/