VHDL: SIMULATION AND SYNTHESIS MODEL

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design (PVL204) 1
SIMULATION MODEL

 VHDL has been designed from the start as a simulation language.

 An understanding of the language must come from examining the

behaviour of a VHDL simulator.

 The basis of VHDL simulation is event processing.

 All VHDL simulators are event-driven simulators.

 There are three essential concepts to event-driven simulation:

• Simulation time
• Delta time
• Event processing

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 2
SIMULATION TIME

 During a simulation, the simulator keeps track of the current time that
has been simulated. This time is known as the simulation time.

 The simulation time is usually measured as an integral multiple of a basic

unit of time known as the resolution limit.

 The simulator cannot measure time delays less than the resolution limit.

 For RTL simulations, there is no need to specify a fine resolution since

we are only interested in clock-cycle by clock-cycle behaviour and the
transfer functions are described with zero or unit time delay.

 It is important to note that the resolution limit is a characteristic of the

simulator, not of the VHDL model. It is usually controlled by a simulator
configuration setting.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 3
EVENT PROCESSING AND PROCESS EXECUTION

 The simulation cycle alternates between event processing and process

execution.

 The, signals are updated as a batch in the event processing part of the
cycle, then processes are run as a batch in the process execution part.

 The signal updating and process execution are kept completely

separate.

 This is how VHDL models concurrency such that it can be modelled

on a sequential computer processor without having to use multiple
processors or threads.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 4
EVENT DRIVEN SIMULATION

 When a signal assignment is performed,

• the target of the assignment is not updated immediately by the assignment;
• in fact it keeps its old value for the remainder of the process execution
phase.
• Instead, the assignment causes a transaction to be added to a queue of
transactions associated with the driver of the signal.

 For example:
a <= '0' after 1 ns, '1' after 2 ns;

 It is also possible to have a zero-delay assignment:

a <= '0';

 Even when there is no time delay the signal is not updated immediately,
since the transaction will be scheduled for the next delta cycle.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 5
EVENT DRIVEN SIMULATION

 Event is the transition is in the signal

• Trigger computation
• Can be on inputs / internal signals

 We use event driven simulation for the simulation of a combinational

circuit.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 6
SIMULATION OF SEQUENTIAL CIRCUITS

 Simulation for a sequential circuit

• Suppose input is changing quite a bit ( say changing every 1 ns)
• the clock frequency is 100 mega hertz, i.e., time period is 10 ns.

 An input is changing after every 1 ns. But, the flip flop is going to be
active every 10 ns.

 Example: Sequential circuit have a register, combinational circuit and

a register.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 7
SIMULATION OF SEQUENTIAL CIRCUITS (CONT.)

 Cycle based Simulation

• In a sequential circuit, simulator compute the value on the every active
clock edges that is called the cycle based simulation.

 Simulation Time
• Event time at which computation happens
• Events are ordered chronologically
• Note, simulation time is not a real time, it is a time taken by the simulator

 The events are ordered in the chronological order or in the simulation

time.

 Example: Simulation of a 2-input AND gate. The inputs are some

wave forms with changes at 100 ns, 200 ns and 300 ns.
• The simulator know the order of events like 100, 200, 300.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 8
SIMULATION CYCLE TIMING

 Example: Suppose AND gate is driving another NOR gate.

 Simulation trigger for the above circuit due to

• Input events: 100ns (110 to 010), 200ns and 300ns
• Internal signal events

 The simulator as it simulate new events happen in the internal signal

that is pushed in at the appropriate place in the correct order.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 9
SIMULATION CYCLE TIMING

 Example: Suppose AND gate is driving another NOR gate.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 10
SIMULATION TIMING: ISSUES

 In functional/logic simulation, if elements have zero delay.

• Delta delay for resolving zero delay problem.
• Events (on external signals and one happen on internal signals due to
computations) are ordered in simulation time and are handled in the same
order.

 How small the delta delay for simulation implementation?

• Smaller than the smallest delay in the circuit.
• Smaller than smallest change in any input signal.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 11
SIMULATION TIMING: ISSUES

 Only inputs in sensitivity list

• In response to an event on any of the inputs (in sensitivity list), process
computes from top to bottom once.
• Even if the order of assignments match the data flow, each assignment
use value of inputs at current simulation time, though the output are
assigned after delta delay.
• To force a process computation, in response to assignment of value to
internal signal, internal signals should be included in the sensitivity list.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 12
PROCESS – CONCURRENT STATEMENT

 A concurrent statement is equivalent to a process with signals in the

RHS of the concurrent statement, in the process sensitivity list.

 When a combinational block is coded in a single process, all the input

signals and all internal signals should be in the sensitivity list.

 This is required as the assignment happens at (t+delta) time for an event

at ‘t’ and the subsequent statements use the value of internal signals at
time ‘t’.

 A process could be equivalently written with multiple concurrent

statements.

 In real cases, multiple concurrent statements and multiple process works

concurrently, responding to various events on inputs or internal signals.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 13
SYNTHESIS MODEL

 The VHDL has been designed as a simulation language without regard to

the needs of synthesis or any other application area.

 Synthesizers make an interpretation of the language.

 This interpretation is based on mappings of special VHDL constructs

onto hardware with equivalent behaviour.

 These special constructs are known as templates

 The mapping is not always straightforward-

• Some VHDL constructs have direct one-to-one mappings to hardware
equivalents
• Many constructs have no possible hardware equivalents, at least within the
confines of logic synthesis, and these will cause errors during synthesis.
Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 14
TEMPLATES

 Constructs have to meet specific constraints in order to be

mappable.

 Synthesizers imposes these constraints on the use of the language

so that only VHDL constructs that have hardware equivalents can
be used.

 Templates
• Simple registers
• Registers with asynchronous reset
• Registers with synchronous reset
• Latches, RAMs, ROMs
• Tristate drivers
• Finite-state machines

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 15
SYNTHESIS TEMPLATES

 It is extremely important to conform to these templates since they

dictate how VHDL must be written in order to be synthesizable.

 VHDL models must be written for synthesis from the start; it is not
possible to take just any VHDL that simulates correctly and expect it
to be synthesizable.

 Many years of work have been wasted by engineers who failed to

realize this and wasted their time perfecting simulation models before
considering the synthesis constraints.

Dr. Bharat Garg, Assistant Professor, TIET, Patiala FPGA Based System Design 16