Analog-iitb
Ist part Analytical Questions (All subjective) 5 Q 45 min
1) One number of five digit is given if we append 9 before the number
it will become 4 times when append 9 at end . WHAT IS NUMBER?
2) 6 MONKS 6 cannible( can eat monks if C> M any time
any where) One boat . boat can sustain at most 3 persons. Trivial
question....
3) Two inputs in a block are going (N1 and N2) two outputs (Max and
min of that). If U have 4 numbers than how u use this as a building
block to sort 4 numbers.
4) Two men B1 and B2 and two women G1 and G2 are their. One is killed
who is victim we have to find this.....with given condition...........
Cond1) B1's sister argues G1's husband after killing. Condn two
sister argues twice with Victim's spouse after killing.
5) A to E five persons are their. 100 rs to be distributed some cond
given U have to find how A will get max profit tough question carries
8 marks...
Technical Part contains 50 marks time 1 hour
1st part match the following.
Questions 10 all basics topics........
1) static (wrt dynamic circuits)
2) Electromigration
3) Hot electron
4) Tr in Saturation
5) Latch-up
6) Seq. Ckt.
7) CLM
8) FIR filter.
9) ...
10) ...
2nd part contains 15 question all subjective drawing circuits simple
all are from moris mano very-very easy so U have to score high..........(Objective)
1) Dynamic circuits.......with feedback called HALF LATCH.
2) inv with PMOS and NMOS exchanged
3) which circuit is having smallest fall delay . options 1) NAND both
input connected 2) NOR both input connected 3) NAND with one input
at VDD 4) nor with one input at GND
4) question on microprocessor
6) question on DMA
7) Network simple question on charge sharing
8) Implement following statement with logic gates if(a==b) {y=p} else{y=q}
9) One complicated ckt with two inputs and one output and VDD and
no GND and is XNOR.
10) Current mirror simple question current is I2 = 2I1 answer.
11) NAND and NOR equivalent to the inverter with same rise and
fall time.
3rd section............... 10 question more marks ..........
1) Layout routing
2) Capacitance from layout
3) Fringing and area capacitance calculation
4) Sheet resistance is given u have to calculate total resistance.
5) Microprocessor question with 3-stage pipeline instruction.
Easy question
6) Simple circuit with glitch in that how to remove it and draw
the waveforms. K map has given.
7) Implemet ckt with AND/OR/INV .
Other questions were easy Best of luck to all of U.
Interviews were based on projects and some simple digital ckts....................Some device
physics band banding and how capacitance varies with High and low frequency. Basics of
microe or VLSI.
Good Luck ALL.........
1)
It is to find inv. char with subtrates connected to some other
voltages.(not vdd not gnd)
2)
Two blocks with FF and CLB are connected in series. Given the internal
structure of first block. Input to the ckt is D input. U have to find the
internal structure of other block so that out of II block will be same as
D.
3)
one disk is 40% black and 60%is white. One sensor is sensing its color,
Black is 1 and white is 0. Disk is rotating
U have to design a simple ckt such that ckt should be able to find
direction
of rotation of disk.
4)
layout one question *
5) state machine *
6) timing setup and hold time
7)
puzzeles *
* indicates that only pattern is given no specific questions are given on
that by nilesh
Rajesh
Written Test :
1. If A.B = 0, prove that A xor B = A or B
2. CMOS inverter with P and N devices interchanged. Draw the o/p waveform for
square wave i/p with Vtn =Vtp = 1 V. Vdd = 5V.
3. Given a logic function. Realize with static CMOS. Do sizing for equal worst case
rise and fall time. Given un = 2up.
4. FIFO : sender => 200Megasamples/sec. Receiver => 10 Megasamples/sec. Sender
sends a burst of 10usec in every 1 sec. Find the depth of FIFO.
5. A simple ques on karnaugh map simplification.
6. A question on optical sensors: A and B are placed at 90degrees around the optical
disk that is painted black on 40% of its area. Design a logic to detect the direction
of rotation. (Ans: Give A to clk & B to input or vice versa of D FF)
7. A question on 3 flip-flops cascaded..2 & 3 f/f have closk skew..draw output
waveforms..hold time =0 .One case was when Tcq was less than clock skew
& when it is greater
8. Simple booelan function to be implemented using ex-or , nand , nor gates.
9. Given sheet resistance of metal, and some metal later layout( dimensions were
given ), metal contact......find the power dissipation
Interview :
1. Draw CMOS inverter and explain the transfer char qualitatively with different region
of operations.
2. Realize shift registers in VHDL using signals / variables.
3. Pipelining hazards and possible solutions.
4. Cache design.
5. Prove qualitatively that product of 3 conseq integers is divisible by 6.
6. Sum of digits of a no is div by 3 then prove that no will also be.
7. 5 teams participating in league tournament. How many matches total ?
8. Assume a processor has „S‟ stages of pipeline, and each instruction requires 1 clock
cycle for execution. If a code is written such that a fraction “b” of the total number of
instructions are branch instructions, then what is the average number of clock cyc les
required per instruction (CPI of the processor)?
9. Assume two tristate buffers with inputs A and B, and control C and D, which are
independent of each other. The outputs of both buffers are shorte, what is probability
of bus contention?
** Fundamentals about set up time, hold time, VHDL syntax for simple circuits, timing
analysis of given circuits, are asked.
