Processor Fundamentals and System Bus Explanation
1. Registers and Fetch-Execute Cycle
a. General-purpose register name
The Accumulator is the general-purpose register typically found in simpler processors. It is
used to perform calculations and store intermediate results.
b. Memory Address Register (MAR)
i. Function: The MAR holds the address of the memory location that is to be accessed for a
read or write operation.
ii. Type of data stored: The MAR stores memory addresses (numerical values representing
locations in memory).
iii. Register supplying data at the start of fetch stage: The Program Counter (PC) supplies
the address to the MAR during the fetch stage.
c. Current Instruction Register (CIR)
i. Function: The CIR stores the instruction currently being decoded and executed.
ii. Type of data stored: The CIR stores the machine code or binary representation of the
current instruction.
iii. Register supplying data at the end of fetch stage: The Memory Data Register (MDR)
supplies the data (instruction) to the CIR.
d. Differences between MAR and MDR
1. Function:
- MAR holds the address of a memory location.
- MDR holds the data being transferred to or from that memory location.
2. Type of Data Stored:
- MAR stores addresses.
- MDR stores actual data or instructions.
3. Interaction:
- MAR interacts with the address bus to locate memory locations.
- MDR interacts with the data bus to transfer data.
2. System Bus
a. Explanation of system buses
1. Data Bus: Transmits data between components such as the processor, memory, and I/O
devices.
2. Address Bus: Carries memory addresses from the processor to other components (e.g.,
memory or I/O).
3. Control Bus: Carries control signals (e.g., read/write signals) to coordinate operations.
b. Bus Width
i. What determines bus width: The number of parallel lines in the bus determines its width.
ii. Bus with the least width: The control bus typically has the least width as it only needs to
carry control signals, which are fewer in number.
iii. Effect of changing address bus from 32-bit to 64-bit:
Increasing the address bus width allows the processor to access a larger memory range.
Specifically:
- A 32-bit address bus supports 2^32 (4GB) of memory.
- A 64-bit address bus supports 2^64 (16 exabytes) of memory.
3. Fetch Stage and Register Transfer Notation
a. Explanation of fetch stage statements:
1. MAR ← [PC]: The value of the Program Counter (PC) is copied into the Memory Address
Register (MAR). The MAR now holds the address of the memory location to fetch the next
instruction.
2. MDR ← [[MAR]]: The data at the memory location specified by MAR is fetched into the
Memory Data Register (MDR). The double brackets indicate the actual data is retrieved
from the memory location.
3. CIR ← [MDR]: The data in the MDR (the fetched instruction) is copied to the Current
Instruction Register (CIR). The CIR now holds the instruction to be decoded and executed.
b. Use of buses in statements
1. MAR ← [PC]: The address bus is used to transfer the address from the MAR to memory.
2. MDR ← [[MAR]]: The data bus is used to transfer the data from memory to the MDR.
4. Von Neumann Model and Interrupts
a. Three buses in the von Neumann model:
1. Data Bus: Transfers data between components.
2. Address Bus: Transfers memory addresses to locate data or instructions.
3. Control Bus: Sends control signals to manage data flow and operations.
b. Steps in fetch stage
1. Step 2: The memory location pointed to by MAR is accessed, and its contents are copied to
MDR.
2. Step 3: The data/instruction in MDR is transferred to CIR.
3. Step 4: The PC is incremented to point to the next instruction.
c. Execution of LDD 35
LDD 35: Load the data at memory location 35 into the accumulator.
1. The address 35 is loaded into MAR.
2. The data at address 35 is fetched into MDR.
3. The data in MDR is transferred to the accumulator.
d. Interrupts
i. Definition: An interrupt is a signal that temporarily halts the current execution to allow
the processor to handle an event or execute a higher-priority task.
ii. Actions of processor during interrupt:
1. Save the current state of registers (including PC).
2. Load the address of the interrupt service routine (ISR) into the PC.
3. Execute the ISR.
4. Restore the saved state and resume normal execution.
