FPGA Architecture, Technologies, and Tools
Neeraj Goel IIT Delhi
Plan
FPGA architecture
Basics of FPGA
FPGA technologies
Architectures of different commercial FPGAs
FPGA tools
FPGA implementation flow and software involved
HDL coding for FPGA
Some coding examples and techniques
Jan 10, 2009
Neeraj Goel/IIT Delhi
What is FPGA
FPGA Field Programmable Gate Array
A programmable hardware
Relation between VHDL and FPGA
VHDL models hardware and FPGA implements the hardware modeled by VHDL
Relation between ASIC and FPGA
Same in functionality FPGA are reprogrammable
Jan 10, 2009
Neeraj Goel/IIT Delhi
FPGA
Field Programmable Gate Array A plane and regular structure in which logic and interconnect both are programmable Programmability of logic any combinational or sequential logic can be implemented Programmability of interconnect any logic component can be connected to anyone else
Jan 10, 2009
Neeraj Goel/IIT Delhi
ASIC verses FPGA
FPGA
Programmability Low cost solution Larger area, power and speed Less design and testing time
Proc FPGA ASIC Performance
ASIC
Low cost for large volume Area and power efficient High frequencies can be achieved Huge testing cost in term of time and money
Jan 10, 2009
Neeraj Goel/IIT Delhi
Applications of FPGAs
Conventional applications
For design prototyping For emulation
New applications
As hardware acceralator In place of ASIC
Less time to market
Complete System on Chip (SoC) solution
Jan 10, 2009
Neeraj Goel/IIT Delhi
Programming technology
Anti-fuse based
All the contacts or open initially Programming converts selected locations as conducting One time programmable (OTP)
SRAM based E2ROM or Flash based Tradeoffs
Anti-fuse is less area, less power consuming E2RAM takes more time for programming SRAM is technology leaders
Jan 10, 2009 Neeraj Goel/IIT Delhi
Programmable Logic
Fine grain fabric
A universal gate like NAND or AND-OR-NOT
Middle grain
Multiplexer based ROM/RAM based
Coarse grain
FFT or a processor as a basic unit
Tradeoffs
Fine grain FPGA involves more interconnection overhead Coarse grain are application specific
Jan 10, 2009 Neeraj Goel/IIT Delhi
Programmable Logic
Op = X xor Y xor Z 0 1 1 0 1 0 0 1
LUT based
X X Y X X Y 0 1 Z
Jan 10, 2009
MUX based
OP
OP
XYZ
Neeraj Goel/IIT Delhi
A simple programmable logic block
a b c d
LUT
y q FF
clock
Jan 10, 2009
Neeraj Goel/IIT Delhi
Programmable interconnects
Connection box
Connects input/output of logic block to interconnect channels
Switch box
Connects horizontal channels to vertical channels
Transmission gate (or a pass transistor) is used for each connection
Jan 10, 2009
Neeraj Goel/IIT Delhi
Interconnections
4 3 2 1
2
5
2
5
[1]
1
[10]
1 2 3 4
1 2 3 4
4 3 2 1
[9]
1
[21]
A switch box
Routing succeeded with a channel width factor of 3.
A snapshot from VPR
Neeraj Goel/IIT Delhi
Jan 10, 2009
Top view of a simple FPGA Architecture
pq ps pm pn
pp [108] po [11] [109] [107]
pi pj
pu pv out:pv [1] [10] [106]
pl pk
pa [111] pb [9] [21] [113]
pe pf
pd [110] pc [20] [112]
pt pr ph
pg
A snapshot from VPR
Jan 10, 2009
Routing succeeded with a channel width factor of 3.
Neeraj Goel/IIT Delhi
Review and questions
Is FPGA an ASIC? Can we implement an processor in FPGA? Are PLAs same as FPGA? The companies which produce FPGA? Why FPGAs are important to our VLSI? Do we need to study FPGA internals?
Jan 10, 2009
Neeraj Goel/IIT Delhi
Questions?
Plan
FPGA architecture
Basics of FPGA
FPGA technologies
Architectures of different commercial FPGAs
FPGA tools
FPGA implementation flow and software involved
HDL coding for FPGA
Some coding examples and techniques
Jan 10, 2009
Neeraj Goel/IIT Delhi
Advanced FPGA Architectures
Companies
Xilinx Altera Actel Amtel Quicklogic
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture
Basic blocks are a logical cell
a b c d e FF clock
LUT
y q
A 4 input LUT can also act as 16x1 RAM or Shift register
Jan 10, 2009 Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture
Basic blocks are a logical cell A slice comprise of two logic cells A configurable logic block (CLB) may have upto 4 slices
CLB of XC4000 series have 1 slice CLB of virtex series have 2 or 4 slices
A hierarchical structure help in reducing interconnections
Interconnections are costly resource in FPGA
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: a CLB in XC4000
Source: xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: a CLB in XC4000
Two 4-input and one 3-input function generator Two latched outputs and two unlatched output
Fun. Gen. Fun. Gen. Fun. Gen.
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: a CLB in XC4000
One 9-input function generator Latched or unlatched output
Fun. Gen. Fun. Gen. Fun. Gen.
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: a CLB in XC4000
One 9-input function generator Latched or unlatched output
Fun. Gen. Fun. Gen. Fun. Gen.
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: a CLB in XC4000
function generator as RAM
Level triggered, edge triggered, single port, dual port 16x2, 32x1, 16x1 bit array
D0 G1..G4 Fun. Gen. D1 H1..H4 Fun. Gen.
Neeraj Goel/IIT Delhi
16x2 single port bit array
Jan 10, 2009
Xilinx FPGA Architecture: a CLB in XC4000
function generator as 16x2 edge triggered single port RAM
Source: xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: a CLB in XC4000
Fast carry chains
Dedicated logic in F and G function generators for fast carry generation Dedicated routing resources for carry chains
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: Interconnections
Five type of interconnection based on length
Single length lines, double length lines, Quad, Octal and long lines
Source: xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: Interconnections
Single and double lines with programmable switch box
Source: xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: Virtex array
Architecture overview
Source: xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: Virtex array
One CLB 2 slice
Jan 10, 2009
Source: xilinx.com
Neeraj Goel/IIT Delhi
Xilinx FPGA Architecture: Platform Computing
Latest FPGA features
4 slices in a CLB Block RAM Embedded multiplier and DSP block Embedded processors
PowerPC, a hard core Microblaze a soft core
Other interface cores Gbps rocket IO Partial reconfigurability
Jan 10, 2009
Neeraj Goel/IIT Delhi
Altera FPGA families
Similar to Xilinx FPGAs
Basic block is LE (logic element) Basic unit is LAB (Logic array block) equivalent to CLB
Platform computing
MegaRAM DSP block having embedded multiplier Nios embedded processor
Jan 10, 2009
Neeraj Goel/IIT Delhi
Review and questions
Effect of new technologies
Good for DSP computing
Embedded multipliers and BRAMs
A new player in embedded computing A good solution for network applications
Are FPGA internals helpful for a designer?
Jan 10, 2009
Neeraj Goel/IIT Delhi
Questions?
Jan 10, 2009
Neeraj Goel/IIT Delhi
Plan
FPGA architecture
Basics of FPGA
FPGA technologies
Architectures of different commercial FPGAs
FPGA tools
FPGA implementation flow and software involved
HDL coding for FPGA
Some coding examples and techniques
Jan 10, 2009
Neeraj Goel/IIT Delhi
FPGA implementation flow
RTL
Logic Synthesis
Constraint file
Mapping
Netlist
Place and Route
FPGA
Jan 10, 2009
Configuration
Neeraj Goel/IIT Delhi
HDL Synthesis
Input: HDL VHDL or Verilog Output: Netlist Process
Analysis of the HDL Behavior synthesis steps include scheduling and binding
Datapath and FSM are implemented
Logic synthesis is logic minimization Output is in terms of basic gates and flip-flops Also estimates area and delay
Jan 10, 2009 Neeraj Goel/IIT Delhi
HDL Syhthesis
EDA Tools
Synplify Xilinx XST Mentor FPGA express Synopsys DC compiler
Jan 10, 2009
Neeraj Goel/IIT Delhi
Mapping
Input: Netlist and ucf Output: FPGA specific logic and gates Process (
For LUT based FPGA
For k input LUT, find the sub-graph with k input and one output
Tools: Vendor specific
Jan 10, 2009
Neeraj Goel/IIT Delhi
Place and Route
Place
Place the LUTs physically close which are connected most
Reduce the overall net length
Route
Use of routing resources to minimize the delay
Router have the delay model of interconnects
Both place and route are NP complete problem
Heuristics are used Mostly the process of placement and routing is iterative in nature
Configuration file generation
Based on place and route data configuration file is generated
Jan 10, 2009 Neeraj Goel/IIT Delhi
FPGA configuration
Configuration bitstream
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx tools flow
Source: dev manual, Xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Design entry and synthesis
Source: dev manual, Xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Design implementation process
Source: dev manual, Xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Design entry and synthesis
Input
Schematic
Basic cells Core generator
HDL
Synthesis process
Can have various different module
Each module is synthesized as different native generic object (ngo) file All ngo files are combined to form native generic database (ngd) file
Constraints can be given as input to ngdbuild process
Jan 10, 2009 Neeraj Goel/IIT Delhi
Floorplanner Supports hand-placement of FPGA components Creates FNF or UCF file Some components like DLLs need to be placed manually
Jan 10, 2009
Neeraj Goel/IIT Delhi
FPGA Editor Very powerful surgical tool Can change any configuration detail of FPGA
Placement of components Configuration of CLB Slices Routing of particular nets Logic inside the LUTs
Jan 10, 2009
Neeraj Goel/IIT Delhi
Jan 10, 2009
Neeraj Goel/IIT Delhi
Jan 10, 2009
Neeraj Goel/IIT Delhi
Timing Analyzer Performs static analysis of the circuit performance Reports critical paths with all sources of delays Determines maximum clock frequency
Jan 10, 2009
Neeraj Goel/IIT Delhi
Xilinx tool flow revisited
Source: dev manual, Xilinx.com
Jan 10, 2009 Neeraj Goel/IIT Delhi
Questions?
Jan 10, 2009
Neeraj Goel/IIT Delhi
Plan
FPGA architecture
Basics of FPGA
FPGA technologies
Architectures of different commercial FPGAs
FPGA tools
FPGA implementation flow and software involved
HDL coding for FPGA
Some coding examples and techniques
Jan 10, 2009
Neeraj Goel/IIT Delhi
Writing HDL code for FPGA
While writing HDL code, one should be know
Resources available in FPGA Mapping of code to resource
If multiplication is performed
Embedded multipliers should be used
Various reports during synthesis and implementation convey the resource usage information
For array variables
Block ram should be used
Jan 10, 2009 Neeraj Goel/IIT Delhi
Writing HDL code for FPGA
If a synthesis tool will infer a BRAM or Multiplier depends on
Internals of synthesis tool Quality of HDL code
Best practice for good results
Read the documentation of synthesis tool
They will give example; how to write code
Read the synthesis report carefully
Jan 10, 2009
Neeraj Goel/IIT Delhi
XST: How to write DFF code
Jan 10, 2009
Source: XST user guide, Xilinx.com Delhi Neeraj Goel/IIT
XST: How to write DFF code
Note
Positive edge triggering
Synthesis report must say
Inferred a D type flip-flop
Jan 10, 2009
Neeraj Goel/IIT Delhi
XST: How to write counter code
Jan 10, 2009
Source: XST user guide, Xilinx.com Delhi Neeraj Goel/IIT
XST: How to write adder code
Jan 10, 2009
Source: XST user guide, Xilinx.com Delhi Neeraj Goel/IIT
XST: How to write multiplier code
Jan 10, 2009
Source: XST user guide, Xilinx.com Delhi Neeraj Goel/IIT
Summary
Present day FPGAs are quite powerful Need to understand their strengths and internal characteristics to fully exploit their potential Designer must understand what will be designed
Apart from functional correctness, insight in structure is necessary for optimization If the implemented output is not desired
Something wrong EDA tools is not provided enough information!
Good to have understanding of tool flow for advanced manipulations
Jan 10, 2009
Neeraj Goel/IIT Delhi
Questions?
Jan 10, 2009
Neeraj Goel/IIT Delhi
Thank you!
Jan 10, 2009
Neeraj Goel/IIT Delhi
