Experiment 1: Study and verify the outputs of the logic gates (AND, OR, NOT,

NAND, NOR, Ex-OR, and Ex-NOR).

• AND gate: 7408

• OR gate: 7432

• NOT gate (Inverter): 7404

• NAND gate: 7400

 • NOR gate: 7402

• Ex-OR gate: 7486

• Ex-NOR gate: 74266

Viva Questions:
1. How many AND gates are required to realize Y = CD + EF + G?
Ans: AND Gates for Y = CD + EF + G: 2 AND gates are required (one for CD,
one for EF). The G term and final OR operation would require additional
gates.
2. How many NAND gates are required to design a XOR gate? Draw XOR
gate using NAND gate.
Ans: Number of NAND gates for XOR: 4 NAND gates

3. Which gates are the universal gates? Why these gates are called
universal gates?
• NAND and NOR are universal gates
• They can implement all other logic gates (AND, OR, NOT) using
combinations of themselves
• This is because they can create any Boolean function through their
configurations
Experiment 2: Implement Half Adder, Full Adder, Half Subtractor and Full
Subtractor.
• Half Adder: 7486 (XOR gate) and 7408 (AND gate)
• Full Adder: 7486 (XOR gate), 7408 (AND gate), and 7432 (OR gate)
• Half Subtractor: 7486 (XOR gate) and 7400 (NAND gate)
• Full Subtractor: 7486 (XOR gate), 7400 (NAND gate), and 7432 (OR gate)
Viva Questions:
1. Draw the full adder using half adders.

2. Draw the full subtractor using half subtractor.

3. What is a major limitation of a half adder?

Ans: The major limitation of a half adder is its inability to handle a carry-in
from a previous addition. This means a half adder can only add two single-bit
binary numbers without considering any previously existing carry, which
restricts its use in multi-bit addition scenarios. To overcome this limitation, a
full adder is used, which can incorporate a carry-in input.
Experiment 3: Implement 3-bit parallel Binary Adder/Subtractor.
Viva Questions:
1. How many full adders and XOR gates are required to make 4-bit Binary
Adder/Subtractor?
Ans: For a 4-bit Binary Adder/Subtractor:
• Full Adders required: 4
• XOR gates required: 8 (4 for input modifications, 4 for sum generation)
The 4 full adders handle bit-wise addition/subtraction, while the XOR gates
are used for managing the addition/subtraction mode and generating
individual sum bits.
2. What is the disadvantage of a ripple adder?
Ans: The main disadvantage of a ripple adder is propagation delay. In this
design, each full adder waits for the carry from the previous stage to
complete its addition, causing a cumulative delay that increases with the
number of bits. This means the time to add larger binary numbers becomes
significantly longer, reducing the circuit's overall speed.
3. Draw the 4-bit parallel Binary Adder/Subtractor
Ans:
Experiment 4: Implement 3-bit carry look-ahead adder.
IC number-74283

Viva Questions:
1.What property distinguishes a look-ahead-carry adder from ripple adder?
Ans: The key distinguishing property of a carry look-ahead adder (CLA) compared
to a ripple carry adder is that it reduces carry propagation delay by generating
and propagating carry signals in parallel, instead of waiting for each stage's carry
to ripple through sequentially.
2. What are the two functions Carry look-ahead logic uses to create carry look-
ahead generator circuit?
Ans: The two fundamental functions used in carry look-ahead logic are:
• Carry Propagate Function (P): P = A ⊕ B
• Carry Generate Function (G): G = A • B
These functions help determine how carries are generated and propagated
between bits during addition.
3. What is carry propagation delay?
Ans: Carry propagation delay is the time it takes for a carry signal to travel
through a circuit from the least significant bit to the most significant bit. In a
ripple carry adder, this delay increases linearly with the number of bits, as each
stage must wait for the previous stage's carry. In contrast, a carry look-ahead
adder minimizes this delay by calculating carries in parallel, significantly reducing
the overall addition time for larger bit-width adders.
Experiment 5: Implement 4-bit Binary -to -Gray, Gray -to -Binary code
converter.
Viva Questions:
1. What is the property of gray code?
Ans: The key property of Gray code is that between any two adjacent numbers,
only a single bit changes. This means when you move from one number to the
next in a Gray code sequence, exactly one bit is flipped from 0 to 1 or vice
versa. This unique characteristic distinguishes Gray code from other binary
encoding schemes.
2. What are the applications of gray code?
Ans: Applications of Gray code include:
• Rotary encoders and position sensors, where precise measurement of
mechanical rotation is crucial
• Error correction in digital communication systems
• Minimizing switching errors in analog-to-digital and digital-to-analog
converters
• Genetic algorithms and randomized search algorithms
• Solving certain computational problems like the traveling salesman
problem
• Reducing glitches in digital circuits by minimizing bit transitions
• Mapping in digital cartography and geographical information systems

3. What are the weighted and un-weighted codes? Is gray code weighted?
Ans:
• Weighted codes are those where each bit position has a specific numerical
weight or value. In a weighted code, each bit contributes a specific
multiplicative value to the overall number (like standard binary, where
each bit represents a power of 2).
• Unweighted codes are those where bits do not have a positional
numerical value.
Gray code is an unweighted code. Unlike standard binary where each bit position
represents a power of 2, Gray code does not assign a fixed weight to each bit
position. Its primary purpose is to ensure minimal bit transitions between
adjacent numbers, not to represent numerical values in a traditional weighted
manner.
Experiment 6: Implement a 2x2 Binary Multiplier.
Viva Questions:
1. Draw 4x4-Binary Multiplier.
Ans:

In a 4x4 binary multiplier, we use AND gates to generate partial products and full
adders to sum these partial products. The basic structure involves:
• 16 AND gates (4 rows × 4 columns)
• Multiple stages of full adders to sum the partial products
• The result will be an 8-bit output (since 4 × 4 = 8 bits)

2. How many full adders and AND gates are will be required to draw 4x3 binary
multiplier?
Ans: AND gates: 4 × 3 = 12 AND gates
Full adders: Depends on the partial product summation, but typically around 9-
10 full adders
3. How many bits will in the result of multiplication of M-bit and N-bit
numbers?
Ans: For M-bit and N-bit numbers, the result will have (M+N) bits.
• Example: A 4-bit number × A 3-bit number = 7-bit result
• General formula: Result bits = M + N
Experiment 7: Implement (4 to 2) line and (8 to 3) line Encoders.
Encoder IC- 74148
Viva Questions:
1. What is Priority Encoder?
Ans: A priority encoder is a digital circuit that:
• Converts multiple input lines into a binary code
• Gives priority to the highest-numbered active input
• Produces an encoded output representing the highest-priority active
input
• Useful when multiple inputs are active simultaneously, and only the
highest-priority input needs to be encoded
Key characteristics:
• If multiple inputs are active, it selects the input with the highest priority
• Outputs a binary code corresponding to the selected input
• Often includes an additional output to indicate whether any input is active
 2. What is decimal to BCD encoder?
Ans: Converts a decimal input (0-9) to its equivalent 4-bit Binary Coded
Decimal representation
• Converts decimal digits into their binary equivalent
• Typically has 10 input lines (one for each decimal digit 0-9)
• Produces a 4-bit output representing the BCD code
3. What are the applications of an encoder circuit?
Ans: Applications of Encoder Circuits:
• Keyboard input processing
• Priority interrupt handling in computer systems
• Digital communication systems
• Control systems
• Data compression
• Memory addressing
• Input device interfaces
• Priority management in digital controllers
• Signal routing in complex digital systems
• Conversion between different number representations
Example use cases:
• Computer processors use priority encoders to manage interrupt requests
• Telecommunications equipment uses encoders for signal processing
• Industrial control systems use encoders for input prioritization
• Digital keyboards use encoders to convert key presses to binary codes

Experiment 8: Implement (2 to 4) line and (3 to 8) line Decoders.

Deocder IC- 74138
Viva Questions:
1. Draw the 3x8 decoder using 2x4 decoders.
Ans: To create a 3x8 decoder using 2x4 decoders:
• You'll need two 2x4 decoders
• Use the most significant input bit to enable/select between the two
decoders
• The remaining two input bits will be used as inputs for both decoders
• Additional logic (typically AND gates) will be needed to combine the
decoder outputs
2. What is a binary decoder?
Ans: A binary decoder is a digital circuit that:
• Converts an n-bit binary input into 2^n mutually exclusive output lines
• Activates only one output line corresponding to the binary input
• Essentially "decodes" the binary input to select a specific output line
• Opposite functionality of an encoder

3. What are the applications of a decoder?

Ans: Decoders are fundamental components in digital systems, enabling
precise selection and routing of signals based on binary input codes. They
transform compact binary representations into specific, targeted control or
data selection mechanisms.
• Memory address decoding
• Instruction decoding in microprocessors
• Data demultiplexing
• Memory mapping
• Control signal generation
• Input/output port selection
• Display drivers
• Digital system control
• Arithmetic logic units (ALUs)
• Multiplexer/demultiplexer systems
• Instruction set implementation
• Register selection in computer architectures
Experiment 9: Implement 4x1 and 8x1 Multiplexers.

MUX IC- 74151

Viva Questions:
1. Draw the block diagram of 8 input multiplexer using 2-input multiplexer, 16
input multiplexer using 2-input multiplexer.
Ans: - 8-input Multiplexer using 2-input Multiplexers:
• Requires 3 selection lines
• Cascade 4 x 2-input multiplexers
• Use 2 selection lines to select between 2-input multiplexers
• 3rd selection line determines output
- 16-input Multiplexer using 2-input Multiplexers:
• Requires 4 selection lines
• Cascade 8 x 2-input multiplexers
• Use 3 selection lines to select between 2-input multiplexers
• 4th selection line determines final output
2. What are the applications of a multiplexer?
Ans: Applications of Multiplexer:
• Data routing in communication systems
• Signal selection in digital circuits
• Computer memory addressing
• Input/output port selection
• Digital signal processing
• Telephone switching systems
• Data acquisition systems
• Computer bus systems
• Parallel-to-serial conversion
• Control system logic
• Arithmetic logic units (ALUs)
• Microprocessor instruction decoding

3. Implement the following function using 4x1 Mux. F(A, B, C) =∑ (2, 4,7)
Ans: Inputs: A, B as selection lines
• C as data input
• Truth table mapping:
• When A=0, B=0 (input 0): 0
• When A=0, B=1 (input 1): 0
• When A=1, B=0 (input 2): 1 (matches minterm 2)
• When A=1, B=1 (input 3): 1 (matches minterm 4 and 7)
Experiment 10: Implement 1x4 and 1x8 De-multiplexers.

Demux IC- 74139

Viva Questions:
1. Draw a 1x8 demultiplexer using 1x4-demultiplexer.
Ans:
2. Why a demultiplexer is called a data distributor?
Ans: A demultiplexer is called a data distributor because it:
• Takes a single input data line
• Uses selection lines to distribute this input to multiple output lines
• Effectively "distributes" or routes the input signal to one of several
possible output lines
• Acts like a selector that routes a single input to multiple potential
destinations
• Opposite functionality of a multiplexer, which combines multiple inputs
into a single output

3. How many selection lines are required in 1x64 demultiplexer.

Ans: To select 1 out of 64 output lines
• Number of selection lines = log₂(64)
• log₂(64) = 6 selection lines
• These 6 selection lines can uniquely address all 64 output lines
• Allows routing of a single input to any of the 64 possible output lines
The demultiplexer is crucial in digital systems for routing signals, distributing
data, and implementing complex switching and selection logic.

Experiment 11: Verify the characteristic/state tables of SR and D FLIP-FLOPS

using NAND gates.
D flip-flop: 7474 IC
SR flip flop: 74279 IC
Viva Questions:
1.What is difference between the flip flop and latch?
Ans: Latch:
• Level-triggered device
 • Changes output immediately when enable/control signal is active
• Sensitive to input changes while enable signal is active
• Simpler circuit design
• Used in combinational logic circuits
Flip-Flop:
• Edge-triggered device
• Changes output only at clock edge (rising or falling)
• More stable and predictable
• Prevents unwanted state changes
• Primarily used in synchronous sequential circuits
• Provides better timing and synchronization
• Preferred in complex digital systems like registers and memory elements

2. Draw the SR flip flop and D flip flop using NOR gates
Ans: SR Flip-Flop (NOR Gate):
• Two NOR gates cross-coupled
• S (Set) and R (Reset) inputs
• Requires careful input management to avoid invalid states
• Outputs Q and Q' (complement)
D Flip-Flop (NOR Gate):
• Constructed using NOR gates
• Single D input represents the data to be stored
• Eliminates the invalid state problem of SR flip-flop
• Captures input state at clock edge
3. What is a sequential digital circuit?
Ans: A sequential digital circuit is a type of digital logic circuit that:
• Has memory or storage elements
 • Outputs depend on both current inputs and previous state
• Uses flip-flops or latches to store state information
• Output is a function of both present inputs and past history
• Includes memory, registers, counters, and state machines
• Characterized by sequential behavior and state transitions
• Enables complex computational and control mechanisms
Key characteristics:
• Contains storage elements
• Timing-dependent operations
• State-based computation
• Ability to remember and process previous inputs
• Used in complex digital systems like computers, controllers, and
communication devices
Experiment 12: Design a 2-bit Arithmetic Logic Unit.

The 74181 is a classic 4-bit arithmetic logic unit (ALU) integrated circuit that
was widely used in early computer and digital design applications.
Viva Questions:
1. Draw the 4-bit arithmetic unit.
Ans:
2. Register A holds the 8-bit binary 11011001. Determine the B operand and
the logic microoperation to be performed in order to change the value in A to
01101101
Ans: Register A Transformation:
• Initial Value: 11011001
• Desired Final Value: 01101101
To transform 11011001 to 01101101, we need:
• B Operand: 10110100
• Logic Microoperation: AND operation
• Verification: 11011001 AND 10110100 = 01101101
Calculation: 11011001 (Original A) & 10110100 (B operand)
01101101 (Resulting A)

3. What is the purpose of ALU?

Ans: Purpose of ALU (Arithmetic Logic Unit):
 • Performs arithmetic operations (addition, subtraction)
• Executes logical operations (AND, OR, NOT, XOR)
• Supports comparison operations
• Generates status flags (carry, zero, overflow)
• Core computational component in processors
• Processes data according to instruction requirements
• Supports various mathematical and logical manipulations
• Enables complex computational tasks in digital systems
Key functions:
• Integer arithmetic
• Bitwise logical operations
• Shift and rotate operations
• Comparison and testing
• Generating control signals for other circuit components