Islam Mohamed Abdelaziz

Email: islam mohamed

LinkedIn: Islam Mohamed | LinkedIn
Mobile:01068110029
Education
Faculty of Engineering – Cairo University
BSc. Electronics and Electrical Communications department (2019-2024)
Cumulative Grade: Very Good
Graduation Project: cxl link layer verification using uvm
Military status: exempted
Projects
➢ Digital ic projects:
1. Digital verification of CXL link layer using UVM Sponsored by: Si-vision
- Project phases: Supervisors: Dr Omar Nasr /
• CXL standard reading Eng Omnia Tayseer
• Creating and documenting a verification plan
• UVM architecture Coding
• WB modeling of different CXL mechanisms
• Writing assertions to verify suitable sequences
• Reading the essential parts of the design RTL codes of test benches and start debugging
• Driving the design to get outputs and start verifying
• Start randomization to catch bugs in addition to coverage measurement to determine whether
the verification process is finished or not
• reporting the bugs and the coverage percentage (code, functional)
- Key Responsibilities:
• Driving the Interface between the Transaction and Link layer (i.e., Behavior of the transaction
layer)
• Verifying Blocks: Packer, Unpacker, Credit management TX and RX
• Verifying End to End Messages sent and received by 2 DUTs
• Automate the running of all the project by do scripting files
• Developed and maintained TCL scripts to automate project workflows, enhancing efficiency
and consistency.
• Implemented syntax checkers to ensure code quality and adherence to coding standards.
• Conducted thorough UVM verification for RTL code, identifying and resolving potential issues.
• Collaborated with the design team to refine verification strategies and improve overall code
reliability.
- Key Achievements:
• Streamlined project execution by automating repetitive tasks.
• high coverage results
• reporting bugs for all the system
2. “RTL to GDS Implementation of Low Power Configurable Multi Clock Digital System”
▪ Description: It is responsible of receiving commands through UART receiver to do different system
functions as register file reading/writing or doing some processing using ALU block and send result as
well as CRC bits of result using 4 bytes frame through UART transmitter communication protocol.
▪ Project phases:
 - RTL Design from Scratch of system blocks (ALU, Register File, Synchronous FIFO, Integer Clock
Divider, Clock Gating, Synchronizers, Main Controller, UART TX, UART RX).
- Integrate and verify functionality through self-checking testbench.
- Constraining the system using synthesis TCL scripts.
- Synthesize and optimize the design using design compiler tool.
- Analyze Timing paths and fix setup and hold violations.
- Verify Functionality equivalence using Formality tool
- Physical implementation of the system passing through ASIC flow phases and generate the GDS
File.
- Verify functionality post-layout considering the actual delays.
➢ DSP projects:
o Numbers Voice Recognition | (MATLAB)
o Implementation of jpeg compression standard | (MATLAB)
➢ Software projects:
o Wedding planner system| C++ (OOP)
o University website (front-end part) demo
Internship
• Si-vision digital verification internship:
a. System Verilog and assertion b. UVM
c. Internship project: UVM environment of ALU
Technical Skills
➢ Digital Design
o HDL languages (Verilog/System Verilog) o Static timing analysis
o Clock domain crossing
o TCL Scripting Language o Clock tree synthesis
o RTL synthesis | Formal verification | DFT | PnR o Dft
➢ Software
o C/C++ o ISTQB verification concepts
o OOP| Data Structures o SW testing
o Python
o Linux
➢ Embedded Systems:
o AVR Microcontrollers Interfacing
o C for Embedded Applications (Embedded C)
o Real-Time Operating System (RTOS)
➢ EDA Tools:
o Questasim o Cadence Virtuoso
o Quartus o Proteus
o Design Compiler, Formality
COURSES
➢ Digital Systems:
o Hardware Description Languages for FPGA Design (University Colodare Boulder) in Coursera Summer 2024
o Digital IC Design Diploma | Under the supervision of Eng. Ali El-Temsah