Syllabus

Unit 1 Introduction: Functional units of digital system and their

interconnections, buses, bus architecture, types of buses and bus arbitration.
Register, bus and memory transfer. Processor organization, general registers
organization, stack organization and addressing modes
Unit 2 Arithmetic and logic unit: Look ahead carries adders. Multiplication:
Signed operand multiplication, Booths algorithm and array multiplier. Division
and logic operations. Floating point arithmetic operation, Arithmetic & logic unit
design. IEEE Standard for Floating Point Numbers Unit 3 Control Unit:
Instruction types, formats, instruction cycles and sub cycles (fetch and execute
etc), micro operations, execution of a complete instruction. Program Control,
Reduced Instruction Set Computer, Pipelining. Hardwire and micro programmed
control: micro programme sequencing, concept of horizontal and vertical
microprogramming.
Unit 4 Memory: Basic concept and hierarchy, semiconductor RAM memories,
2D & 2 1/2D memory organization. ROM memories. Cache memories: concept
and design issues & performance, address mapping and replacement Auxiliary
memories: magnetic disk, magnetic tape and optical disks Virtual memory:
concept implementation.
Unit 5 Input / Output: Peripheral devices, I/O interface, I/O ports, Interrupts:
interrupt hardware, types of interrupts and exceptions. Modes of Data Transfer:
Programmed I/O, interrupt initiated I/O and Direct Memory Access., I/O channels
and processors. Serial Communication: Synchronous & asynchronous
communication, standard communication interfaces
 UNIT-1
1.1. Functional Units of Digital System
 A computer organization describes the functions and design of the various units of a digital system.

 A general-purpose computer system is the best-known example of a digital system. Other examples
include telephone switching exchanges, digital voltmeters, digital counters, electronic calculators
and digital displays.
 Computer architecture deals with the specification of the instruction set and the hardware units that
implement the instructions.
 Computer hardware consists of electronic circuits, displays, magnetic and optic storage media and
also the communication facilities.
 Functional units are a part of a CPU that performs the operations and calculations called for by the
computer program.

 Functional units of a computer system are parts of the CPU (Central Processing Unit) that performs
the operations and calculations called for by the computer program. A computer consists of five
main components namely, Input unit, Central Processing Unit, Memory unit Arithmetic & logical
unit, Control unit and an Output unit.

Input unit
 Input units are used by the computer to read the data. The most commonly used input
devices are keyboards, mouse, joysticks, trackballs, microphones, etc.
 However, the most well-known input device is a keyboard. Whenever a key is pressed, the
corresponding letter or digit is automatically translated into its corresponding binary code
and transmitted over a cable to either the memory or the processor.
Central processing unit: Central processing unit commonly known as CPU can
be referred as an electronic circuitry within a computer that carries out the
instructions given by a computer program by performing the basic arithmetic,
logical, control and input/output (I/O) operations specified by the instructions.

Memory unit
 The Memory unit can be referred to as the storage area in which programs are kept which are
running, and that contains data needed by the running programs.
 The Memory unit can be categorized in two ways namely, primary memory and secondary
memory.
 It enables a processor to access running execution applications and services that are temporarily
stored in a specific memory location.
 Primary storage is the fastest memory that operates at electronic speeds. Primary memory
contains a large number of semiconductor storage cells, capable of storing a bit of information.
The word length of a computer is between 16-64 bits.
 It is also known as the volatile form of memory, means when the computer is shut down,
anything contained in RAM is lost.
 Cache memory is also a kind of memory which is used to fetch the data very soon. They are
highly coupled with the processor.
 The most common examples of primary memory are RAM and ROM.
 Secondary memory is used when a large amount of data and programs have to be stored for a
long-term basis.
 It is also known as the Non-volatile memory form of memory, means the data is stored
permanently irrespective of shut down.
 The most common examples of secondary memory are magnetic disks, magnetic tapes, and
optical disks.
Arithmetic & logical unit: Most of all the arithmetic and logical operations of
a computer are executed in the ALU (Arithmetic and Logical Unit) of the
processor. It performs arithmetic operations like addition, subtraction,
multiplication, division and also the logical operations like AND, OR, NOT
operations.
Control unit
  The control unit is a component of a computer's central processing unit that coordinates the
operation of the processor. It tells the computer's memory, arithmetic/logic unit and input
and output devices how to respond to a program's instructions.
 The control unit is also known as the nerve center of a computer system.
 Let's us consider an example of addition of two operands by the instruction given as Add
LOCA, RO. This instruction adds the memory location LOCA to the operand in the register
RO and places the sum in the register RO. This instruction internally performs several steps.
Output Unit
 The primary function of the output unit is to send the processed results to the user. Output
devices display information in a way that the user can understand.
 Output devices are pieces of equipment that are used to generate information or any other
response processed by the computer. These devices display information that has been held
or generated within a computer.
 The most common example of an output device is a monitor.

1.2. Buses, Bus Architecture

A bus that connects major components (CPU, memory and I/O devices) of a
computer system is called as a System Bus. A bus is a set of electrical wires (lines)
that connects the various hardware components of a computer system. It works as
a communication pathway through which information flows from one hardware
component to the other hardware component. Bus Architecture is shown in figure
below.
  A computer system is made of different components such as memory, ALU, registers etc.
 Each component should be able to communicate with other for proper execution of
instructions and information flow.
 If we try to implement a mesh topology among different components, it would be really
expensive.
 So, we use a common component to connect each necessary component i.e. BUS.

1.3. Types of buses

System bus contains 3 categories of lines used to provide the communication
between the CPU, memory and IO named as:
1. Data Bus
2. Address Bus
3. Control Bus

Data Bus: As the name suggests, data bus is used for transmitting the data /
instruction from CPU to memory/IO and vice-versa. It is bi-directional. The width
of a data bus refers to the number of bits (electrical wires) that the bus can carry
at a time. Each line carries 1 bit at a time. So, the number of lines in data bus
determine how many bits can be transferred parallelly. The width of data bus is
an important parameter because it determines how much data can be
transmitted at one time. The wider the bus width, faster would be the data flow
on the data bus and thus better would be the system performance.
Examples-
 A 32-bit bus has thirty two (32) wires and thus can transmit 32 bits of data at a time.
 A 64-bit bus has sixty four (64) wires and thus can transmit 64 bits of data at a time.

8
Address Bus : As the name suggests, address bus is used to carry address from
CPU to memory/IO devices. It is used to identify the particular location in
memory. It carries the source or destination address of data i.e. where to store or
from where to retrieve the data. It is uni-directional.

9
Example- When CPU wants to read or write data, it sends the memory read or
memory write control signal on the control bus to perform the memory read
or write operation from the main memory and the address of the memory
location is sent on the address bus.
 If CPU wants to read data stored at the memory location (address) 4, the CPU send the value
4 in binary on the address bus.

The width of address bus determines the amount of physical memory addressable
by the processor.
 Inother words, it determines the size of the memory that the computer can use.
 The wider is the address bus, the more memory a computer will be able to use.
 The addressing capacity of the system can be increased by adding more address lines.

Examples-
 An address bus that consists of 16 wires can convey 216 (= 64K) different addresses.
 An address bus that consists of 32 wires can convey 232 (= 4G) different addresses.

Control Bus : As the name suggests, control bus is used to transfer the control
and timing signals from one component to the other component. The CPU uses
control bus to communicate with the devices that are connected to the computer
system. The CPU transmits different types of control signals to the system
components. It is bi-directional.
Typical control signals hold by control bus
Memory read – Data from memory address location to be placed
on data bus. Memory write – Data from data bus to be placed on
memory address location. I/O Read – Data from I/O address
location to be placed on data bus.
I/O Write – Data from data bus to be placed on I/O address location.
Other control signals hold by control bus are interrupt, interrupt acknowledge,
bus request, bus grant and several others. The type of action taking place on
the system bus is indicated by these control signals.
Example-
10
When CPU wants to read or write data, it sends the memory read or memory write
control signal on the control bus to perform the memory read or write operation
from the main memory. Similarly, when the processor wants to read from an I/O
device, it generates the I/O read signal.

1.4. System Bus Arbitration

11
Bus Arbitration is the procedure by which the active bus master accesses the bus,
relinquishes control of it, and then transfers it to a different bus-seeking processor
unit. A bus master is a controller that can access the bus for a given instance.
A conflict could occur if multiple DMA controllers, other controllers, or
processors attempt to access the common bus simultaneously, yet only one is
permitted to access. Bus master status can only be held by one processor or
controller at once. By coordinating the actions of all devices seeking memory
transfers, the Bus Arbitration method is used to resolve these disputes
There are two approaches to bus arbitration:
 Centralized Bus Arbitration - In which the necessary arbitration is carried out by a lone
bus arbitrator.
 Distributive Bus Arbitration - In which every device takes part in choosing the new bus
master. A 4bit identification number is allocated to each device on the bus. The created ID
will decide the device's priority
a) Centralized Bus Arbitration Methodologies : There are three methods of Centralized
Bus Arbitration, which are listed below:
i. Daisy Chaining method: It is a simple and cheaper method where all the bus masters
use the same line for making bus requests. The bus grant signal serially propagates
through each master until it encounters the first one that is requesting access to the bus.
This master blocks the propagation of the bus grant signal, therefore any other
requesting module will not receive the grant signal and hence cannot access the bus.
During any bus cycle, the bus master may be any device – the processor or any DMA
controller unit, connected to the bus.

Advantages:
12
 Simplicity and Scalability.
 The user can add more devices anywhere along the chain, up to a certain maximum value.
Disadvantages:
 The value of priority assigned to a device depends on the position of the master bus.
 Propagation delay arises in this method.
 If one device fails then the entire system will stop working.

ii. Polling or Rotating Priority method: In this, the controller is used to generate the
address for the master(unique priority), the number of address lines required depends
on the number of masters connected in the system. The controller generates a sequence
of master addresses. When the requesting master recognizes its address, it activates the
busy line and begins to use the bus.

Advantages –
 This method does not favor any particular device and processor.
 The method is also quite simple.

Disadvantages –
 Adding bus masters is difficult as increases the number of address lines of the circuit.
 If one device fails then the entire system will not stop working.

iii. Fixed priority or Independent Request method: In this, each master has a separate
pair of bus request and bus grant lines and each pair has a priority assigned to it. The
built-in priority decoder within the controller selects the highest priority request and
asserts the corresponding bus grant signal.
 Advantages –
This method generates a fast response.
Disadvantages –
Hardware cost is high as a large no. of control lines is required.

Distributed BUS Arbitration:

In distributed arbitration, all devices participate in the selection of the next bus master.

 In this scheme each device on the bus is assigned a4-bit identification number.
 The number of devices connected on the bus when one or more devices request for the
control of bus, they assert the start-arbitration signal and place their 4-bit ID numbers on
arbitration lines, ARB0 through ARB3.
 These four arbitration lines are all open-collector. Therefore, more than one device can place
their 4-bit ID number to indicate that they need to control of bus. If one device puts 1 on the
bus line and another device puts 0 on the same bus line, the bus line status will be 0. Device
reads the status of all lines through inverters buffers so device reads bus status 0as logic 1.
Scheme the device having highest ID number has highest priority.
 When two or more devices place their ID number on bus lines then it is necessary to identify
the highest ID number on bus lines then it is necessary to identify the highest ID number
from the status of bus line. Consider that two devices A and B, having ID number 1 and 6,
respectively are requesting the use of the bus.
 Device A puts the bit pattern 0001, and device B puts the bit pattern 0110. With this
combination the status of bus-line will be 1000; however because of inverter buffers
code seen by both devices is 0111.
  Each device compares the code formed on the arbitration line to its own ID, starting from
the most significant bit. If it finds the difference at any bit position, it disables its drives at
that bit position and for all lower-order bits.
 It does so by placing a 0 at the input of their drive. In our example, device detects a
different on line ARB2 and hence it disables its drives on line ARB2, ARB1 and ARB0.
This causes the code on the arbitration lines to change to 0110. This means that device B
has won the race.
 The decentralized arbitration offers high reliability because operation of the bus is
not dependent on any single device.

1.5. Register

 Registers are a type of computer memory used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU. The registers used by the CPU are
often termed as Processor registers.
 A processor register may hold an instruction, a storage address, or any data (such as bit
sequence or individual characters).
 The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address
of the next instruction after the execution of the current instruction is completed.

Following is the list of some of the most common registers used in a basic computer:

Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

The following image shows the register and memory configuration for a basic computer.

 The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
 The Data Register (DR) contains 16 bits which hold the operand read from the memory
location.
 The Memory Address Register (MAR) contains 12 bits which hold the address for the
memory location.
 The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
 The Accumulator (AC) register is a general purpose processing register.
 The instruction read from memory is placed in the Instruction register (IR).
 The Temporary Register (TR) is used for holding the temporary data during the processing.
 The Input Registers (IR) holds the input characters given by the user.
 The Output Registers (OR) holds the output after processing the input data.

1.6. Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to
transfer information from one register to another. The number of wires connecting
all of the registers will be excessive if separate lines are used between each
register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information
between registers in a multi-register configuration system.
A bus consists of a set of common lines, one for each bit of register, through
which binary information is transferred one at a time. Control signals determine
which register is selected by the bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data inputs
(0 through 3) and two selection inputs (S1 and S2).

The two selection lines S1 and S2 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register and transfer
them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of
all four multiplexers are selected and applied to the outputs that forms the bus.
This, in turn, causes the bus lines to receive the content of register A since the
outputs of this register are connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive
the content provided by register B.
The following function table shows the register that is selected by the bus for each
of the four possible binary values of the Selection lines.
A bus system can also be constructed using three-state gates instead of
multiplexers. The three state gates can be considered as a digital circuit that has
three gates, two of which are signals equivalent to logic 1 and 0 as in a
conventional gate. However, the third gate exhibits a high-impedance state. The
most commonly used three state gates in case of the bus system is a buffer gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with three-state
buffers.
  The outputs generated by the four buffers are connected to form a single bus line.
 Only one buffer can be in active state at a given point of time.
 The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.
 A 2 * 4 decoder ensures that no more than one control input is active at any given point
of time.

Memory Transfer

Most of the standard notations used for specifying operations on memory transfer
are stated below.

 The transfer of information from a memory unit to the user end is called a Read
operation.
 The transfer of new information to be stored in the memory is called a Write operation.
 A memory word is designated by the letter M.
 We must specify the address of memory word while writing the memory transfer
operations.
 The address register is designated by AR and the data register by DR.
 Thus, a read operation can be stated as:

Read: DR ← M [AR]
 The Read statement causes a transfer of information into the data register (DR) from the
memory word (M) selected by the address register (AR).
 And the corresponding write operation can be stated as:

Write: M [AR] ← R1
 The Write statement causes a transfer of information from register R1 into the memory
word (M) selected by address register (AR).
1.7. Processor organizations

Processor Organizations:

There are 3 types of Processor organizations

1. Stored Program Organization

2. General Register Organization
3. Stack Organization

1. Stored Program Organization:

The simplest way to organize a computer is to have one processor register and
instruction code format with two parts. The first part specifies the operation to be
performed and the second specifies an address. The memory address tells the
control where to find an operand in memory. This operand is read from memory
and used as the data to be operated on together with the data stored in the
processor register. Figure 5.1 depicts this type of organization. Instructions are
stored in one section of memory and data in another. For a memory unit with 4096
words we need 12 bits to specify an address since 212 = 4096. If we store each
instruction code in one 16-bit memory word, we have available four bits for the
operation code (abbreviated op code) to specify one out of 16 possible operations,
and 12 bits to specify the address of an operand. The control reads a 16-bit
instruction from the program portion of memory. It uses the 12-bit address part of
the instruction to read a 16-bit operand from the data portion of memory. It then
executes the operation specified by the operation code.
Computers that have a single-processor register usually assign to it the name
accumulator and label it AC. The operation is performed with the memory operand
and the content of AC.
Computers that have a single-processor register usually assign to it the name
accumulator and label it AC. The operation is performed with the memory operand
and the content of AC.

2. General Register Organization

 Memory locations are needed for storing pointers, counters, return addresses, temporary
results, and partial products during multiplication.
 Having to refer to memory locations for such applications is time consuming
because memory access is the most time-consuming, operation in a computer.
 It is more convenient and more efficient to store these intermediate values in
processor registers.
 When a large number of registers are included in the CPU, it is most efficient to connect
them through a common bus system. The registers communicate with each other not only
for direct data transfers, but also while performing various microoperations.
 Hence it is necessary to provide a common unit that can perform all the arithmetic,
logic, and shift microoperations in the processor.
 A bus organization for seven CPU registers is shown in Fig. 2. The output of each register is
connected to two multiplexers (MUX) to form the two buses A and B. The selection lines in
each multiplexer select one register or the input data for the particular bus.
 The A and B buses form the inputs to a common arithmetic logic unit (ALU).
 The operation selected in the ALU determines the arithmetic or logic micro-operation that is
to be performed.
 The result of the microoperation is available for output data and also goes into the inputs of
all the registers.
 The register that receives the information from the output bus is selected by a decoder.
 The decoder activates one of the register load inputs, thus providing a transfer path
between the data in the output bus and the inputs of the selected destination register.
 the control unit that operates the CPU bus system directs the information flow through the
registers and ALU by selecting the various components in the system. For example, to
perform the operation R1 ← R2 + R3
 the control must provide binary selection variables to the following selector inputs:
 MUX A selector (SELA): to place the content of R2 into bus A.
 MUX B selector (SELB): to place the content o f R 3 into bus B.
 ALU operation selector (OPR): to provide the arithmetic addition A + B.
 Decoder destination selector (SELD): to transfer the content of the output bus into R1.
 The four control selection variables are generated in the control unit and must be available
at the beginning of a clock cycle.
 The data from the two source registers propagate through the gates in the multiplexers and
the ALU, to the output bus, and into the inputs of the destination register, all during the
clock cycle interval.
 Then, when the next clock transition occurs, the binary information from the output bus is
transferred into R1.
  To achieve a fast response time, the ALU is constructed with high-speed circuits.

3. Stack Organization
Stack is a storage structure that stores information in such a way that the last item
stored is the first item retrieved. It is based on the principle of LIFO (Last-in-first-
out). The stack in digital computers is a group of memory locations with a register
that holds the address of top of element. This register that holds the address of top
of element of the stack is called Stack Pointer.
The two operations of a stack are:
1. Push: Inserts an item on top of stack.
2. Pop: Deletes an item from top of stack.

Implementation of Stack
1. Register Stack
2. Memory Stack.
Register Stack

A stack can be organized as a collection of finite number of registers that are used
to store temporary information during the execution of a program. The stack
pointer (SP) is a register that holds the address of top of element of the stack.

Memory Stack

A stack can be implemented in a random access memory (RAM) attached to a

CPU. The implementation of a stack in the CPU is done by assigning a portion of
memory to a stack operation and using a processor register as a stack pointer. The
starting memory location of the stack is specified by the processor register as stack
pointer.

1.8. Addressing Modes

The addressing modes help us specify the way in which an operand’s effective
address is represented in any given instruction. Some addressing modes allow
referring to a large range of areas efficiently, like some linear array of addresses
along with a list of addresses. The addressing modes describe an efficient and
flexible way to define complex effective addresses.
The programs are generally written in high-level languages, as it’s a convenient
way in which one can define the variables along with the operations that a
programmer performs on the variables. This program is later compiled so as to
generate the actual machine code. A machine code includes low- level
instructions.
A set of low-level instructions has operands and opcodes. An addressing mode has
no relation with the opcode part. It basically focuses on presenting the address of
the operand in the instructions.

Addressing Modes Types

The addressing modes refer to how someone can address any given memory
location. Five different addressing modes or five ways exist using which this can
be done.
You can find the list below, showing the various kind of addressing modes:

 Implied Mode
 Immediate Mode
 Register Mode
 Register Indirect Mode
 Autodecrement Mode
 Autoincrement Mode
 Direct Address Mode
 Indirect Address Mode
 Indexed Addressing Mode
Before getting into discussing the addressing modes, one must understand more
about the “effective address” term.

Effective Address (EA)

The effective address refers to the address of an exact memory location in which
an operand’s value is actually present. Let us now explain all of the addressing
modes.
Implied Mode
In the implied mode, the operands are implicitly specified in the definition of
instruction. For instance, the “complement accumulator” instruction refers to an
implied-mode instruction. It is because, in the definition of the instruction, the
operand is implied in the accumulator register. All the register reference
instructions are implied-mode instructions that use an accumulator.
Immediate Mode
In the immediate mode, we specify the operand in the instruction itself. Or, in
simpler words, instead of an address field, the immediate-mode instruction
consists of an operand field. An operand field contains the actual operand that is to
be used in conjunction with an operation that is determined in the given
instruction. The immediate-mode instructions help initialize registers to a certain
constant value.

Register Mode
In the register mode, the operands exist in those registers that reside within a CPU.
In this case, we select a specific register from a certain register field in the given
instruction. The k-bit field is capable of determining one 2k register.

Register Indirect Mode

In the register indirect mode, the instruction available to us defines that particular
register in the CPU whose contents provides the operand’s address in the memory.
In simpler words, any selected register would include the address of an operand
instead of the operand itself.
The reference to a register is equivalent to specifying any memory address. The
pros of using this type of instruction are that an instruction’s address field would
make use of fewer bits to select a register than would be require when someone
wants to directly specify a memory address.

Autodecrement or the Autoincrement Mode

The Autodecrement or Autoincrement mode is very similar to the register indirect
mode. The only exception is that the register is decremented or incremented before
or after its value is used to access memory. When the address stored in the register
defines a data table in memory, it is very crucial to decrement or increment the
register after accessing the table every time. It can be obtained using the
decrement or increment instruction.
Direct Address Mode
In the direct address mode, the address part of the instruction is equal to the
effective address. The operand would reside in memory, and the address here is
given directly by the instruction’s address field. The address field would specify
the actual branch address in a branch-type instruction.

Indirect Address Mode

In an indirect address mode, the address field of an available instruction gives that
address in which the effective address gets stored in memory. The control fetches
the instruction available in the memory and then uses its address part in order to
(again) access memory to read its effective address.
Indexed Addressing Mode
In the indexed addressing mode, the content of a given index register gets
added to an instruction’s address part so as to obtain the effective address.
Here, the index register refers to a special CPU register that consists of an
index value. An instruction’s address field defines the beginning address of any
data array present in memory.