Question 2
Answer:
Drawbacks of Clocked RS Flip-Flop
A clocked RS flip-flop has the following issues:
1. Indeterminate State (S = 1, R = 1): The output is unpredictable
when both inputs are high.
2. No Toggle Functionality: The RS flip-flop cannot toggle its state
(switch between 0 and 1) directly.
3. Propagation Delay: The time taken for output to stabilize after an
input change may cause glitches.
4. Asynchronous Behavior: If S and R inputs change at the same time,
the flip-flop's response may be uncertain.
Operation of JK Flip-Flop
A JK flip-flop overcomes the limitations of an RS flip-flop. It has two inputs: J
(Set) and K (Reset). It operates based on the clock pulse.
Truth Table of JK Flip-Flop
Q(n Q(n+ Operatio
J K
) 1) n
No
00 0 0
Change
No
00 1 1
Change
No
01 0 0
Change
01 1 0 Reset
10 0 1 Set
No Characteristic Equation of JK Flip-
10 1 1
Flop Change
The 11 0 1 Toggle characteristic equation is derived
as 11 1 0 Toggle follows:
Q(n+1)=JQ′+K′QQ(n+1)=JQ′+K′Q
Where:
Q(n)Q(n) is the present state.
Q(n+1)Q(n+1) is the next state.
J and K control the state transition.
Circuit Diagram of JK Flip-Flop
A JK flip-flop can be implemented using NAND gates as shown below:
J --------|>o|--|
| |
Q -------| |---- Q(next)
| |
K --------|>o|--|
The circuit contains feedback paths to allow toggling when J=K=1.
Timing Diagram of JK Flip-Flop
A timing diagram shows the relationship between J, K, Clock, and Output
(Q) over time.
When J = 1 and K = 0 → Q is set to 1.
When J = 0 and K = 1 → Q is reset to 0.
When J = 1 and K = 1 → Q toggles on each clock pulse.
Question 3
Solution
A sequential circuit using a JK flip-flop based on the given state
diagram.
Step 1: Information from the State Diagram
The state diagram shows transitions between states based on input values.
Present Inpu Next
State t State
00 0 01
00 1 11
01 0 00
01 1 10
10 0 01
10 1 11
11 0 00
11 1 10
Step 2: Assign Flip-Flops
we have two states (Q1 and Q0), we use two JK flip-flops.
Each state is represented as:
00 → State A
01 → State B
10 → State C
11 → State D
tep 3: Determine Flip-Flop Excitation Table
For JK flip-flops, we determine the excitation table based on required
transitions.
Q1 Inpu Next Q1 J1 J0
Q0 t Q0 K1 K0
00 0 01 0X 10
00 1 11 10 10
01 0 00 0X 01
01 1 10 10 X1
10 0 01 X1 10
10 1 11 X1 X0
11 0 00 01 01
11 1 10 01 X1
Where:
J1, K1 control the first flip-flop (Q1).
J0, K0 control the second flip-flop (Q0).
X represents "don't care" conditions.
Step 4: Obtain Boolean Equations using Karnaugh Maps (K-Maps)
Using K-map simplification, we derive expressions for J1, K1, J0, and K0.
Expression for J1
J1=X+Q0J1=X+Q0
Expression for K1
K1=X⋅Q0K1=X⋅Q0
Expression for J0
J0=XJ0=X
Expression for K0
K0=Q1K0=Q1
tep 5: Implement the Circuit
Using the simplified Boolean equations, we draw the logic circuit:
1. J1 and K1 are determined by Q0.
2. J0 and K0 depend on X and Q1.
3. The circuit is constructed using AND, OR, and NOT gates to satisfy the
equations.
