THREE IN ONE

VLSI INTERVIEW GUIDE

IDEAL FOR:
Verification Engineers
RTL Design Engineers
FPGA Developers
VLSI Freshers & Professionals
ASIC/SoC Design & Verification Aspirants
Job Seekers in Core Electronics
 DIGITAL DESIGN – ADVANCED
INTERVIEW QUESTIONS
Ideal for: VLSI Job Interviews | RTL Designers | FPGA
Engineers | Physical Design Aspirants

1. What is metastability? How is it avoided?

Answer:
Metastability is an uncertain state between logic 0
and 1 in flip-flops due to violating setup/hold
times. Occurs during asynchronous signal capture.
Avoid by:
Using two-stage synchronizers
Employing Gray codes in counters
CDC (Clock Domain Crossing) methodology

2. How does pipelining improve throughput? Give a

practical example.
Answer:
Pipelining breaks a long operation into smaller
stages to process multiple operations
concurrently.
Throughput ↑ (one result per clock), but
latency remains.
Example:
3-stage multiplier: While Stage 3 processes
result-1, Stage 2 processes result-2, Stage 1
starts result-3.

3. What is retiming in digital design?

Answer:
Retiming is the movement of flip-flops across
logic gates to balance delay and optimize clock
frequency.
Used to:
Minimize critical path
Balance pipeline stages

4. Can a combinational loop exist in RTL? What are

the consequences?
Answer:
Yes, but it should be avoided.
Combinational loop: Output feeds back to input
without flip-flop → causes non-deterministic
behavior, oscillations, or synthesis failure.
Solution:
Insert registers or redesign logic to break loop
5. What are setup and hold margins? How are they
ensured in real chips?
Answer:
Margins = extra timing budget added by STA
tools to account for variations
Ensured via:
Timing pessimism
Derating
Corner analysis (SS, FF, TT)

6. Explain CDC issues. What techniques are used to

resolve them?
Answer:
Clock Domain Crossing (CDC) issues occur when
signals transfer from one clock domain to another,
causing:
Metastability
Data loss
Glitches
Solutions:
Two-stage synchronizers
Handshake protocols
Asynchronous FIFOs
Gray coding for counters
7. How do you balance combinational paths in
pipeline stages?
Answer:
Use retiming and buffer insertion to equalize
delay
Ensure minimum slack in all stages for
maximum throughput
Insert buffers where delay is low; split heavy logic
across stages

8. What is fan-out? What happens if it’s too large?

Answer:
Fan-out: Number of gates driven by a single
output
Large fan-out → increased load capacitance →
longer delay
Fix:
Use buffer chains
Reduce number of loads
Clock-tree optimization
9. What is logic synthesis? What optimizations does
it perform?
Answer:
Logic synthesis = Convert RTL → gate-level
netlist
Tool optimizations:
Area optimization
Timing closure
Power reduction
Retiming
State encoding optimization (FSMs)
Example: Replacing mux logic with priority gates

10. What is glitch in combinational circuits? How

can it be avoided?
Answer:
Glitch: An unwanted short pulse due to unequal
path delays in a combinational logic circuit.
Happens when multiple inputs change
simultaneously but the signal paths have
different delays.
Avoidance:
Use hazard-free logic design
Add synchronizing flip-flops
Balance logic path delays
11. What is metastability? How do we mitigate it in
digital designs?
Answer:
Metastability occurs when a flip-flop's input
violates setup or hold time, leading to an
undefined output (neither 0 nor 1).
Common in CDC (clock domain crossing).
Mitigation:
Use 2 or 3-stage synchronizers
Ensure proper timing budget (setup/hold
margins)
Use an example with CDC flip-flop synchronizer
chain.

12. How do you avoid race-around condition in a JK

flip-flop?
Answer:
Race-around happens when J=K=1 and clock is
high too long → output toggles continuously.
Avoided using:
Edge-triggered flip-flops
Master-slave configuration
13. What is RTL? What are its key components in
digital design?
Answer:
RTL: Register Transfer Level → abstraction
describing the flow of data between registers
and logic operations.
Key components:
Flip-flops/registers
Combinational logic
State machines
RTL is the input to synthesis tools and is typically
written in Verilog/VHDL.

14. Explain one-hot encoding. Why is it used in

FSMs?
Answer:
One-hot encoding assigns a separate flip-flop
per state → only one flip-flop active (hot) at a
time.
Pros:
Simplifies combinational logic
Fast transitions, minimal decoding logic
Cons:
Higher area (more flip-flops)
Best used when number of states is small, speed is
critical.
15. How do you handle multiple clock domains in a
large chip?
Answer:
Use CDC synchronizers, asynchronous FIFOs,
and clock domain managers
Follow design guidelines like:
No combinational logic across domains
Use Gray code counters for counters sent
across clocks
FIFO write-clock and read-clock with handshaking

16. What are the different types of hazards in

digital design?
Answer:
1. Static hazard: Output momentarily changes
when it should remain constant
2. Dynamic hazard: Output oscillates multiple
times
3. Functional hazard: Due to multiple signal
changes simultaneously
Solved by:
Redundant logic
Path delay balancing
Using hazard-free Karnaugh maps
17. What’s the impact of clock skew in a sequential
circuit? How is it addressed?
Answer:
Clock skew: Difference in arrival time of clock
signal at different flip-flops.
Can cause:
Hold time violations
Setup time violations
Functional failure
Fixes:
Clock tree synthesis (CTS)
Use clock buffers
Balancing path delays
Deskewing circuits

18. What are false paths and multi-cycle paths?

How do you handle them?
Answer:
False Path: A path that will never be activated
functionally, e.g., due to mutually exclusive control
signals.
Multi-cycle Path: A path intentionally allowed to
take more than one clock cycle.
Handling:
Use SDC constraints:
set_false_path -from A -to B
set_multicycle_path 2 -from A -to B

19. What is a scan chain? Why is it used?

Answer:
Used in DFT (Design for Testability).
Combines flip-flops into a chain to shift test
vectors in and out.
Benefits:
Observability & controllability
Easy stuck-at fault detection

20. What is reconvergent fanout?

Answer:
A reconvergent fanout occurs when a signal
branches and the branches reconverge at a
later point.
Important in Static Timing Analysis and test
coverage.
May require path-based analysis due to correlation.
 VERILOG – ADVANCED
INTERVIEW QUESTIONS
Ideal for: RTL Design Engineers | FPGA Developers | ASIC
Verification Enthusiasts | VLSI Interview Preparation

1. Write Verilog code for an edge detector

Answer:
module edge_detector (
input clk,
input sig,
output reg rise
);
reg sig_d;
always @(posedge clk) begin
sig_d <= sig;
rise <= sig & ~sig_d;
end
endmodule

2.Write Verilog code for a 32-bit register with load

and reset.
Answer:
module register_32bit (
input clk,
input rst,
 input load,
input [31:0] d,
output reg [31:0] q
);
always @(posedge clk or posedge rst) begin
if (rst)
q <= 32'h0;
else if (load)
q <= d;
end
endmodule

3. Write Verilog code for clock divider by 4.

Answer:
module clk_div4 (
input clk, rst,
output reg clk_out
);
reg [1:0] count;
always @(posedge clk or posedge rst) begin
if (rst) begin
count <= 2'b0;
clk_out <= 1'b0;
end else begin
count <= count + 1;
 if (count == 2'b11)
clk_out <= ~clk_out;
end
end
endmodule

4. Write Verilog code to implement a pulse

stretcher.
Answer:
module pulse_stretcher (
input clk, rst, in_pulse,
output reg out_pulse
);
reg [2:0] count;
always @(posedge clk or posedge rst) begin
if (rst) begin
out_pulse <= 0;
count <= 0;
end else if (in_pulse) begin
out_pulse <= 1;
count <= 3;
end else if (count > 0) begin
count <= count - 1;
out_pulse <= 1;
 end else
out_pulse <= 0;
end
endmodule

5. Write Verilog code to detect a glitch (1-cycle

pulse) on an input signal.
Answer:
module glitch_detector (
input clk,
input sig,
output reg glitch
);
reg sig_d1, sig_d2;
always @(posedge clk) begin
sig_d1 <= sig;
sig_d2 <= sig_d1;
glitch <= sig_d1 ^ sig_d2;
end
endmodule

6. Write Verilog code for a pulse generator with

pulse width of 3 clock cycles.
Answer:
module pulse_generator (
 output reg pulse
);
reg [1:0] count;
reg active;

always @(posedge clk or posedge rst) begin

if (rst) begin
count <= 0;
pulse <= 0;
active <= 0;
end else if (trigger && !active) begin
active <= 1;
count <= 2;
pulse <= 1;
end else if (active) begin
if (count == 0) begin
pulse <= 0;
active <= 0;
end else begin
count <= count - 1;
end
end
end
endmodule
7. Write Verilog code for an asynchronous FIFO
(conceptual model only).
Answer:
module async_fifo (
input wr_clk, wr_en,
input rd_clk, rd_en,
input [7:0] din,
output reg [7:0] dout,
output reg empty, full
);
reg [7:0] mem [7:0];
reg [2:0] wr_ptr, rd_ptr;

always @(posedge wr_clk) begin

if (wr_en && !full) begin
mem[wr_ptr] <= din;
wr_ptr <= wr_ptr + 1;
end
end

always @(posedge rd_clk) begin

if (rd_en && !empty) begin
dout <= mem[rd_ptr];
rd_ptr <= rd_ptr + 1;
end
end
always @(*) begin
full = (wr_ptr + 1 == rd_ptr);
empty = (wr_ptr == rd_ptr);
end
endmodule

8. Write Verilog code for a 4x4-bit multiplier using

add-and-shift logic.
Answer:
module mult_4bit (
input [3:0] a, b,
output [7:0] product
);
reg [7:0] p;
integer i;
always @(*) begin
p = 0;
for (i = 0; i < 4; i = i + 1)
if (b[i])
p = p + (a << i);
end
assign product = p;
endmodule
9. Write Verilog code for a dual-edge triggered flip-
flop.
Answer:
module dual_edge_ff (
input clk, d,
output reg q
);
reg q1, q2;
always @(posedge clk)
q1 <= d;
always @(negedge clk)
q2 <= d;
always @(*)
q = clk ? q1 : q2;
endmodule

10. Write Verilog code to implement a debouncer

for a push-button.
Answer:
module debouncer (
input clk, rst, noisy,
output reg clean
);
reg [3:0] shift;
always @(posedge clk or posedge rst) begin
if (rst) begin
shift <= 0;
clean <= 0;
end else begin
shift <= {shift[2:0], noisy};
if (shift == 4'b1111)
clean <= 1;
else if (shift == 4'b0000)
clean <= 0;
end
end
endmodule

11. Write Verilog code for a signed saturating adder

(8-bit).
Answer:
module saturating_adder (
input signed [7:0] a, b,
output reg signed [7:0] sum
);
wire signed [8:0] temp_sum = a + b;
always @(*) begin
if (temp_sum > 127)
sum = 127;
 else if (temp_sum < -128)
sum = -128;
else
sum = temp_sum[7:0];
end
endmodule
12. Write Verilog code to generate a 50% duty cycle
clock from an input clock of any frequency.
Answer:
module clock_div_2 (
input clk, rst,
output reg clk_out
);
always @(posedge clk or posedge rst) begin
if (rst)
clk_out <= 0;
else
clk_out <= ~clk_out;
end
endmodule
13. Write synthesizable Verilog code to implement a
rising edge detector.
Answer:
module rising_edge_det (
input clk, rst, signal_in,
output pulse_out
);
reg signal_d;

always @(posedge clk or posedge rst) begin

if (rst)
signal_d <= 0;
else
signal_d <= signal_in;
end

assign pulse_out = signal_in & ~signal_d;

endmodule

14. Write a Verilog module to implement a counter

that counts from 5 to 13 and wraps around.
Answer:
module counter_5_to_13 (
input clk, rst,
output reg [3:0] count
);
always @(posedge clk or posedge rst) begin
if (rst)
count <= 4'd5;
else if (count == 4'd13)
count <= 4'd5;
else
count <= count + 1;
end
endmodule

15. Write Verilog code for a synchronous one-hot

FSM with three states.
Answer:
module one_hot_fsm (
input clk, rst,
output reg [2:0] state
);
parameter IDLE=3'b001, LOAD=3'b010,
DONE=3'b100;
always @(posedge clk or posedge rst) begin
if (rst)
state <= IDLE;
else begin
case (state)
IDLE: state <= LOAD;
 LOAD: state <= DONE;
DONE: state <= IDLE;
default: state <= IDLE;
endcase
end
end
endmodule

16. Write Verilog code for a pipelined 4-stage adder

for 8-bit inputs.
Answer:
module pipelined_adder (
input clk,
input [7:0] a, b,
output reg [8:0] sum
);
reg [7:0] a_pipe [0:3];
reg [7:0] b_pipe [0:3];
integer i;
always @(posedge clk) begin
a_pipe[0] <= a; b_pipe[0] <= b;
for (i = 1; i < 4; i = i + 1) begin
a_pipe[i] <= a_pipe[i-1];
b_pipe[i] <= b_pipe[i-1];
end
 sum <= a_pipe[3] + b_pipe[3];
end
endmodule

17. Write Verilog code to implement a configurable

width register with synchronous reset.
Answer:
module flex_reg #(parameter WIDTH=8)(
input clk, rst,
input [WIDTH-1:0] d,
output reg [WIDTH-1:0] q
);
always @(posedge clk) begin
if (rst)
q <= 0;
else
q <= d;
end
endmodule

18. Write Verilog code for a signed multiplier using

shift-and-add.
Answer:
module signed_multiplier (
input signed [3:0] a, b,
 output reg signed [7:0] product
);
integer i;
reg signed [7:0] temp_a, temp_b;

always @(*) begin

product = 0;
temp_a = a;
temp_b = b;
for (i = 0; i < 4; i = i + 1)
if (temp_b[i])
product = product + (temp_a << i);
end
endmodule

19. Write Verilog code to detect 4 consecutive 1’s

in a serial data stream.
Answer:
module detect_4_ones (
input clk, rst, din,
output reg detect
);
reg [3:0] shift;
always @(posedge clk or posedge rst) begin;
if (rst) begin
 shift <= 0;
detect <= 0;
end else begin
shift <= {shift[2:0], din};
detect <= (shift == 4'b1111);
end
end
endmodule

20. Write Verilog code for a RAM with 4-bit

address, 8-bit data, and write-enable.
Answer:
module ram_sync (
input clk, we,
input [3:0] addr,
input [7:0] din,
output reg [7:0] dout
);
reg [7:0] mem [0:15];
always @(posedge clk) begin
if (we)
mem[addr] <= din;
dout <= mem[addr];
end
endmodule
 SYSTEMVERILOG – ADVANCED
INTERVIEW QUESTIONS
Ideal for: ASIC Verification Engineers | UVM Developers
| RTL Coders | System-Level Designers

1. Implement a parameterized queue-based FIFO

using SystemVerilog class.
Answer:
class fifo #(type T = int, int DEPTH = 8);
rand T q[$];
function void push(T data);
if (q.size() < DEPTH)
q.push_back(data);
else
$display("FIFO Full");
endfunction

function T pop();
if (q.size() > 0)
return q.pop_front();
else begin
$display("FIFO Empty");
return '0;
end
endfunction
 function int size();
return q.size();
endfunction
endclass

2. Create a virtual interface and bind it to a DUT.

Answer:
interface alu_if(input bit clk);
logic [3:0] a, b;
logic [3:0] result;
logic op; // 0: add, 1: sub
endinterface
module alu(alu_if intf);
always_ff @(posedge intf.clk) begin
if (intf.op == 0)
intf.result <= intf.a + intf.b;
else
intf.result <= intf.a - intf.b;
end
endmodule

module top;
logic clk;
alu_if intf(clk);
alu u1(intf);
endmodule
3. Write a SystemVerilog constraint to generate an
even number between 10 and 100 divisible by 6.
Answer:
class gen_num;
rand int x;
constraint c1 {
x inside {[10:100]};
x % 2 == 0;
x % 6 == 0;
}
endclass

4. Write a SystemVerilog covergroup to monitor bus

transactions.
Answer:
class bus_monitor;
logic [3:0] addr;
logic [7:0] data;
covergroup cg @(posedge clk);
coverpoint addr {
bins all_addrs[] = {[0:15]};
}
coverpoint data {
bins low = {[0:63]};
 bins high = {[64:255]};
}
endgroup

function new();
cg = new();
endfunction
endclass

5. Implement a polymorphic class hierarchy for

packet types.
Answer:
class packet;
rand bit [7:0] id;
virtual function void display();
$display("Packet ID: %0d", id);
endfunction
endclass
class data_packet extends packet;
rand bit [31:0] payload;
function void display();
super.display();
$display("Data: %0h", payload);
endfunction
endclass
class ctrl_packet extends packet;
rand bit [3:0] opcode;
function void display();
super.display();
$display("Opcode: %0d", opcode);
endfunction
endclass

6. Use a typedef enum with a case inside a class

method.
Answer:
typedef enum {IDLE, READ, WRITE} state_t;

class fsm;
state_t current;
function void next_state(state_t s);
case (s)
IDLE: $display("State: IDLE");
READ: $display("State: READ");
WRITE: $display("State: WRITE");
default: $display("Unknown");
endcase
endfunction
endclass
7. Demonstrate with clause in constrained
randomization.
Answer:
class item;
rand int a, b;
endclass
module tb;
item it = new();
initial begin
void'(it.randomize() with { a > b; a < 100; b > 10;
});
$display("a = %0d, b = %0d", it.a, it.b);
end
endmodule

8. Create a dynamic array of objects and randomize

each with different seeds.
Answer:
class pkt;
rand int val;
endclass
module tb;
pkt pkt_arr[10];
initial begin
 foreach(pkt_arr[i]) begin
pkt_arr[i] = new();
pkt_arr[i].randomize() with { val inside {[0:100]};
};
$display("pkt[%0d] = %0d", i, pkt_arr[i].val);
end
end
endmodule

9. Show how to override a method using super in a

derived class.
Answer:
class base;
function void say();
$display("Base class");
endfunction
endclass

class derived extends base;

function void say();
super.say();
$display("Derived class");
endfunction
endclass
10. Implement a mailbox with blocking get and
show inter-thread communication.
Answer:
module tb;
mailbox #(int) mbx = new();

initial begin
#10;
int val;
mbx.get(val);
$display("Received: %0d", val);
end
initial begin
#5;
mbx.put(42);
end
endmodule

11. Write a class with nested class to represent a

configurable packet structure.
Answer:
class packet;
rand bit [7:0] header;
class payload;
 rand bit [31:0] data;
function void display();
$display("Payload Data: %0h", data);
endfunction
endclass

payload p = new();

function void display();

$display("Header: %0h", header);
p.display();
endfunction
endclass

12. Implement inline constraints to generate an

address that is 16-byte aligned between 0x1000
and 0x2000.
Answer:
class addr_gen;
rand bit [31:0] addr;
endclass

module tb;
addr_gen ag = new();
 initial begin
void'(ag.randomize() with {
addr inside {[32'h1000:32'h2000]};
addr % 16 == 0;
});
$display("Aligned Address: %0h", ag.addr);
end
endmodule

13. Create a class factory with different object

types and dynamically create objects.
Answer:
class base;
virtual function void disp(); endfunction
endclass

class A extends base;

function void disp(); $display("Class A");
endfunction
endclass

class B extends base;

function void disp(); $display("Class B");
endfunction
endclass
module tb;
base obj;
string type = "B";

initial begin
if (type == "A")
obj = new A;
else
obj = new B;
obj.disp();
end
endmodule

14. Cover cross coverage between opcode and

address range.
Answer:
module tb;
logic [3:0] opcode;
logic [7:0] addr;

covergroup cg @(posedge clk);

coverpoint opcode;
coverpoint addr {
bins range1 = {[0:63]};
bins range2 = {[64:127]};
 }
cross opcode, addr;
endgroup

initial begin
cg = new();
// drive values and sample
end
endmodule

15. Demonstrate post_randomize() usage in a class.

Answer:
class trans;
rand int a, b, sum;
function void post_randomize();
sum = a + b;
endfunction
endclass
module tb;
trans t = new();
initial begin
void'(t.randomize());
$display("a=%0d b=%0d sum=%0d", t.a, t.b,
t.sum);
end
endmodule
16. Use a dynamic array inside a class and
randomize its contents.
Answer:
class mem_block;
rand bit [7:0] mem[];

constraint c {
mem.size() == 8;
foreach (mem[i])
mem[i] inside {[0:255]};
}
endclass

17. Build a scoreboard class to compare expected

vs actual values.
Answer:
class scoreboard;
mailbox #(int) exp, act;
function new();
exp = new();
act = new();
endfunction
task compare();
int e, a;
 forever begin
exp.get(e);
act.get(a);
if (e !== a)
$display("Mismatch: Exp=%0d Act=%0d", e, a);
else
$display("Match: %0d", a);
end
endtask
endclass

18. Demonstrate constraint inheritance and

override.
Answer:
class base;
rand int x;
constraint c { x < 100; }
endclass

class child extends base;

constraint c_override { x > 50; }
endclass
19. Write a function to return the highest value in a
dynamic array.
Answer:
function int get_max(input int arr[]);
int max = arr[0];
foreach (arr[i])
if (arr[i] > max)
max = arr[i];
return max;
endfunction

20. Explain and implement the randc qualifier.

Answer:
class randc_test;
randc bit [2:0] val;
endclass
module tb;
randc_test rt = new();
initial begin
repeat (8) begin
rt.randomize();
$display("val = %0d", rt.val);
end
end
endmodule
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