Tessolve Semiconductor Private Limited
Training
Verilog TEST
Marks: 15
Questions
1) What function does the following Verilog module implement?
module funtionality (f, a, b, c);
input a,b,c;
output f, wire t;
assign t = (a & b) | c;
assign f = a ^ t;
endmodule
a) f = a’.b + a’.b’.c
b) f = a’.c + a.b’.c’
c) f = a’.c + a’.b.c’
d) None of the above
2) Consider the following Verilog module.
module guess (data, cond, result);
input [7:0] data;
input [1:0] cond;
output reg [7:0] result;
always @(data) begin if (cond == 2’b01) result = data;
else if (cond == 2’b10) result = data + 1;
else if (cond == 2’b11) result = data – 1;
end
endmodule
Which of the following is true when the module is synthesized?
a) A combinational circuit will be generated.
b) A sequential circuit with storage elements will be generated.
c) If the synthesizer supports adder and subtractor blocks, a combinational
circuit will be generated.
d) None of the above.
3) What will the following code segment generate on synthesis, assuming that
the three variables x0, x1 and x2 map into three latches/ flip-flops?
always@(posedge clock)
x2=in;
always@(posedge clock)
x1=x2;
always@(posedge clock)
x0=x1;
a) A 3-bit shift register
b) Three D flip-flops all fed with the data “in”
c) Values of x0 and x1 will be indeterminate
d) A 3-bit parallel load register
4) Which of the following are true for the following code segment?
input [31:0] a;
input [0:4] b;
input sel;
output f;
assign f = sel ? a[b] : 1’b0;
a) One 32-to-1 and one 2-to-1 multiplexers will be generated.
b) One 2-to-1 multiplexer will be generated.
c) A single large multiplexer will be generated.
d) None of the above.
5) Which of the following constructs will be generating a decoder /
demultiplexer, where “a”, “b” and “c” are variables?
a) assign a = b[c];
b) assign b[c] = a;
c) assign a = (b) ? c : ~c;
d) assign a = b & c
6) What will the following code segment generate?
Input clk, in;
output reg [N-1:0]out;
always@(posedge clk)
begin
out[0]<= in;
genvar x;
generate for (x=1; x<N; x=x+1)
begin fun_loop
out[x]<= out[x-1];
end
end
a) All N D-flip-flop will be initialized to the value of “in” at every positive
“clk” edge.
b) A N-1-bit shift register will be synthesized
c) A N-bit arithmetic right shift register will be synthesized
d) A N-bit shift register will be synthesized
7) Which of the following statements is false?
a) A netlist of predefined modules in Verilog represents a structural
representation.
b) The truth table of the function with output column (01010111) represents
a behavioral representation of the function.
c) A netlist consisting of one 2-input XOR and one 2-input OR gate
represents a behavioral representation.
d) None of the above
8) Which of the following is true for the following module?
module mydesign (a, b);
input [1:0] b;
output reg a;
always @(b) begin
if (b == 2’b00) a = 1’b0;
else if (b == 2’b11) a = 1’b1;
end
endmodule
a) A combinational circuit implementing a XOR function will be generated.
b) A combinational circuit implementing an AND function will be generated.
c) A latch will be generated for the output “a”.
d) The synthesis tool will give an error.
9) Generate loop is used for _________.
a) To permits one or more variable declarations
b) For fix number of iteration
c) For A & B
d) None
10) For the following code segment, the final value of variable “c” will be
………….. integer a, b, c;
initial begin
a = 55; b = 10; c = 5;
end
initial
begin
a <= #10 b * c;
b <= #10 a – 25;
c <= #10 a + b;
end
a) 70
b) 75
c) 80
d) 65
11) If a =1 , assign y=(a==2'b11) then value of y will be
a) 1 b) 1’b0 c) 2’b11 d) None of above
12) What does the following code segment do?
reg a, b, c;
integer i;
for (i=0; i<8;i=i+1)
begin {a,b,c} = i;
end
a) Assign the value of “i" to all the three variables a, b, c in the loop.
b) Assign all possible binary patterns to the variables a, b, c.
c) Will give a syntax error on compilation.
d) None of the above.
13) Which loop statement is not used in verilog HDL?
a) for loop b) while loop c) forever loop d) foreach loop
14) What will the following code segment do?
initial
begin int1=42; int2=17; end
always@(posedge clock)
int2=int1;
always@(posedge clock)
int1=int2;
a) A race condition will occur, i.e. both the integer variables will update with
either value of “int1” or “int2”
b) Swap the values of the variables “int1” and “int2”
c) Both variables will get updated with the value 42
d) Both variables will get updated with the value 17
15) If the 8-bit variable “x” declared as ‘reg [7:0] x’ is initialized to 8’b10101101,
What will be its value after execution of the following code segment?
always@(posegde clock)
begin
x<= x<<1;
x[0] <=x[7];
end
a) 8’b01011010
b) 8’b01011011
c) 8’b11010110
d) 8’b01010110
