Chapter 3: Basic

Computer Organization
& Design
Instruction Codes

• The organization of the computer is defined by its:

• internal registers
• the timing and control structures
• the set of instructions

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Instruction Codes
• The internal organization of a digital system is defined by the sequence of
microoperations it performs on data stored in its registers/memory

• The user of a microcontroller/microprocessor can control the process by

means of a program.

• A program is a set of instructions that specify the operations, operands,

and the processing sequence.

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Instruction Codes cont.

• A microcontroller/microprocessor instruction is a binary code that

specifies a sequence of micro-operations for the computer.

• Each computer has its unique instruction set

• Instruction codes and data are stored in memory

• The microcontroller/microprocessor reads each instruction from memory

and places it in a control register

• The control unit interprets the binary code of the instruction and proceeds
to execute it by issuing a sequence of micro-operations

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Instruction Codes cont.

• An Instruction code is a group of bits that instructs the computer to perform

a specific operation (sequence of microoperations).

• It is divided into parts (basic part is the operation part)

• The operation code of an instruction is a group of bits that defines certain

operations such as add, subtract, shift, and complement

• The operation code is sometimes called a macrooperation because it

specifies a set of microoperations

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Instruction Codes cont.

• The number of bits required for the operation code depends on the total
number of operations provided by the microcontroller/microprocessor

• 2n (or little less) distinct operations  n bit operation code

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Instruction Codes cont.

It’s an ADD
Memory operation

Op code
Control
110010?????????? Unit

Read instruction
from memory

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Instruction Codes cont.

• An operation must be performed on some data stored in processor

registers or in memory

• An instruction code must therefore specify not only the operation, but also
the location of the operands (in registers or in the memory), and where the
result will be stored (registers/memory)

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Instruction Codes cont.

• Memory words can be specified in instruction codes by their address

• Processor registers can be specified by assigning to the instruction another

binary code of k bits that specifies one of 2k registers

• Each microcontroller/microprocessor has its own particular instruction

code format

• Instruction code formats are developed by microcontroller/microprocessor

designers who specify the architecture of the Micro.
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Instruction Codes cont.
Stored Program Organization
1 2
• An instruction code is usually divided into operation code, operand address,
addressing mode, etc.
3

• The simplest way to organize a microcontroller/microprocessor is to have

one processor register (accumulator AC) and an instruction code format
with two parts (op code, address)

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Instruction Codes
Stored Program Organization cont.
15 12 11 0 Memory
Opcode Address 15
4096x16
0
Instruction Format
Instructions
15 0
(program)
Binary Operand

Operands
(data)

15 0

Processor register
(Accumulator AC)

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Instruction Codes
Indirect Address
• There are three Addressing Modes used for address portion of the
instruction code:
• Immediate: the operand is given in the address portion (constant)
• Direct: the address points to the operand stored in the memory
• Indirect: the address points to the pointer (another address) stored in
the memory that references the operand in memory.

• One bit of the instruction code can be used to distinguish between direct &
indirect addresses

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Instruction Codes
Indirect Address cont.
Instruction Format Effective address
15 14 12 11 0
I Opcode Address

Direct Address Indirect address

22 0 ADD 457 35 1 ADD 300

300 1350

457 Operand

1350 Operand

+ +
AC AC

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Instruction Codes
Indirect Address cont.

• Effective address: the address of the operand in a computation-type

instruction or the target address in a branch-type instruction

• The pointer can be placed in a processor register instead of memory as

done in commercial microcontroller/ microprocessor

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Computer Registers
• Computer instructions are normally stored in consecutive memory
locations and executed sequentially one at a time

• The control reads an instruction from a specific address in memory and

executes it, and so on

• This type of sequencing needs a counter to calculate the address of the

next instruction after execution of the current instruction is completed

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Computer Registers cont.

• It is also necessary to provide a register in the control unit for storing the
instruction code after it is read from memory

• The microcontroller/microprocessor needs processor registers for

manipulating data and a register for holding a memory address

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 Registers in the Basic Computer
11 0
PC
11 0
AR Memory

15 0 4096 x 16
IR
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC

List of Basic Computer Registers

DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character

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 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR

Adder E
and
logic
AC 4 Computer Registers
LD INR CLR Common Bus System
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
16-bit common bus

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Computer Registers
Common Bus System cont.
• S2S1S0: Selects the register/memory that would use the bus

• LD (load): When enabled, the particular register receives the data from the
bus during the next clock pulse transition

• E (extended AC bit): flip-flop holds the carry

• DR, AC, IR, and TR: have 16 bits each

• AR and PC: have 12 bits each since they hold a memory address
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Computer Registers
Common Bus System cont.
• When the contents of AR or PC are applied to the 16-bit common bus, the
four most significant bits are set to zeros

• When AR or PC receives information from the bus, only the 12 least

significant bits are transferred into the register

• INPR and OUTR: communicate with the eight least significant bits in the
bus

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Computer Registers
Common Bus System cont.
• INPR: Receives a character from the input device (keyboard,…etc) which is
then transferred to AC

• OUTR: Receives a character from AC and delivers it to an output device (say

a Monitor)

• Five registers have three control inputs: LD (load), INR (increment), and CLR
(clear)

• Register  binary counter with parallel load and synchronous clear

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Computer Registers
Memory Address
• The input data and output data of the memory are connected to the
common bus

• But the memory address is connected to AR

• Therefore, AR must always be used to specify a memory address

• By using a single register for the address, we eliminate the need for an
address bus that would have been needed otherwise

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Computer Registers
Memory Address cont.
• Register  Memory: Write operation

• Memory  Register: Read operation (note that AC cannot directly read

from memory!!)

• Note that the content of any register can be applied onto the bus and an
operation can be performed in the adder and logic circuit during the same
clock cycle

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Computer Registers
Memory Address cont.
• The transition at the end of the cycle transfers the content of the bus into
the destination register, and the output of the adder and logic circuit into
the AC

• For example, the two microoperations

DR←AC and AC←DR (Exchange)
can be executed at the same time

• This is done by??

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Computer Registers
Memory Address cont.
• 1- place the contents of AC on the bus (S2S1S0=100)
• 2- enabling the LD (load) input of DR
• 3- Transferring the contents of the DR through the adder and logic circuit
into AC
• 4- enabling the LD (load) input of AC
• All during the same clock cycle
• The two transfers occur upon the arrival of the clock pulse transition at the
end of the clock cycle
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Computer Instructions
Basic Computer Instruction code format

Memory-Reference Instructions (OP-code = 000 ~ 110)

15 14 12 11 0
I Opcode Address

Register-Reference Instructions (OP-code = 111, I = 0)

15 12 11 0
0 1 1 1 Register operation

Input-Output Instructions (OP-code =111, I = 1)

15 12 11 0
1 1 1 1 I/O operation
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BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag if one
SKO F100 Skip on output flag if one
ION F080 Interrupt on
IOF F040 Interrupt off
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Computer Instructions
Instruction Set Completeness
• The set of instructions are said to be complete if the computer includes a
sufficient number of instructions in each of the following categories:
• Arithmetic, logical, and shift instructions
• Instructions for moving information to and from memory and processor
registers
• Program control instructions together with instructions that check
status conditions
• Input & output instructions

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Timing & Control
• The timing for all registers in the basic computer is controlled by a master
clock generator

• The clock pulses are applied to all flip-flops and registers in the system,
including the flip-flops and registers in the control unit

• The clock pulses do not change the state of a register unless the register is
enabled by a control signal (i.e., Load)

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Timing & Control cont.

• The control signals are generated in the control unit and provide control
inputs for the multiplexers in the common bus, control inputs in processor
registers, and microoperations for the accumulator

• There are two major types of control organization:

• Hardwired control
• Microprogrammed control

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Timing & Control cont.

• In the hardwired organization, the control logic is implemented with gates,

flip-flops, decoders, and other digital circuits.

• In the microprogrammed organization, the control information is stored in

a control memory (if the design is modified, the microprogram in control
memory has to be updated)

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The Control Unit for the basic computer
Instruction register (IR)
15 14 13 12 11 - 0 Other inputs

3x8
decoder
7 6543 210
D0
I
D7 Control Control
logic outputs
gates
T15
T0

15 14 . . . . 2 1 0
4 x 16
Sequence decoder

4-bit Increment (INR)

sequence Clear (CLR)
counter
(SC) Clock

Hardwired Control Organization

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- Generated by 4-bit sequence counter and 4x16 decoder
- The SC can be incremented or cleared.

- Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
D3T4: SC  0
T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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Timing & Control cont.

• A memory read or write cycle will be initiated with the rising edge of a
timing signal
• So, a memory read or write cycle initiated by a timing signal will be
completed by the time the next clock goes through its positive edge
• The clock transition will then be used to load the memory word into a
register
• The memory cycle time is usually longer than the processor clock cycle
 wait cycles

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Timing & Control cont.
• T0: AR←PC
• Transfers the content of PC into AR if timing signal T0 is active
• T0 is active during an entire clock cycle interval
• During this time, the content of PC is placed onto the bus (with S2S1S0=010)
and the LD (load) input of AR is enabled
• The actual transfer does not occur until the end of the clock cycle when the
clock goes through a positive transition
• This same positive clock transition increments the sequence counter SC from
0000 to 0001
• The next clock cycle has T1 active and T0 inactive
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Instruction Cycle
• A program is a sequence of instructions stored in memory

• The program is executed in the computer by going through a cycle for each
instruction (in most cases)

• Each instruction in turn is subdivided into a sequence of sub-cycles or

phases

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Instruction Cycle cont.

• Instruction Cycle Phases:

• 1- Fetch an instruction from memory
• 2- Decode the instruction
• 3- Read the effective address from memory if the instruction has an
indirect address
• 4- Execute the instruction
• This cycle repeats indefinitely unless a HALT instruction is encountered

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Instruction Cycle
Fetch and Decode
• Initially, the Program Counter (PC) is loaded with the address of the first
instruction in the program

• The sequence counter SC is cleared to 0, providing a decoded timing

signal T0

• After each clock pulse, SC is incremented by one, so that the timing

signals go through a sequence T0, T1, T2, and so on

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Instruction Cycle
Fetch and Decode cont.
• T0: AR←PC (this is essential!!)
The address of the instruction is moved to AR.

• T1: IR←M[AR], PC←PC+1

The instruction is fetched from the memory to IR , and the PC is
incremented.

• T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)

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BC Instruction cycle: [Fetch Decode [Indirect] Execute]*
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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BC Instruction cycle: [Fetch Decode [Indirect] Execute]*
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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BC Instruction cycle: [Fetch Decode [Indirect] Execute]*
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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BC Instruction cycle: [Fetch Decode [Indirect] Execute]*
• Fetch and Decode T0: AR PC (S0S1S2=010, T0=1)
T1: IR  M [AR], PC  PC + 1 (S0S1S2=111, T1=1)
T2: D0, . . . , D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

T1 S2

T0 S1 Bus

S0
Memory
7
unit
Address
Read

AR 1

LD
PC 2

INR

IR 5

LD Clock
Common bus

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 Start DETERMINE THE TYPE OF INSTRUCTION
SC  0

T0
AR  PC
T1
IR  M[AR], PC  PC + 1
T2
Decode Opcode in IR(12-14),
AR  IR(0-11), I  IR(15)

(Register or I/O) = 1 = 0 (Memory-reference)

D7

(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)

I I

T3 T3 T3 T3
Execute Execute AR  M[AR] Nothing
input-output register-reference
instruction instruction
SC  0 SC  0 Execute T4
memory-reference
instruction
SC  0

D'7IT3: AR M[AR]
D'7I'T3: Nothing
D7I'T3: Execute a register-reference instr.
D7IT3: Execute an input-output instr.

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REGISTER REFERENCE INSTRUCTIONS
Register Reference Instructions are identified when
- D7 = 1, I = 0
- Register Ref. Instr. is specified in B0 ~ B11 of IR
- Execution starts with timing signal T3

r = D7 I’ T3 => Register Reference Instruction

Bi = IR(i) , i=0,1,2,...,11, the ith bit of IR.
r: SC  0
CLA rB11: AC  0
CLE rB10: E0
CMA rB9: AC  AC’
CME rB8: E  E’
CIR rB7: AC  shr AC, AC(15)  E, E  AC(0)
CIL rB6: AC  shl AC, AC(0)  E, E  AC(15)
INC rB5: AC  AC + 1
SPA rB4: if (AC(15) = 0) then (PC  PC+1)
SNA rB3: if (AC(15) = 1) then (PC  PC+1)
SZA rB2: if (AC = 0) then (PC  PC+1)
SZE rB1: if (E = 0) then (PC  PC+1)
HLT rB0: S  0 (S is a start-stop flip-flop)

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 MEMORY REFERENCE INSTRUCTIONS
Operation
Symbol Symbolic Description
Decoder
AND D0 AC  AC  M[AR]
ADD D1 AC  AC + M[AR], E  Cout
LDA D2 AC  M[AR]
STA D3 M[AR]  AC
BUN D4 PC  AR
BSA D5 M[AR]  PC, PC  AR + 1
ISZ D6 M[AR]  M[AR] + 1, if M[AR] + 1 = 0 then PC  PC+1

• The effective address of the instruction is in AR and was placed there during timing signal T2 when I = 0, or
during timing signal T3 when I = 1
• Memory cycle is assumed to be short enough to be completed in a CPU cycle
• - The execution of MR Instruction starts with T4
AND to AC
D0T4: DR  M[AR] Read operand
D0T5: AC  AC  DR, SC  0 AND with AC

ADD to AC
D1T4: DR  M[AR] Read operand
D1T5: AC  AC + DR, E  Cout, SC  0 Add to AC and store carry in E 46
 MEMORY REFERENCE INSTRUCTIONScont.
LDA: Load to AC
D2T4: DR  M[AR]
D2T5: AC  DR, SC  0
STA: Store AC
D3T4: M[AR]  AC, SC  0
BUN: Branch Unconditionally
D4T4: PC  AR, SC  0
BSA: Branch and Save Return Address
M[AR]  PC, PC  AR + 1

Memory, PC, AR at time T4 Memory, PC after execution

20 0 BSA 135 20 0 BSA 135
Return address: PC = 21 Next instruction 21 Next instruction

AR = 135 135 21
136 Subroutine PC = 136 Subroutine

1 BUN 135 1 BUN 135

Memory 47
Memory
 Memory Reference
Instructionscont.

BSA: executed in a sequence of two micro-operations:

D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0

ISZ: Increment and Skip-if-Zero

D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T6: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0

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 Memory-reference instruction

AND ADD LDA STA

D0 T 4 D1 T 4 D2 T 4 D 3T 4
DR M[AR] DR M[AR] DR  M[AR] M[AR]  AC
SC  0

D0 T 5 D1 T 5 D2 T 5
AC  AC  DR AC  AC + DR AC  DR
SC <- 0 E  Cout SC  0
SC  0

BUN BSA ISZ

D4 T 4 D5 T 4 D6 T 4

PC  AR M[AR]  PC DR  M[AR]
SC  0 AR  AR + 1

D5 T 5 D6 T 5

PC  AR DR  DR + 1
SC  0
D6 T 6
M[AR]  DR
If (DR = 0)
then (PC  PC + 1)
SC  0

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