Unit-2
Computer Organization:
Instruction codes, Computer Registers, Common Bus System, Computer Instructions,
Timing and Control, Instruction Cycle, Memory Reference Instructions, Input-output
and Interrupt
Content
Instruction codes
Computer Registers
Common Bus System
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference Instructions
Input-output and Interrupt
Introduction
Organization of computer is defined by its :
Internal Registers
Timing and Control Structure
Set of instructions that it uses
Every different processor type has its own design (different registers, buses, microoperations,
machine instructions, etc.)
Modern processor is a very complex device and it contains
Many registers
Multiple arithmetic units, for both integer and floating point calculations
Ability to pipeline several consecutive instructions to speed execution etc.
However, to understand how processors work, we will start with a simplified processor model
Basic Computer
The Basic Computer has two components, a processor and memory
The memory has 4096 words in it
4096 = 212, so it takes 12 bits to select a word in memory
Each word is 16 bits long
CPU RAM
0
15 0
4095
Instructions
Program
A sequence of (machine) instructions
(Machine) Instruction
A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation)
Instructions of a program, along with any needed data are stored in memory
The CPU reads the next instruction from memory
It is placed in an Instruction Register (IR)
Control circuitry in control unit then translates the instruction into the sequence of microoperations
necessary to implement it
Instruction Format
Instruction Format 15
I
14
Opcode
12 11
Address
0
Addressing
Instruction Codes mode
A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation)
A computer instruction is often divided into two parts
An opcode (Operation Code) that specifies the operation for that instruction
Sometimes called as Macro-operation
An address that specifies the registers and/or locations in memory to use for that operation
In the Basic Computer, the memory contains 4096 (= 2 12) words, we needs 12 bit to specify
which memory address this instruction will use
In the Basic Computer, bit 15 of the instruction specifies the addressing mode
0: direct addressing
1: indirect addressing
Since the memory words, and hence the instructions, are 16 bits long, that leaves 3 bits for the
instruction’s opcode
Instruction Format …
Sometimes the address bit of instruction code represent various different information,
classified into different Instruction formats:
Immediate Instruction: when second part of instruction specifies operand
When second part of address specify address:
Direct Addressing: second part of instruction specifies address of an operand
Indirect Addressing: second part of instruction designates an address of a memory in
which the address of the operand is found
Addressing Mode
The address field of an instruction can represent either
Direct address: the address in memory of the data to use (the address of the operand)
Indirect address: the address in memory of the address in memory of the data to use (Effective
Address)
Direct addressing Indirect addressing
22 0 ADD 457 35 1 ADD 300
300 1350
457 Operand
1350 Operand
+ + Effective Address: Address of the
operand
Effective Address: Address of the
operand AC AC
Computer Register
A processor has many registers to hold instructions, addresses, data, etc
The processor has a register, the Program Counter (PC) that holds the memory address of
the next instruction to be executed
Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits
In a direct or indirect addressing, the processor needs to keep track of what locations in
memory it is addressing: The Address Register (AR) is used for this
The AR is a 12 bit register in the Basic Computer
When an operand is found, using either direct or indirect addressing, it is placed in the
Data Register (DR). The processor then uses this value as data for its operation
The Basic Computer has a single general purpose register – the Accumulator (AC)
Computer Register …
The significance of a general purpose register is that it can be referred to in instructions
e.g. load AC with the contents of a specific memory location; store the contents of AC into a
specified memory location
Often a processor will need a scratch register to store intermediate results or other
temporary data; in the Basic Computer this is the Temporary Register (TR)
The Basic Computer uses a very simple model of input/output (I/O) operations
Input devices are considered to send 8 bits of character data to the processor
The processor can send 8 bits of character data to output devices
The Input Register (INPR) holds an 8 bit character gotten from an input device
The Output Register (OUTR) holds an 8 bit character to be send to an output device
Registers in the Basic Computer
11 0
PC
Memory
11 0
4096 x 16
AR
15 0
IR CPU
15 0 15 0
TR DR
7 0 7 0 15 0
OUTR INPR AC
List of BC Registers
DR 16 Data Register Holds memory operand
AR 12 Address Register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction Register Holds instruction code
PC 12 Program Counter Holds address of instruction
TR 16 Temporary Register Holds temporary data
INPR 8 Input Register Holds input character
OUTR 8 Output Register Holds output character
Content
Instruction codes
Computer Registers
Common Bus System
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference Instructions
Input-output and Interrupt
Common Bus System
Basic computer: 8 register, a memory unit and a control unit
The registers in the Basic Computer are connected using a bus
This gives a savings in circuitry over complete connections between registers
Output of 7 register and memory connected to input of bus
Specific output that is selected for bus lines will be determined by selection variables S2, S1, S0
LD (Load) input is enabled receives the data from the Bus (Next clock pulse)
DR, AC, IR and TR – 16 bits each
AR and PC – 12 bits each (MSB as set to 0’s)
INPR and OUTR – 8 bit each (Only LSB’s)
S1 Bus
Common Bus System … Memory unit
S0
7
4096 x 16
Address
Write Read
AR 1
LD INR CLR
PC 2
LD INR CLR
DR 3
AC on the bus (S2, S1, S0 = 100), enabling LD
LD INR CLR
input of DR
E
Transferring the content of DR through adder and ALU AC 4
logic circuit into AC, enabling LD input of AC LD INR CLR
All during the same clock cycle
INPR
IR 5
LD
TR 6
LD INR CLR
OUTR
Clock
LD
Common Bus System …
Three control lines, S2, S1, and S0 control which register the bus selects as its input
S2 S1 S0 Register
0 0 0 x
0 0 1 AR
0 1 0 PC
0 1 1 DR
1 0 0 AC
1 0 1 IR
1 1 0 TR
1 1 1 Memory
Either one of the registers will have its load signal activated, or the memory will have its write signal
activated
Will determine where the data from the bus gets loaded
Memory places its 16 bit output on bus when read input is activated and S2, S1, S0 = 111
Common Bus System …
4 register DR, AC, IR, TR is 16 bit. The 12-bit registers, AR and PC, have 0’s loaded onto
the bus in the high order 4 bit positions
When the 8-bit register OUTR is loaded from the bus, the data comes from the low order 8
bits on the bus
INPR – connected to provide information to bus
– receives character from input device and transfer to AC
OUTR – can only receive information from bus
– receives a character from AC and delivers to Output device
Three types of input to AC:
from AC: complement AC, Shift AC
from DR: arithmetic and logic microoperation
from INPR
Bus lines connected to inputs of 6 registers and memory
If the memory size is 64K , then how many bits required to
represent its location
A. 10
B. 12
C. 14
D. 16
If the memory size is 64K , then how many bits required to
represent its location
A. 10
B. 12
C. 14
D. 16
In the instruction binary code if the 15th (MSB) is 1 then it
indicates
A. Immediate Addressing
B. Direct Addressing
C. Indirect Addressing
D. Effecting Addressing
In the instruction binary code if the 15th (MSB) is 1 then it
indicates
A. Immediate Addressing
B. Direct Addressing
C. Indirect Addressing
D. Effecting Addressing
In basic computer, PC is of how many bits register
A. 8
B. 12
C. 14
D. 16
In basic computer, PC is of how many bits register
A. 8
B. 12
C. 14
D. 16
Content
Instruction codes
Computer Registers
Common Bus System
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference Instructions
Input-output and Interrupt
Computer Instructions
Basic Computer Instruction Format
1. Memory – Reference Instructions (OP-code = 000 ~ 110)
15 14 12 11 0
I Opcode Address
2. Register – Reference Instructions (OP-code = 111, I = 0)
15 12 11 0
0 1 1 1 Register operation
3. Input – Output Instructions (OP-code =111, I = 1)
15 12 11 0
1 1 1 1 I/O operation
Computer Instructions …
Only 3 bits are used for operation code
It may seem computer is restricted to eight different operations
However register – reference and input – output instructions use remaining 12 bit as part of
operation code
Therefore, total number of instruction can exceed 8
In fact total no. of instructions chosen for basic computer is 25
Basic Computer Instructions
Symbol Hexadecimal Code (I = 0) Hexadecimal Code (I = 1) Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC is positive
SNA 7008 Skip next instruction if AC is negative
SZA 7004 Skip next instruction if AC is zero
SZE 7002 Skip next instruction if E is zero
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
Instruction Set Completeness
A computer should have a set of instructions so that the user can construct machine language programs to
evaluate any function that is known to be computable.
The set of instructions are said to be complete if computer includes a sufficient number of instruction in
each of the following categories:
Functional Instructions
Arithmetic, logic, and shift instructions
ADD, CMA, INC, CIR, CIL, AND, CMA, CLA
Transfer Instructions
Data transfers between the main memory and the processor registers
LDA, STA
Control Instructions
Program sequencing and control
BUN, BSA, ISZ
Input/output Instructions
Input and output
INP, OUT
Content
Instruction codes
Computer Registers
Common Bus System
Computer Instructions
Timing and Control
Instruction Cycle
Memory Reference Instructions
Input-output and Interrupt
Control Unit
Control Unit (CU) of a processor translates from machine instructions to the control signals
for the microoperations that implement them
Control units are implemented in one of two ways
Hardwired Control
CU is made up of sequential and combinational circuits to generate the control signals
Advantage: optimized to provide fast mode of operations
Disadvantage: requires changes in wiring if design has been modified
Microprogrammed Control
A control memory on the processor contains microprograms that activate the necessary control signals
We will consider a hardwired implementation of the control unit for the Basic Computer
Timing and Control
Instruction register (IR)
15 14 13 12 11 - 0
Other inputs
3x8
decoder
7 6543 210
D 0
I Combinational
D 7 Control Control
logic signals
T 15
T0
15 14 . . . . 2 1 0
4 x 16
decoder
4-bit Increment (INR)
sequence Clear (CLR)
counter
(SC) Clock
Timing Signals
Generated by 4-bit sequence counter and 4 x 16 decoder
The Sequence Counter (SC) can be incremented or cleared
Example: T0, T1, T2, T3, T4, T0, T1, . . .
Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.
T0 T1 T2 T3 T4 T0
Clock
T0
T1
T2
T3
T4
D3
CLR
SC
Example
Register Transfer statement
Specifies a transfer of content of PC into AR, if timing signal T0 is Active
At T0, T0 active and all other clock pulse will be inactive
PC is placed onto the bus (S2,S1,S0=010) and the LD (Load) input of AR is enabled
At the same positive clock transition increments the sequence counter (SC) from 0000 to
0001.
The next clock cycle has T1 active and T0 inactive
Instruction Cycle
In Basic Computer, a machine instruction is executed in the following cycle:
Fetch an instruction from memory
Decode the instruction
Read the effective address from memory if the instruction has an indirect address
Execute the instruction
After an instruction is executed, the cycle starts again at step 1, for the next instruction
This process continues indefinitely unless a HALT instruction is encountered
Note: Every different processor has its own (different) instruction cycle
Fetch and Decode
Initially PC loaded with address of first instruction and Sequence counter cleared to 0,
giving timing signal T0
After each clock pulse, SC is incremented by 1 (T0, T1, T2, and so on)
Fetch and Decode
At T0: T1
S2
Place the content of PC into bus by making S2,S1,S0=010 T0 S1 Bus
Transfer the content of bus to AR by enabling the LD input of AR S0
At T1: Memory
7
unit
Enable read input of memory Address
Read
Place content of bus by making S2,S1,S0=111
Transfer content of bus to IR by enabling the LD input of IR AR 1
Increment PC by enabling the INR input of PC
LD
PC 2
INR
IR 5
LD
Clock
Common bus
Determine the Type of Instructions
Start
SC <-- 0
AR <-- PC
T0
Execute a register-reference Instruction
T1 Execute a Input-output Instruction
IR <-- M[AR], PC <-- PC + 1
T2
Decode Opcode in IR(12-14),
AR <-- IR(0-11), I <-- IR(15)
(Register or I/O) = 1 = 0 (Memory-reference)
D7
(I/O) = 1 = 0 (register) (indirect) = 1 = 0 (direct)
I I
T3 T3 T3 T3
Execute Execute AR <-- M[AR] Nothing
input-output register-reference
instruction instruction
SC <-- 0 SC <-- 0 Execute T4
memory-reference
instruction
SC <-- 0
Register–Reference Instructions
Register Reference Instructions are identified when
D7 = 1, I = 0
Register Ref. Instr. is specified in B0 ~ B11 of IR
Execution starts with timing signal T3
– Register Reference Instruction
e.g.
