Chapter 1
The 80x86 Microprocessors
Evolution from 8080/8085 to 8086
In 1978, Intel Corp. introduced a 16-bit microprocessor called the 8086.
8086 was a major improvement over 8080/8085 in several ways:
1. The 8086's capacity of 1 megabyte of memory exceeded the
8080/8085's capability of handling a maximum of 64K bytes.
2. The 8080/8085 was an 8-bit system (work on only 8 bits of data at a
time). Data larger than 8 bits had to be broken into 8-bit pieces to be
processed by the CPU.
3. The 8086 was a pipelined processor, as opposed to the non
pipelined 8080/8085.
In a system with pipelining, the data and address buses are busy
transferring data while the CPU is processing information, thereby
increasing the effective processing power of the microprocessor.
2 Assembly Language
Evolution from 8086 to 8088
The 8086 is a microprocessor with a 16-bit data bus internally and
externally
All registers are 16 bits wide and there is a 16-bit data bus to transfer
data in and out of the CPU.
At that time all peripherals were designed around an 8-bit microprocessor
instead of 16-bit external data bus .
A printed circuit board with a 16-bit data bus was much more expensive.
Therefore, Intel came out with the 8088 version.
8088 is identical to the 8086 as far as programming is concerned, but
externally it has an 8-bit data bus instead of a 16-bit bus.
8088 has the same memory capacity, 1 megabyte.
In 1981, Intel's fortunes changed forever when IBM picked up the 8088
as their microprocessor of choice in designing the IBM PC.
3 Assembly Language
Other Microprocessors: 80286, 80386, 80486
Intel introduced the 80286 in 1982.
Its features included
16-bit internal and external data buses
24 address lines, which give 16 megabytes of memory (224 = 16
megabytes);
Virtual memory
The 80286 can operate in one of two modes: real mode or protected
mode.
Real mode is simply a faster 8088/8086 with the same maximum of
1 megabyte of memory.
Protected mode allows for 16M of memory but is also capable of
protecting the operating system and programs from accidental or
deliberate destruction by a user
Virtual memory is a way of fooling the microprocessor into thinking
that it has access to an almost unlimited amount of memory by
swapping data between disk storage and RAM.
4 Assembly Language
32-bit Microprocessor
In 1985 Intel introduced the 80386 (sometimes called 80386DX), internally
and externally a 32-bit microprocessor with a 32-bit address bus.
It is capable of handling physical memory of up to 4 gigabytes (232).
Virtual memory was increased to 64 terabytes (246).
Intel introduced numeric data processing chips, called math coprocessors,
such as the 8087, 80287, and 80387.
Later Intel introduced the 386SX, which is internally identical to the 80386
but has a 16-bit external data bus and a 24-bit address bus which gives a
capacity of 16 megabytes (224) of memory.
This makes the 386SX system much cheaper.
With the introduction of the 486 in 1989, Intel put a greatly enhanced
version of the 386 and the math coprocessor on a single chip plus
additional features such as cache memory.
Cache memory is static RAM with a very fast access time.
5 Assembly Language
Pentium
In 1992 Intel introduced the Pentium.
The Pentium had speeds of 60 and 66 MHz, but new design features
made its processing speed twice that of the 66-MHz 80486.
Although the Pentium has a 64-bit data bus, its registers are 32-bit and
it has a 32-bit address bus capable of addressing 4 gigabytes of
memory.
In 1995 Intel introduced the Pentium Pro, the sixth generation of the x86
family.
Pentium Pro is an enhanced version of the Pentium.
6 Assembly Language
Processor Architecture Impacting Factors
Markets
Processor
Architecture
Technology Applications
7 Assembly Language
Evolution of Intel’s Processors
Moore’s law: The number of transistors per integrated
circuit(IC) would double every 18 months
Pentium 4, 2001
55 Million Transistors
1.5 GHz
~ 30 years
4004, 1971
2300 Transistors
108 kHz
http://www.intel.com/research/silicon/mooreslaw.htm
8 Assembly Language
Evolution of Intel’s Processors
Processor Transistor Count Year Designer Process Area
Apple A12 (hexa-
core ARM64 6,900,000,000 2018 Apple 7 nm 83.27 mm2
"mobile SoC")
Xbox One X
(Project Scorpio) 7,000,000,000 2017 Microsoft/AMD 16 nm 360 mm²[42]
main SoC
IBM z13 Storage
7,100,000,000 2015 IBM 22 nm 678 mm²
Controller
72-core Xeon Phi 8,000,000,000 2016 Intel 14 nm 683 mm²
IBM z14 Storage
9,700,000,000 2017 IBM 14 nm 696 mm²
Controller
32-core SPARC
10,000,000,000 2015 Oracle 20 nm
M7
Apple A12X (octa-
core ARM64 10,000,000,000 2018 Apple 7 nm
"mobile SoC")
Centriq 2400 18,000,000,000 2017 Qualcomm 10 nm 398 mm2
32-core AMD Epyc 19,200,000,000 2017 AMD 14 nm 768 mm2
GC2 IPU 23,600,000,000 2018 Graphcore 16 nm 825 mm2
9 Assembly Language
By End of the Decade…
10,000
~2B Transistors 100,000
~30 GHz 30GHz
1.8B
1,000 10,000 14GHz
6.5GHz
100 Itanium® 3 GHz
Transistors
1,000
Itanium® proc
(MT)
10
Pentium® Pro
100 Pentium® Pro
1 486Pentium proc Pentium® proc
486
386 10
0.1 286 Frequency
8085 286 386
8085 8086
8086
(MHz) 1 8080
0.01 8080
8008 8008
4004
0.001 0.1 4004
’70 ’80 ’90 ’00 ’10
’70 ’80 ’90 ’00 ’10
“…30 gigahertz devices, 10 nanometer or less
delivering a tera instruction of performance by 2010”(1)
1) Pat Gelsinger, Intel CTO, Spring 2002 IDF
10 Assembly Language
Evolution of Intel’s Processors
Product 4004 8008 8080 8085 8086 8088 80286 80386 80486 Pentium P. Pro
Year 1971 1972 1974 1976 1978 1979 1982 1985 1989 1992 1995
MHz .108 .5-.8 2-3 3-8 5-10 5-8 6-16 16-33 25-50 60, 66 150
# Pins 18 18 40 40 40 40 68 132 168 273 387
# Tran K 2.9 3 4.5 6.5 29 29 130 275 1,200 3,100 5,500
Memory 4K 16K 64K 64K 1M 1M 16M 4G 4G 4G 64G
Data bus
Int. 4 8 8 8 16 16 16 32 32 32 32
Ext. 4 8 8 8 16 8 16 32 32 64 64
Add bus 4 8 16 16 20 20 24 32 32 32 36
Data type 4 8 8 8 8, 16 8, 16 8, 16 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
11 Assembly Language
Internal Block Diagram of the 8088/86 CPU
EXECUTION UNIT (EU) BUS INTERFACE UNIT (BIU)
address
generation and
bus control
12 Assembly Language
Multiplexed Bus
The multiplexing of n address lines and m data lines is a mechanism
where:
same lines / pins work as address line during first ( addressing ) phase of
communication between microprocessor and external chip
then the same lines / pins work as data lines during second ( data
exchange ) phase of communication between microprocessor and
external chip
This helps in reduction of number of pins both in:
Microprocessor and multiple external chips there by reducing:
package size of all the chips involved
size of board / product made from these chips
cost
13 Assembly Language
Pipelining
There are two ways to make the CPU process information faster:
1. Increase the working frequency or
2. Change the internal architecture of the CPU
The first option is technology dependent, meaning that the designer must
use whatever technology is available at the time, with consideration for
cost.
The technology determines the working frequency, power consumption,
and the number of transistors packed into a single-chip microprocessor.
The second option for improving the processing power of the CPU has to
do with the internal working of the CPU.
In the 8085 microprocessor, the CPU could either fetch or execute at a
given time.
Fetch Execute Fetch Execute
14 Assembly Language
Pipelining (Cont.)
The idea of pipelining in its simplest form is to allow the CPU to fetch and
execute at the same time.
Fetch Execute Fetch Execute Non pipelined
Fetch Execute
Fetch Execute
2-stage pipeline
Fetch Execute
15 Assembly Language
Pipelining in the 8088/86
Intel implemented the concept of pipelining in the 8088/86 by splitting the
internal structure of the microprocessor into two sections:
the execution unit (EU) and
the bus interface unit (BIU).
These two sections work simultaneously. The BIU accesses memory and
peripherals while the EU executes instructions previously fetched.
This works only if the BIU keeps ahead of the EU; thus the BIU of the
8088/86 has a buffer, or queue.
The buffer is 4 bytes long in the 8088 and 6 bytes in the 8086.
If any instruction takes too long to execute, the queue is filled to its
maximum capacity and the buses will sit idle.
The BIU fetches a new instruction whenever the queue has room for 2
bytes in the 6-byte 8086 queue, and for 1 byte in the 4-byte 8088 queue.
In some circumstances, the microprocessor must flush out the queue.
16 Assembly Language
8088/86 Registers
Registers: used to store information temporarily.
Information: data (8/16-bit) to be processed or the address of data.
Category Bits Register Names
AX (accumulator), BX (base addressing),
General 16
CX (counter), DX (point to data in I/O operations)
registers, 16-bit each
8 AH, AL, BH, BL, CH, CL, DH, DL
categories
Pointer 16 SP (stack pointer), BP (base pointer)
Index 16 SI (source index), DI (destination index)
Six
CS (code segment), DS (data segment),
Segment 16
SS (stack segment), ES (extra segment)
14
Instruction 16 IP (instruction pointer)
Flag 16 FR (flag register)
17 Assembly Language
8-bit/16-bit Registers
8-bit registers
16-bit registers
18 Assembly Language
