Scheme of Studies for BS (Computer Science) 2023
Digital Logic Design-Lab
Course Code: CSDL-223L
Semester Credit Hours Prerequisite
[BSCS-3] [0+1] [ EEAP-121L or
None]
Course Description
The basic purpose of this course is to introduce the concepts and tools for design of digital
electronic circuits using both combinational and sequential logic. Students will learn methods for
systematically designing digital circuits that satisfy their functional specifications and will be able
to develop application-specific logic designs in a structured, repeatable, convergent, and self-
documenting manner. This course provides a modern introduction to logic design and the basic
building blocks used in digital systems, in particular digital computers. It starts with a discussion
of combinational logic: logic gates, minimization techniques, arithmetic circuits, and modern logic
devices such as field programmable logic gates. The second part of the course deals with sequential
circuits: flip-flops, synthesis of sequential circuits.
Course Learning Outcomes (CLOs)
The course learning outcome along with domain and BT level are listed below
S. # CLO STATEMENT DOMAIN BT LEVEL PLO
CLO-1 Apply the fundamental concepts of C3
digital logic design to implement a C 3
combinational and sequential circuit. Application
CLO-2 P3
Practice circuits by using discrete
P Complete Overt 3
components and digital ICs.
Response
CLO-3 Contribute individually or as a team A2
A 9
member to work effectively. Responding
* BT= Bloom’s Taxonomy, C=Cognitive Domain, P=Psychomotor Domain, A= Affective Domain
Course Materials
This course introduces the following topics to students:
Binary Systems: Introduction to digital and analogue systems, Number Systems and
Conversions, Arithmetic with number systems, Radix/r’s Complement and Diminished
radix/(r-1)’s Complements, Subtraction using r’s Complements and (r-1)’s complement,
Signed and unsigned number systems and their arithmetic, Binary Codes, Decimal Codes
and Alphanumeric Codes
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Scheme of Studies for BS (Computer Science) 2023
Boolean Algebra and Logic Gates: Boolean Postulates and Theorems, Boolean Functions
and their Complements, Sum of Min Terms and Product of Max Terms, Standard forms
and Canonical Forms, Digital logic gates
Gate level Minimization: Karnaugh maps, Multi-variable (2,3,4) K-maps, Product of Sum
(POS) and Sum of Product (SOP) simplification, Don’t care conditions, Digital Circuits
using Basic and Universal Gates
Combinational Logic: Analysis and Design Procedure, Code Converters, Adders and its
types, Subtractors, Multiplier, Magnitude Comparator, Decoders and Encoders,
Multiplexers and De-multiplexer
Sequential Circuits: Latches (SR Latch,S’R’ Latch, D Latch), Flip Flops ( D Flip Flop, JK
Flip Flop,SR Flip Flop, T Flip Flop), Characteristic Tables, Characteristic Equations.,
Design and Analysis of Clocked Sequential Circuits (Timing diagram), Designing
Counters
Lab Weekly Schedule
The course schedule for 16 weeks is detailed below
Week Topic
1 Introduction to Lab Equipment and verification of basic logic gates
Introduction to digital trainer i.e. power supply, input-output ports, and different
modules. Study logic gates and verify their truth tables.
2 Introduction to Verilog and synapticad.
Introduction to Verilog design methodologies and conventions.
Identifiers, number specification, and keywords used in Verilog.
Module structure and stimulus block in Verilog.
3 Implementation of Demorgans Law, Distributive Law using gates and Verilog.
Applications of Demorgans law and Distributive law using basic gates.
The HDL-based design language of de-morgans law and distributive law using
Verilog.
4 Simplified Boolean expression to a minimum number of literals using Logic
gates and Verilog.
Simplify Boolean expression using properties.
The HDL-based design language for simplified expressions using Verilog.
5 Design and implementation of adders and subtractors using Logic gates and
Verilog.
Design and construct half adder, full adder, half subtractor and
full subtractor circuits and verify the truth table using logic gates.
The HDL-based design language for adders and subtractors using Verilog.
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Scheme of Studies for BS (Computer Science) 2023
Week Topic
6 Design and implementation of code converter using logic gates and Verilog.
Design and implement 4-bit Binary to gray code converter and Gray to binary
code converter. HDL based design language for gray code converters using
verilog.
7 Design and implementation of BCD to Excess-3 and Excess-3 to BCD converter
using logic gates and verilog.
Design and implement 4-bit BCD to Excess-3 and Excess-3 to BCD converter.
HDL based design language for Excess-3 converters using verilog.
8 Open Ended Lab
Design and implement the designated task using gates. HDL based design
language for designated task using Verilog.
9 Mid Term Exams
10 Design and implementation of magnitude comparator using logic gates and
using Verilog.
Design and implement 2 – Bit magnitude comparator using basic gates.
HDL based design language for 2-bit magnitude comparator using Verilog.
11 Design and implementation of multiplexer and de-multiplexer using logic gates
and Verilog.
Design and implement multiplexer and demultiplexer using logic gates and
study of IC 74150 and IC 74154.
HDL based design language for multiplexer and demultiplexer using Verilog.
12 Design and implementation of encoder and decoder using logic gates and
verilog.
Design and implement encoder and decoder using logic gates
and study of IC 7445 and IC 74147. HDL based design language for encoder
and decoder using Verilog.
13 Study of different types of flip flops using gates.
Verify basic flip flops i.e. D-flip flop and JK flip flop using IC.
14 Design and Implementation of shift register.
Verify serial to parallel shift register using IC.
15 Implementation of decade counter.
Verify mod 10/decade counter using IC.
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Scheme of Studies for BS (Computer Science) 2023
Week Topic
16 Lab Exam
Recommended Textbook
1. Mano, M. M. (2017). Digital Logic and Computer Design. Pearson India. ISBN:
9789332586048.
