Verilog HDL

A Brief Introduction
Spring 2025
 ● Introduction
● Hardware Description
Languages
Outline ● Different Levels of Abstraction
● Getting Started With Verilog
● Verilog Language Features
● Test benches and Simulation
Introduction Nowadays,
billions of
As digital and electronic circuit designs grew in size and transistors
complexity, capturing a large design at the gate level of per chip!
abstraction with schematic-based design became
● Too complex, Moore’s Law?
● Prone to error,
● Extremely time-consuming.
Complex digital circuit designs require a lot more
time for development, synthesis, simulation and
debugging.

Solution? Computer Aided Design (CAD) tools

● Based on Hardware Description Languages
Hardware Description Language (HDL)
HDLs are specialized computer languages used to program electronic and digital
logic circuits.

● High level languages with which we can specify our HW to analyze its design
before actual fabrication.

Two most popular HDLs: Other popular HDLs:

● Verilog ● SystemC
● VHDL ● SystemVerilog
● ...
Design Flow
Some other steps in
(Simplified)
design:
Design Idea
● Simulation to verify the
Behavioral Design
design (at different
Datapath Design

Logic Design
levels)
Physical Design
● Formal verification
Manufacturing

Chip / Board ● etc.

Different Levels of Abstraction
Behavioral vs. Structural Design
Loops
● Behavioral: the highest level of abstraction - Processes
specifying the functionality in terms of its
behavior (e.g. Boolean equations, truth tables, a collection of
registers RTL
algorithms, code, etc.). WHAT, not HOW. linked by Boolean
combinational
logic

Gate
● Structural: a netlist specification of components
and their interconnections (e.g. gates, Switch
transistors, even functional modules).

We will use both.

 Example: Full Adder
Different Levels of Abstraction A
B FA Sum

Cin Cout
● Behavioral modeling:

● Structural modeling:
 Example: Full Adder
Different Levels of Abstraction x
y FA
Sum

in Verilog HDL Cin Cout

module full_adder(x,y,cin,sum,cout);
● Gate-Level modeling: input x,y,cin;
output sum, cout;
wire s1,c1,c2,c3;
○ Verilog HDL supports built-in primitive gates modeling. xor(s1,x,y);
xor(sum,cin,s1);
and(c1,x,y);
and(c2,y,cin);
and(c3,x,cin);
or(cout,c1,c2,c3);

Dataflow modeling:
endmodule
●
○ Mainly used to describe combinational circuits. The basic module full_adder(x,y,cin,sum,cout);
input x,y,cin;
mechanism used is the continuous assignment. output sum, cout;

assign {cout, sum} = x + y + cin;

endmodule

● Behavioral modeling:
○ Used to describe complex circuits (primarily sequential). module full_adder(x,y,cin,sum,cout);
input x,y,cin;
output reg sum, cout;
Mechanisms: initial and always statements.
always @ (x or y or cin) begin
{cout, sum} = a + b + cin;
end
endmodule
 module …
Module 1 Module 4

Module 2 Module 4
endmodule

Getting Started Module 2

With Verilog ● Modules can
have interfaces
Module 3
Describing a digital system as a to other
set of modules
Module 4
modules
(instantiation =
Module 4
creating a copy).
● Modules are
connected using
nets.
What can we do?

● Simulation to verify the system (test benches)

● Synthesis to map to hardware (low-level primitives, ASIC, FPGA)
Development Process
Verilog Verilog
Testbench
Module(s) Module(s)

SIMULATION SYNTHESIS

Open source or commercial

software available

FPGA ASIC
Evaluate Result Specific software (e.g., Commercial CAD
Xilinx ISE or Vivado) tools
Verilog Language Features
Operators
Verilog Language Features
Operators
Verilog Language Features
Operators
Verilog Language Features
Operators: Logical vs. Bitwise

1'b1 && 1'b1 = 1 1'b1 & 1'b1 = 1

1'b1 && 1'b0 = 0 1'b1 & 1'b0 = 0
! 1'b1 = 0 ~ 1'b1 = 0
! 3'b000 = 1 ~ 3'b000 = 111
3'b111 && 3'b111 = 1 3'b111 & 3'b111 = 111
3'b100 && 3'b111 = 0 3'b000 & 3'b111 = 000
Verilog Language Features
Operators
Verilog Language Features
Operators

Reduction, conditional,
concatenation, and replication
operators also available.
Verilog Language Features Data Values

Verilog supports 4 value levels:

Value Level Represents ● All unconnected nets are set to ‘z’.

● All register variables are set to ‘x’.
0 Logic 0 state

1 Logic 1 state

x Unknown logic state

z High impedance state

Verilog Language Features
Module 1 Module 4
Module - the basic unit of hardware in Verilog
Module 2 Module 4

● Cannot contain definitions of other modules,

● Can be instantiated within another module - hierarchy of modules.

module module_name (list_of_ports);

input/output declarations
Local net declarations Temporary connections (wires)

Parallel statements
endmodule
Verilog Language Features
Module example: A simple AND function

Assign statement:
assign var = expression;
● used typically for combinational circuits
● continuous assignment, delay optional
● LHS must be “net” type var (usually “wire”)
● RHS can be both “register” or “net” type
Verilog Language Features
Module example 2: A 2-level combinational circuit
Verilog Language Features Data Types

A variable can be:

A. Net wire, wor, wand, tri, supply0, supply1, etc.

○ Must be continuously driven,
○ Cannot be used to store a value,
○ Models connections between continuous assignments and instantiations,
○ 1-bit values by default, unless declared as vectors explicitly.
○ Default value of a net is “Z” - high impedance state.

B. Register reg, integer, real, time

○ Retains the last value assigned to it,
○ Usually used to represent storage elements (sometimes in combinational circuits),
○ May or may not map to a HW register during synthesis.
○ Default value of a reg data type is “X”.
Verilog Language Features Data Types

net example:

A.
Verilog Language Features Data Types

net example:

A.

Wrong design!
Verilog Language Features Data Types

net example - correct design:

A.
Verilog Language Features Data Types

net example 2:

A.
Verilog Language Features Data Types

reg example:

● Declaration explicitly specifies the size (default is 1-bit):

○ reg x, y; // 1-bit register variables
○ reg [7:0] bus; // An 8-bit bus

● Treated as an unsigned number in arithmetic expressions.

● MUST be used when modeling actual sequential HW, e.g. counters, shift registers, etc.

● Two types of assignments possible:

○ A = B + C;
○ A <= B + C;
 Come back to these
reg example slides
Verilog Language Features Data Types after you learn about
sequential circuits!

reg example - 32-bit counter with synchronous reset:

Any variable assigned

within the always block
must be of type reg.
Verilog Language Features Data Types

reg example - solution: 32-bit counter with asynchronous reset:

Verilog Language Features Data Types

Integer example:

● General purpose register data type,

● 2’s complement signed integer in arithmetic expressions,
● Default size is 32 bits.
○ wire [15:0] X, Y;
○ integer C;
○ C = X + Y;

Other register
data types:
real, time.
Verilog Language Features
Vectors

● Both Net or reg type variables can be declared as

vectors: multiple bit widths
● Specifying width with: [MSB:LSB]
Verilog Language Features
Vectors

● Parts of a vector can be addressed and used in an expression:

Multi-dimensional
arrays and
memories also
possible.
Verilog Language Features
Constant Values

● Sized or unsized form,

● Syntax:
○ <size>’<base><number>
● Examples:
Verilog Language Features
Parameters

● Constants with a given name,

● Size deduced from the constant value itself:
Verilog Language Features
Predefined Logic Gates

● Can be instantiated within a module to create a structural (gate-level) design.

 There are also
other gates with
Verilog Language Features tristate control

List of Some Primitive Gates ● Output ports must be

connected to a net
● ● Input ports may be either
net or reg type vars
Verilog Language Features
Two Ways to Specify Connectivity During Module Instantiation

`include "module2.v"

Module 1
Module 2
Module 2

Connectivity of the signal lines between two modules can be specified in 2 ways:

● Positional Association (Implicit)

○ Parameters listed in the same order as in the original module description.
● Explicit Association
○ Parameters explicitly listed in arbitrary order.
Verilog Language Features
● Positional Association Example - Full Adder Using Half Adder Module

A
Full Adder
A S
Half Adder S
B B
Carry Half Adder
Cin Cout

Half Adder
 Verilog Language Features
● Positional Association Example - Full Adder Using Half Adder Module

A S
B Half Adder
Carry

G1

G2
 Verilog Language Features
● Positional Association Example - Full Adder Using Half Adder Module

A S
B Half Adder
Carry

G1

G2
 Note the
Verilog Language Features port order

● Positional Association Example - Full Adder Using Half Adder Module

w2

w1 w3

How do we use the half_adder

module to implement a full adder?
 Note the
Verilog Language Features port order

● Positional Association Example - Full Adder Using Half Adder Module

w2

w1 w3
 Verilog Language Features
● Explicit Association Example - Full Adder Using Half Adder Module

w2

w1 w3

Ports are explicitly

specified - order is
not important

Less chance for errors

Verilog Language Features
Combinational vs. Sequential Circuits

Combinational: The output only

depends on the present input.

Sequential: The output depends

on both the present input and
the previous output(s) (the state
of the circuit).
Verilog Language Features
Combinational vs. Sequential Circuits

Sequential logic: Blocks that have memory elements: Flip-Flops, Latches,

Finite State Machines.
● Triggered by a ‘clock’ event.
○ Latches are sensitive to level of the signal.
○ Flip-flops are sensitive to the transitioning of clock

Combinational constructs are not sufficient. We need new constructs:

● always
● initial
Verilog Language Features
Sequential Circuits

Whenever the event in the sensitivity list

occurs, the statement is executed.
Verilog Language Features
Sequential Circuits

● Sequential statements are within an ‘always’ block,

● The sequential block is triggered with a change in the sensitivity list,
● Signals assigned within an always block must be declared as reg,
○ The values are preserved (memorized) when no change in the sensitivity list.

● We do not use ‘assign’ within the always block.

Difference

between

Synchronous

and

Asynchronous
Sequential

Circuits
Verilog Language Features Sequential Circuits

32-bit counter with synchronous reset:

Any variable assigned

within the always block
must be of type reg.
Verilog Language Features Sequential Circuits

Solution: 32-bit counter with asynchronous reset:

Verilog Language Features
Sequential Circuits
How to Simulate Verilog Module(s)
Testbench: provides stimulus to Unit-Under-Test (UUT) to verify its functionality,
captures and analyzes the outputs.

Requirements: Our Verilog module

Inputs and outputs need to be connected to the test bench

TESTBENCH

Unit Under Test

Stimulus Monitor
(UUT)
How to Simulate Verilog Module(s) Example

We can choose
either behavioral
or structural
design.
How to Simulate Verilog Module(s) Example

Let’s choose structural gate-level design:

Which gates do we need, and what will

the connections be?
How to Simulate Verilog Module(s) Example

Let’s choose structural gate-level design:

How to Simulate Verilog Module(s) Example

Let’s choose structural gate-level design:

How to Simulate Verilog Module(s) Example

Let’s choose structural gate-level design:

How to Simulate Verilog Module(s) Example

Let’s choose structural gate-level design:

 Saved as
function_Y_testbench.v
How to Simulate Verilog Module(s) Example
TESTBENCH

Saved as
function_Y.v

Unit Under Test

 Saved as
function_Y_testbench.v
How to Simulate Verilog Module(s) Example
TESTBENCH

Saved as
function_Y.v

Unit Under Test

 Saved as
function_Y_testbench.v
How to Simulate Verilog Module(s) Example
TESTBENCH

Saved as
function_Y.v

Unit Under Test

initial block - gets
executed once Saved as
function_Y_testbench.v
How to Simulate Verilog Module(s) Example
TESTBENCH
`include “function_Y.v”

Saved as
function_Y.v

Unit Under Test

 Saved as
function_Y_testbench.v
How to Simulate Verilog Module(s) Example
TESTBENCH
`include “function_Y.v”

Saved as
function_Y.v

Unit Under Test

How to Simulate Verilog Module(s) Example

Results can be viewed as waveforms:

 How to Simulate Verilog Module(s) Example

We can also monitor the changes and print them to the console using $monitor:

We can also use

$dumpfile to
dump variable
changes to a file.
Short Practice Example 1
Implement a the circuit given below using structural gate-level design approach.
Short Practice Example 1
Implement a the circuit given below using structural gate-level design approach.
Short Practice Example 1
Implement a the circuit given below using structural gate-level design approach.
Short Practice Example 1
Implement a the circuit given below using structural gate-level design approach.
Short Practice Example 1
Implement a the circuit given below using structural gate-level design approach.
Short Practice Example 1
Implement a the circuit given below using structural gate-level design approach.
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Is the delay in ms, ns…?

Short Practice Example 1

Implement a testbench for the Simple_Circuit.
You should specify
the timescale
Short Practice Example 1
Implement a testbench for the Simple_Circuit.
Short Practice Example 2
Implement the circuit specified by the given Boolean equations using
dataflow design approach.
Short Practice Example 2
Implement the circuit specified by the given Boolean equations using
dataflow design approach.
Short Practice Example 2
Implement the circuit specified by the given Boolean equations using
dataflow design approach.
Short Practice Example 2
Implement the circuit specified by the given Boolean equations using
dataflow design approach.
Short Practice Example 2
Implement the circuit specified by the given Boolean equations using
dataflow design approach.
Questions?
Lab Example
Implement a 4-Bit Ripple Carry Adder in Verilog in the following steps:

1. Implement a 1-Bit Full Adder using behavioral

dataflow design approach. Fill in the truth
table, find the corresponding functions for
Sum and Carry_out, write a Verilog module,
test it by writing a testbench for all possible
cases.

2. Implement a 4-Bit Ripple Carry Adder by

instantiating your 1-Bit Full Adder module as
many times as necessary. Use structural
design approach and explicit association.
Test it by writing an appropriate testbench.
Lab Example Solution:

Full_Adder.v module

sum = (A^B)^C
Cout = AB+BC+AC
Full_Adder_Testbench.v module

Simulation results:
Four_Bit_RCA.v module
A4 A3 A2 A1
Four_Bit_RCA_Testbench.v module

Only some test cases.

Why not all?

How can we automate

the process?
Lab Example 2 - Sequential Circuits
Lab Example 2 - Sequential Circuits
Lab Example 2 - Sequential Circuits
A flip flop is a basic building block of sequential logic circuits. It is a circuit that has two
stable states and can store one bit of state information. The output changes state by
signals applied to one or more control inputs.

A basic D Flip Flop has a D (data) input, a clock (CLK) input and outputs Q and Q’ (the
inverse of Q). Optionally it may also include the PR (Preset) and CLR (Clear) control inputs.
Lab Example 2 - Sequential Circuits
Verilog codes for different implementations of D flip-flop:
Lab Example 2 - Sequential Circuits
Verilog codes for different implementations of D flip-flop:
 Lab Example 2 - Sequential Circuits

Here we state the steps of designing a sequential circuit with an

example circuit specification:

111 Sequence Detector:

Design a circuit that outputs 1 when a sequence three consecutive 1’s is
applied to input, and 0 otherwise.

Y
Lab Example 2 - Sequential Circuits
Lab Example 2 - Sequential Circuits
Lab Example 2 - Sequential Circuits
Lab Example 2 - Sequential Circuits

From the state table above

we obtain the following
input equations:
Lab Example 2 - Sequential Circuits
Lab Example 2 - Sequential Circuits
Let’s choose rising-edge
D flip-flop
Lab Example 2 - Sequential Circuits

Alternative structural design using D Flip-flops without reset:

Let’s look at the
code in parts...
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Instantiating D flip flops:
Handle reset and update present_state on change of next_state:

Combinational circuit to implement the output:

N
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letirpe
Nlneota.rle2
wsa
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Behavioral design
U
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names to your states
Lab Example 2 - Sequential Circuits
How would we design a testbench for a sequence detector?

The idea is to have an input bit stream (e.g. a 20-bit binary sequence),

and send one input bit at a time at each clock cycle (e.g. using shifting).
Entire sample testbench code: