Introductory Lecture-
Verilog basics
Lab evaluation criteria
¨ Pre-lab task
¤ 2 marks
¨ Lab task
¤ Simulation4 marks
¤ Lab report 1 mark
n Should be submitted in the next week lab.
¨ Viva (individual)
¤ 3 marks
¤ Actual attendance
Verilog - HDL
¨ Hardware Description Language
¨ C like in syntax but has distinct character and
interpretation
¤ must set perception right before coding in Verilog
¤ must visualize hardware in mind while structuring
Verilog
¨ Modules consisting of procedural blocks and
assignments
Modules – the building block
¨ Module is the basic building block in Verilog
¤ For example : module of full adder
¨ Modules are
¤ Declared
¤ Instantiated
¨ Modules declarations cannot be nested
¨ Modules instantiation can be nested
Modeling Structure: Modules
¨ Modules are interconnected to describe the structure of
digital system
¨ Modules have ports for interconnection with other modules
¤ Ports can be input, output or inout
¨ Modules start with keyword module and end with keyword
endmodule
¨
Hierarchical Design
¨ Verilog code contains a top‐level module and zero or more
instantiated modules
¨ The top‐level module is not instantiated anywhere
¨ Several copies of a lower‐level module may exist
¨ Each copy stores its own values of regs/wires
¨ Ports are used for interconnections to instantiated modules
¨ Order of ports on first line of module definition determine
order for connections of instantiated module
¨ Order of listing inputs, outputs, and inouts on the following
lines is not important
Module Example
Module Ports
¨ port-direction [port-size] port-name, port-name, ... ; where
¤ port-direction – input, output, inout
¤ port-size is a range from [ msb : lsb ]
Logic Values
¨ 0: zero, logic low, false, ground
¨ 1: one, logic high, power
¨ x: unknown
¨ z: high impedance, unconnected, tri‐state
Constants
¨ decimal (default)
¤ 13, ‘d13
¨ binary
¤ 4’b1101
¨ octal
¤ 4’o15
¨ hexadecimal
¤ 4’hd
Data Types
¨ Nets
¤ physicalconnections between components
¤ always show the logic value of the driving components
¤ Many types of nets, we use wire in RTL
¨ Registers
¤ Implicitstorage – unless variable of this type is
modified it retains previously assigned value
¤ Does not necessarily imply a hardware register
¤ Register type is denoted by reg
Variable Declaration
¨ Declaring a net
¤ wire [range] net_name;
¤ Range is specified as [MSb:LSb]
n Default is one bit wide
¨ Declaring a register
¤ reg[range] reg_name;
¨ Declaring memory
¤ reg[range] memory_name [start_addr : end_addr];
¨ Examples
¤ reg r; // 1-bit reg variable
¤ wire w1, w2; // 2 1-bit wire variable
¤ reg[7:0]vreg; // 8-bit register
¤ reg[7:0] memory [0:1023]; //a 1 KB memory
Levels of Abstraction
¨ Gate level
¨ Dataflow level
¨ Behavioral or algorithmic level
Gate level (structural) modeling
¨ Describe the circuit using logic
¨ build from gate primitives
¤ Verilog has built‐in gate‐level primitives
n NAND, NOR, AND, OR, XOR, NOT
¨ Typical gate instantiation is
¤ and instance‐name (out, in1, in2, in3, …)
Example
Data Flow Modeling
¨ Expressions, operands and operators form the basis
of dataflow modeling
¨ assign statement
¤ Continuousassignment
¤ Used to model combinational logic
assign net_name = expression;
example:
assign out = in1 & in2;
assign sum = a + b;
Verilog Operators
¨ Arithmetic: +, = , *, /, %
¨ Binary bitwise: ~, &, |, ^, ~^
¨ Unary reduction: &, ~&, |, ~|, ^, ~^
¨ Logical: !, ~, &&, ||, ==, ===, !=, !==
¨ == returns x if any of the input bits is x or z
¨ === compares xs and zs
¨ Relational: <. >, <=, >=
¨ Logical shift: >>, <<
¨ Conditional: ?:
¨ Concatenation: {}
¨ Replication: {{}}
Example: Concatenation operator
Behavioral Modeling
¨ High level language constructs are used
¤ for loop
¤ if else
¤ while
¨ All statements come in a procedural block
¤ Two types of procedural blocks
n always
n initial
¨ A subset of constructs are synthesizable
Initial and Always
¨ Initial blocks execute once
¤ at t=0
¨ Always blocks execute
continuously
¤ att = 0 and repeatedly
thereafter at triggering
Sensitivity list
¨ Signals
¤ Posedge – rising-edge triggered
¤ Negedge – falling-edge triggered
¤ example:
always @ (posedge clk or negedge rst_n)
begin
…
end
Procedural Assignments
¨ Two types of assignments
¤ Blocking assignment =
n Sequential assignment
¤ Non-Blocking assignment <=
n Concurrent assignment
Blocking assignment
¨ Regular assignment inside procedural block
¨ Assignment takes place immediately
¨ LHS must be reg
Nonblocking assignment <=
¨ Compute RHS
¨ Assignment takes place at end of block
¨ LHS must be a register
Simulation
¨ Once you have made module of your design, you have
to check and debug it before mapping to the fpga
¤ Simulation file (test bench): code file that gives inputs to a
module and takes outputs
¤ Verilog provides in-built Simulator
¤ Timing control
Ports conventions
¨ Must be followed while writing module and test-
bench
Timing control
¨ #<number> statement
¨ statement is not executed until <number> time units
have passed
¨ control is released so that other processes can
execute
¨ used in test-bench and to model propagation delay
in combinational logic
¨ #5 a=2’b01;
¨ xor #2 x2(c, a, b);
System tasks
Reg concept?
Synthesis
¨ Process of going from one abstraction level to
another in design hierarchy
¨ RTL code à fpga netlist
¨ Modelsim file (.v) à xilinx net list
Code
Snapshots
