Microprocessors & Microcontrollers

L8: Memories
 Memory Organization
 Memory stores information such as instructions and data
in binary format (0 and 1). It provides this information to
the microprocessor whenever it is needed.
Memory hierarchy in a computer system
 Main Memory: memory unit that communicates
directly with the CPU (RAM)
 Auxiliary Memory: device that provide backup storage
(Disk Drives)
 Cache Memory: special very-high-speed memory to
increase the processing speed (Cache RAM)
Memory Organization Cont.
 Semiconductor Memories
 Semiconductor memories are made from silicon, unlike
hard-disk drive memory which are magnetics and optics
Main Difference between Memory Technologies:

RAM:
 Data can be read and written but data stored is volatile, i.e. need
power to retain data
ROM:
 Data in ROMs are typically pre-configured. Data can only be
read, and the data stored is not volatile, i.e. don’t need power to
retain data
Flash:
 Data can be read and written, and data stored is not volatile, i.e.
don’t need power to retain data
ROM
 ROM is used to store data that never (or rarely) changed
 Data in ROMs are retained even when power is not
supplied – main advantage of ROM
 Data in ROMs are typically pre-configured using
specialized equipment
 ROM is used as Bootstrap Loader; A program whose
function is to start the computer software operating when
power is turned on
 RAM
 RAM is a temporary data storage
 RAM does not retain its stored data when no power is applied
 When a data unit is written into a given address in the RAM,
the data unit previously stored at that address is replaced by
the new unit
 When a data unit is read at a given address, the data unit that
is read remains there
 There are two types of RAM
 Static RAM (SRAM) The difference is how each
 Dynamic RAM (DRAM) cell is designed
 SRAM vs DRAM
 SRAM uses a latch to store 1 bit in cell while DRAM uses a
capacitor to store 1 bit in a cell
 Therefore, SRAM is more expensive to implement, i.e.
requires more logic gates per cell compared to DRAM
 Because SRAM uses a latch, it works faster than DRAM that
requires the capacitor to be periodically refreshed
 SRAM is typically implemented in high speed CPU cache
memory, while DRAM is implemented in main memory
 Flash Memory
 Flash memory is the closest to the ideal memory:
 capable of high storage capacity
 retains data when power off
 ability to erase and reprogram at will
 fast operation
 Cheap
 Flash memory cell is designed using floating gate MOS
transistor
Computer Memories & Semiconductor
Memories

Source: http://www.vlsifacts.com/classification-of-semiconductor-memories-and-computer-memories/
 Size & Dimension of Memory
 Size of semiconductor memories is represented in bits
 For example, an 8x4 ROM is capable of storing
32 bits

 Dimension of memory is usually measured by two numbers:

its length and its width (Length x Width).
 The length is the total number of locations.
 The width is the number of bits in each location.
 The length (total number of locations) is a function of the
number of address lines.
# of memory locations = 2( # of address lines)
 Size & Dimension of Memory Cont.
 So, a memory chip with 10 address lines would have
210 = 1024 locations (1K)
 Looking at it from the other side, a memory chip with 4K
locations would need
Log24096=12 address lines
 8x4 ROM has 3 address lines (23 = 8) and 4 data lines

For a 32x8 RAM, how many address line and data lines?
Address Line = 5, data line = 8
 The 8085 and Memory
 The 8085 has 16 address lines. That means it can address
216 = 64K memory locations
 Then it will need 1 memory chip with 64 K locations, or 2 chips with
32 K in each, or 4 with 16 K each or 16 of the 4 K chips, etc.

 How would we use these address lines to control the multiple

chips?
 Chip Select
 Usually, each memory chip has a CS (Chip Select) input. The
chip will only work if an active signal is applied on that input.

RD WR

A0
A1
CS

 To allow the use of multiple chips in the make up of memory,

we need to use a number of the address lines for the purpose
of “chip selection”.
 These address lines are decoded to generate the 2n necessary
CS inputs for the memory chips to be used.
 Chip Selection Example
 Assume that we need to build a memory system made up of 4
of the 4 X 4 memory chips
 We will need to use 2 inputs and a decoder to identify which
chip will be used at what time.
 The resulting design would now look like the one on the
following slide.
 Chip Selection Example
RD
WR D0
D1
D2
D3

RD WR RD WR RD WR RD WR

A0 A0 A0 A0
A1 A1 A1 A1
CS CS CS CS

A0
A1

A2 2x4
A3 Decoder
 Memory Map and Addresses
 The memory map is a picture representation of the address
range and shows where the different memory chips are
located within the address range.

 The address range of a particular chip is the list of all addresses

that are mapped to the chip.
 The 8085 and Address Ranges
 The 8085 has 16 address lines. So, it can address a total of 64K
memory locations.
 If we use memory chips with 1K locations each, then we will
need 64 such chips.
 The 1K memory chip needs 10 address lines to uniquely
identify the1K locations. (log21024=10)
 That leaves 6 address lines which is the exact number needed
for selecting between the 64 different chips(log264=6).
 The 8085 and Address Ranges Cont.
 Now, we can break up the 16-bit address of the 8085 into two
pieces:
Chip Select Location Selection within the Chip
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

 Depending on the combination on the address lines A15 - A10,

the address range of the specified chip is determined.
 Chip Select Example
 A chip that uses the combination A15 - A10 = 001000 would
have addresses that range from 2000H to 23FFH.
 Keep in mind that the 10 address lines on the chip gives a range of 00
0000 0000 to 11 1111 1111 or 000H to 3FFH for each of the chips.
 The memory chip in this example would require the following circuit
on its chip select input:
 Chip Select Example Cont.
 If we change the above combination to the following:

 Now the chip would have addresses ranging from: 2400 to 27FF.
 Changing the combination of the address bits connected to the chip
select changes the address range for the memory chip.
 Chip Select Example Cont.
 To illustrate this with a picture:
 In the first case, the memory chip occupies the piece of the memory
map identified as before.
 In the second case, it occupies the piece identified as after.
 High-Order vs. Low-Order Address Lines
 The address lines of a microprocessor can be classified into two
types:
 High-Order
 Used for memory chip selection
 Low-Order
 Used for location selection within a memory chip.

 This classification is highly dependent on the memory system

design.
 Data Lines
 All of the above discussion has been regarding memory length.
Lets look at memory width.
 We said that the width is the number of bits in each memory
word.
 We have been assuming so far that our memory chips have the right
width.
 What if they don’t?
 It is very common to find memory chips that have only 4 bits per location. How
would you design a byte wide memory system using these chips?
 We use two chips for the same address range. One chip will supply 4 of the lower
data bits per address and the other chip supply the other 4 higher data bits for the
same address.
Data Lines Cont.
 Memory Expansion
 Memory can be expanded on its capacity or data width
 Capacity expansion example: 16x4 memory expands to 32x4
memory
 Data width expansion example: 16x4 memory expands to 16x8
memory
 Memory Expansion (cont.)
 Capacity expansion – Use two 16x4 RAM to produce a 32x4
RAM
 Memory Expansion (cont.)
 Data width expansion – Use two 16x4 RAM to produce a
16x8 RAM
 How to read from and write to a RAM?
 Provide the address we want to read or write. Provide the
data along with the address if you want to write.
 We also need a few enable signals to control when we want to
enable the memory, read, and write operation
 The Chip Select signal (CS) is used to enable the memory
 The Write Enable signal (WE) is used to enable the write operation
 The Output Enable signal (OE) is used to enable the read operation
 Read operation example
Read one byte at location A[1:0] = 10 from a 4x8 RAM
 Step 1: Supply address A[1:0] =
10 to Read location 10
 Step 2: Set CS = 0 to enable the
memory
 Step 3: Set OE = 0 to enable read
 Step 4: Set WE = 1 to disable
write
 Step 5: Get the data at location 10
 Write operation example
Write one byte at location A[1:0] = 10 from a 4x8 RAM
 Step 1: Supply address A[1:0] = 10
to write location 10
 Step 2: Supply the Data[7:0] to write
Example: 1010 0111

 Step 3: Set CS = 0 to enable the

memory
 Step 4: Set OE = 1 to disable read
 Step 5: Set WE = 0 to enable write
 Step 6: data[7:0] is written at
location 10