CSE 520210
Microprocessor and
Assembly Language
Main Memory
Array Design
Basic Concepts
• A memory device can be viewed as a
single column table. Memory Address Memory
– Table index (row number) refers to Binary Hex Contents
the address of the memory. 00-0000-0000 000 10011001
– Table entries refer to the memory 00-0000-0001 001 00111000
contents or data.
00-0000-0010 002 11001001
– Each table entry is referred as a
memory location or as a word. 00-0000-0011 003 00111011
• Both the memory address and the
memory contents are binary numbers,
expressed in most cases in Hex format.
• The size of a memory device is 11-1111-1100 3FC 01101000
specified as the number of memory 11-1111-1101 3FD 10111001
locations X width or word size (in bits). 11-1111-1110 3FE 00110100
– For example a 1K X 8 memory 11-1111-1111 3FF 00011000
device has 1024 memory locations,
with a width of 8 bits.
1024 X 8 (or 1KX8) Memory
Address Lines
• A memory device or memory chip must have
three types of lines or connections: Address,
Data, and Control.
• Address Lines: The input lines that select a
Y00 Location 000
memory location within the memory device. Y01 Location 001
– Decoders are used, inside the memory chip, to Y02 Location 002
select a specific location A00 Y03 Location 003
– The number of address pins on a memory chip A01
specifies the number of memory locations.
• If a memory chip has 13 address pins An-2
(A0..A12), then it has: An-1 YFC Location 0FC
213 = 23 X 210 = 8K locations. YFD Location 0FD
YFE Location 0FE
• If a memory chip has 4K locations, then it
YFF Location 0FF
should have N pins:
2N = 4K = 22 X 210 = 212 N=12 address
pins (A0..A11)
Data Lines
• Data Connections: All memory devices have a set of data output pins (for ROM
devices), or input/output pins (for RAM devices).
– Most RAM chips have common bi-directional I/O connections.
– Most memory devices have 1, 8 or 16 data lines.
Data Input Lines
(DI0..DIn-1)
k- address lines k- address lines
(A0..Am-1) 2m words (A0..Am-1) 2m words
k- address lines
(A0..Am-1) 2m words
Read/Write (R/W) n-bits per Output Enable (OE) n-bits per
Read (RD) n-bits per word word
Chip Select (CS) Chip Select (CS)
Write (WR) word
Chip Select (CS)
Data Output Lines
Data Input/Output (D0..Dn-1)
Data Output Lines Lines (D0..Dn-1)
(DO0..DOn-1) (2m X n) ROM with only O/P Data
(2m X n) RAM with common I/P
(2m X n) RAM with separate I/P lines
and O/P Data lines
and O/P Data lines
Control Lines
• Enable Connections:
– All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device.
• If a device is not selected or enabled then no data can be read from, or
written into it.
• The CS or CE input is usually controlled by the microprocessor through the
higher address lines via an address decoding circuit.
• Control Connections:
– RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals.
• Some RAM chips have a common Read/ Write (R/W) signal.
– ROM chips can perform only memory read operations, thus there is no need
for a Write (WR) signal.
• In most real ROM devices the Read signal is called the Output Enable
(OE) signal.
RAM Cells
Static RAM (SRAM): Dynamic RAM (DRAM):
• The basic element of a static RAM cell is the • DRAM stores data in the form of electric
D-Latch. charges in capacitors.
• Data remains stored in the cell until it is • Charges leak out, thus need to refresh
intentionally modified. data every few ms.
• SRAM is fast (Access time: 1ns). • DRAM is slow (Access time: 60ns).
• SRAM needs more space on the • DRAM needs less space on the
semiconductor chip than DRAM. semiconductor chip than SRAM.
– SRAM more expensive than DRAM – DRAM less expensive than SRAM
– SRAM needs more space than DRAM – DRAM needs less space than SRAM
• SRAM consumes power only when accessed. • DRAM needs to be refreshed
• SRAM is used as a Cache • DRAM is used as the main memory
Bit Select
Bit Select
Data In D Q Data Out
Data In Data Out
Write En
RAM Cell DRAM Cell
Memory Read Operations
• A memory read operation is carried out in the following steps:
– The processor loads on the Address bus the address of the memory location to be read (Step 1).
• Some of the address lines select the memory devices that owns the memory location
to be read (Step 1a), while the rest point to the required memory location within the
memory device.
– The processor activates the Read (RD) signal (Step 2).
• The selected memory device loads on the data bus the content of the memory
location specified by the address bus (Step 3).
– The processor reads the data from the data bus, and resets the RD signal (Step 4).
Clock T1 T2 T3
Address Bus Valid Address
Chip Enable
Read (RD)
Data Bus Invalid Data Valid Data
Step 1a
Step 2 Step 3 Step 4
Step 1
Memory Write Operations
• A memory write operation is carried out in the following steps:
– The processor loads on the Address bus the address of the memory location (Step 1).
• Some of the address lines select the memory devices that owns the memory location
to be written (Step 1a), while the rest point to the required memory location within
the memory device.
– The processor loads on the data bus the data to be written (Step 2).
– The processor activates the Write (WR) signal (Step 3).
• The data at the data bus is stored in the memory location specified by the address
bus (Step 4).
Clock T1 T2 T3
Address Bus Valid Address
Data Bus Valid Data
Chip Enable
Write (WR)
Step 2
Step 1
Step 4
Step 1a Step 3
Memory Expansion on Motherboards
Memory Expansion Memory Expansion
Using 4 SIMMs on using 4 Memory
the Motherboard Chips on a SIMM
Motherboard
Slot 3 Slot 4
SIMM
Slot 1 Slot 2
SIMM SIMM
Processor
Semiconductor Memory Expansion
• Address size memory expansion:
– The size of common memory chips is usually less or in the order of 256M-byte.
– Most personal computers have more than 2 GB of RAM.
– Address size expansion increases the word number and does this by utilizing multiple
memory chip connected in parallel to the data bus and each of these chips are
selected one at a time by the higher order address lines.
• Word size memory expansion:
– Most memory devices/chips have a word size (number of data lines) of 8 or 16 bits.
– The word size of today’s microprocessors is 32 bits (80386, 80486) or 64 bits
(Pentium)
– Multiple memory chips are connected to the data bus to achieve the required word
size.
First
Check this
out
Memory Address Size Expansion
• More than one memory chips can be used to expand the number of memory locations
on the system.
• To expand the address size do the following:
– Determine the number of memory chips required, by dividing the required
memory size with the size of the memory devices to be used.
– Connect the data lines of each memory chip in parallel on the data lines of
the processor.
– Connect the address lines of each memory chip in parallel with the low
address lines of the processor.
– Connect the CS lines of each memory device with the high address lines of
the processor through an address decoding circuit..
– Connect together all WR and all RD lines of each memory device.
Memory Address Size Expansion
After doing all the mentioned tasks, there are two techniques used to connect higher order
address line for chip selection for expanding the main memory address size and word
number in such cases.
They are:
• a) Linear decoding
• b) Full decoding
Linear Decoding:
Consider the problem where we have to build 6 KB memory for an 8-bit microprocessor
whose address bus width is 16 bit. The memory chips which are available are 1K X 8.
We will require 6 RAM chips
A9 – A0 will be connected to all 6
chips in parallel
A15, A14, A13, A12, A11, A10 these
six address lines will chip select
each of the six RAM chips as they
are required
Linear Decoding Address Size Expansion
8 bit mp interfaced to 6KB RAM made from six 1K X 8 RAM Chips
Address Map
Binary Address Pattern Address
Device
Selected
Range
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 in Hex
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 RAM 0400
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Chip 0 07FF
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 RAM 0800
0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 Chip 1 0BFF
0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAM 1000
0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 Chip 2 13FF
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 2000
0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Chip 3 23FF
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 4000
0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Chip 4 43FF
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 8000
1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Chip 5 83FF
Linear Decoding Address Size Expansion
Advantages
Does not require any decoder circuit.
Disadvantages
Although there is an address bus of 16-bits wide, we could connect only
6KB of RAM. This idea clearly wasted address space.
Address map is not contiguous. It is sparsely distributed.
Conflicts occur if two of the select lines become active at the same time.
If all unused address lines are not used as chip selectors, then these
unused lines become don’t cares. This results in fold-back, meaning a
memory location will have its image in memory map. For example, if
A15 is don’t care, then address 0000H is same as address 8000H. It
wastes memory space. This case is known as partial decoding where not
all the address lines are used for locating a word.
Partial Decoding
Notice:
1 less RAM chip
A9 to A0; these
10 address lines
are used select
each of the 1K
locations in a
chip.
Only 5 address
lines are used
for selecting 5
of the RAM
chips.
A15 is not
required and is
left not
connected.
8 bit mp interfaced to 5KB RAM made from five 1K X 8 RAM Chips
Address Map
Binary Address Pattern Device
Selecte
*
Address Mirrored
Range Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 d in Hex Range
NC 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 RAM 0400 8400
NC 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Chip 0 07FF 87FF
NC 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 RAM 0800 8800
NC 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 Chip 1 0BFF 8BFF
NC 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 RAM 1000 9000
NC 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 Chip 2 13FF 93FF
NC 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 2000 A000
NC 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Chip 3 23FF A3FF
NC 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 4000 C000
NC 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Chip 4 43FF C3FF
* That is because the NC address line A15 can either be 0 or can be 1
Full Decoding Address Size Expansion
Full Decoding:
Consider an example where we interface 4KB of RAM to an 8 – bit microprocessor. Again
the RAM chips are available in the form of 1K X 8. This time first we build memory map to
identify the address lines to be given to the decoder.
We will require 4 RAM chips
A9 – A0 will be connected to all 4 chips in parallel.
A15, A14, A13, A12, these 4 address lines will do chip selection of a 2 to 4 decoder in
combination.
Each of the four RAM chips will be selected by the 2 to 4 decoder whose input will be
address lines A11, A10
Address Map
Binary Address Pattern Address
Device
Selected
Range
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 in Hex
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM 0000
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Chip 0 03FF
0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 RAM 0400
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 Chip 1 07FF
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 RAM 0800
0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 Chip 2 0BFF
0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 RAM 0C00
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 Chip 3 0FFF
Full Decoding Address Size Expansion
8 bit mp interfaced to
4KB RAM made from
four 1K X 8 RAM Chips
Problem 1
Use address size expansion to build a 32X4 RAM using 8X4 RAM chips and
interface it with a 4 bit mp with 7 bit address bus.
Address has to be in 110 0000 to 111 1111 range.
Address Map
Binary Address Pattern Address line A2, A1 and A0 will be
Device
A6 A5 A4 A3 A2 A1 A0 Selected connected to all four RAM chips to
select each of their 8 word locations.
1 1 0 0 0 0 0 RAM
1 1 0 0 1 1 1 Chip 0 Address line A4 and A3 will be fed into
1 1 0 1 0 0 0 RAM a 2x4 decoder to chip select each of the
1 1 0 1 1 1 1 Chip 1 four RAM chips.
1 1 1 0 0 0 0 RAM
1 1 1 0 1 1 1 Chip 2 Address line A6 and A5 must remain
high to chip select the 2x4 decoder to
1 1 1 1 0 0 0 RAM
Chip 3
obtain the required address range.
1 1 1 1 1 1 1
Address Size Expansion: (32X4 RAM module using 8X4 RAM chips)
Problem 2
Use address size expansion to build a 32X4 RAM using 8X4 RAM chips and
interface it with a 4 bit mp with 8 bit address bus.
Address has to be in 1100 0000 to 1101 1111 range (C0H to DFH)
Address Map
Address line A2, A1 and A0 will be
Binary Address Pattern
Device connected to all four RAM chips to
Selected select each of their 8 word locations.
A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 0 0 0 0 0 RAM Address line A4 and A3 will be fed into
1 1 0 0 0 1 1 1 Chip 0
a 2x4 decoder to chip select each of the
1 1 0 0 1 0 0 0 RAM four RAM chips.
1 1 0 0 1 1 1 1 Chip 1
1 1 0 1 0 0 0 0 RAM Address line A7 and A6 must remain
1 1 0 1 0 1 1 1 Chip 2 high and A5 must remain low to chip
1 1 0 1 1 0 0 0 select the 2x4 decoder to obtain the
RAM
1 1 0 1 1 1 1 1 Chip 3 required address range.
Example: (32X4 RAM module using 8X4 RAM chips - Assume an 8-address line processor)
Problem 2
Design an 8KX8 RAM module using 2KX8 RAM chips. The module should
be connected to an 8-bit processor with a 16-bit address bus and occupy the
address range which starts from the address A000. Show the circuit .
#Number of memory devices needed = 8K/2K = 4
#Number of address lines on each 2KX8 memory chip = 11 because
2K = 2 x 1K = 21 x 210 = 211 (A10 to A0)
#Decoder needed = 2X4. A12 & A11 address lines will be used as input for
the decoder
#Number of address lines needed for the chip select the decoder will be
three because, 16 - 11 - 2 = 3 (A15, A14 A13)
Address Map
Binary Address Pattern Address
Device
Selected
Range
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 in Hex
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM A000
1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 Chip 0 A7FF
1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 RAM A800
1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 Chip 1 AFFF
1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 RAM B000
1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 Chip 2 B7FF
1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 RAM B800
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Chip 3 BFFF
Circuit Diagram
D7
D0 D7 D0 D7 D0 D7 D0 D7
2Kx8 RAM 2Kx8 RAM 2Kx8 RAM 2Kx8 RAM
D0 A0 A0 A0 A0
A10 A10 A10 A10
RD WR CS RD WR CS RD WR CS RD WR CS
RD
WR
A0
2X4 DEC.
A11
A Y0
A12
B Y1
A13
Y2
A14
CS Y3
A15 A15
Word Size Memory Expansion
If it is required to have a memory of word size ‘W’ and the word size of the
availability memory ICs is ‘w’ (W>w and W= nw where n=2,3,4,…), then ‘n’
number of similar ICs can be combined together to achieve the desired word
size of ‘W’ from smaller ICs of word size ‘w’.
For example, if we need a RAM of 16 bit word length (W=16) and to build
this if we have chips or ICs of only w=4 bit word length, then we have to
have n= W/w = 16/4 = 4 similar ICs or RAM chips connected side by side to
all the data lines of the 16 bit Data BUS.
This type of memory expansion is what we call memory word size expansion
where multiple smaller word memory chips are used side by side to
implement larger word size memory.
Word Size Memory Expansion
How to connect?
These chips are to be connected in the following way:
Connect the corresponding address lines of each chip individually that is
A0 of each chip is connected together and it becomes A0 of the overall
memory. Similarly connect other address lines together.
Connect the RD input of each IC together and it becomes the read input for
the overall memory. Similarly connect the WR and CS inputs.
Data lines from each of the chips will be connected sequentially to each of
the lines of the Data Bus.
The number of data-input/output lines will be equal to the product of the
number of chips used and the word size of each chip and should be equal
to the width of the Data Bus.
Word Size Memory Expansion
Problem 1
Obtain a 16x8 memory using 16x4 memory ICs.
Solution
Since the word size required is W=8 and the word size of the available IC is
w=4, therefore W/w = 2 chips are required to obtain the desired memory.
In this 16x8 memory, the higher order four bits (D7, D6, D5, D4)
of each 8-bit word are located in memory chip M1 and the lower order
four bits (D3, D2, D1, D0) are located in memory chip M0.
A 16 word chip requires only 4 address lines to address all its word locations
and these address lines (A3, A2, A1, A0) from both 4 chips will be connected
in parallel to the address lines of the system.
CS, RD and WR from both chips will be connected to the CS, RD and WR of
the system.
Word Size Memory Expansion
Word Size Memory Expansion
Problem 2
Obtain a 16x12 memory using 16x4 memory ICs.
Solution
Since the word size required is W=12 and the word size of the available IC is
w=4, therefore W/w = 3 chips are required to obtain the desired memory.
In this 16x12 memory, D11, D10, D9 & D8 of each 12-bit word are located in
memory chip M2, D7, D6, D5 & D4 of each 12-bit word are located in
memory chip M1 and D3, D2, D1 & D0 are located in memory chip M0.
A 16 word chip requires only 4 address lines to address all of its word
locations and these address lines (A3, A2, A1, A0) from all 3 chips will be
connected in parallel to the address lines of the system.
CS, RD and WR from all 3 chips will be connected to the CS, RD and WR of
the system.
Word Size Memory Expansion
Thank you
