MP3398D
MP3398D
DESCRIPTION FEATURES
The MP3398D is a step-up controller with four • 4-String, 350mA/String Max WLED Driver
current channels designed to drive WLED • 5V-to-28V Input Voltage Range
arrays for large LCD panel backlighting • 2.5% Current Matching Accuracy between
applications. The MP3398D allows for flexible Strings
expansion of the number of LED channels by • Programmable Switching Frequency
two or more ICs in parallel sharing a single • PWM and Analog Dimming Mode
inductive power source. • Cascading Capability with a Single Power
The MP3398D employs peak-current mode with Source
a fixed switching frequency. The frequency is • LED Open and Short LED Protection
programmable by an external setting resistor. • Programmable Over-Voltage Protection
The MP3398D drives an external MOSFET to (OVP)
boost up the output voltage from a 5V to 28V • Recoverable Thermal Shutdown
input supply and can regulate the current in • Over-Current Protection (OCP)
each LED string to the value set by an external • Inductor/Diode Short Protection
current-setting resistor. • Under-Voltage Lockout (UVLO)
The MP3398D applies four internal current • Available in SOIC16 and SOIC20 Packages
sources for current balancing. The current
matching can achieve 2.5% regulation accuracy
APPLICATIONS
between strings. The low regulation voltage on • Desktop LCD Flat-Panel Displays
the LED current sources reduces power loss. • Flat-Panel Video Displays
• 2D/3D LCD TVs and Monitors
The MP3398D can support both analog and
PWM dimming independently to meet different All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
dimming mode requests. Full protection “MPS” and “The Future of Analog IC Technology” are registered trademarks of
features include over-current protection (OCP), Monolithic Power Systems, Inc.
TYPICAL APPLICATION
L1 D1 VOUT
VIN
C1 C2
GND
R1
15
VIN GATE 14
C3 R2
16 13
VCC ISENSE
1 R6
4
COMP GND
String 1
String 2
String 3
String 4
R4 2 12
EN MP3398D OVP
C4 5 11
OSC LED1
R5 7 10
ADIM LED2
3
9
PWM LED3
6 8
ISET LED4
R3
ORDERING INFORMATION
Part Number Package Top Marking
MP3398DGS* SOIC16
See Below
MP3398DGY** SOIC20
* For Tape & Reel, add suffix –Z (e.g. MP3398DGS–Z)
** For Tape & Reel, add suffix –Z (e.g. MP3398DGY–Z)
PACKAGE REFERENCE
TOP VIEW TOP VIEW
COMP 1 16 VCC
EN 2 15 VIN
PWM 3 14 GATE
GND 4 13 ISENSE
OSC 5 12 OVP
ISET 6 11 LED1
ADIM 7 10 LED2
LED4 8 9 LED3
SOIC16 SOIC20
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 5V, TA = 25°C, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Operating input voltage VIN 5 28 V
VIN = 12V, VEN = 5V,
Supply current (quiescent) IQ 1.2 1.35 1.5 mA
no load without switching
VIN = 12V, VEN = 5V,
Supply current (operation) IOP 3 5.5 mA
no load with switching
Supply current (shutdown) IST VEN = 0V, VIN = 12V 0.01 0.5 μA
VEN = 5V, 7V < VIN < 28V,
LDO output voltage VCC 5.4 6 6.6 V
0 < IVCC < 10mA
VCC UVLO threshold VIN_UVLO Rising edge 3.6 4 4.4 V
VCC UVLO hysteresis 200 mV
EN high voltage VEN_HIGH VEN rising 1.4 V
EN low voltage VEN_LOW VEN falling 0.6 V
Step-Up Converter
Gate driver impedance
VCC = 6V, VGATE = 6V 4.5 7 Ω
(sourcing)
Gate driver impedance (sinking) VCC = 6V, IGATE = 10mA 2.5 5 Ω
ROSC = 115kΩ 459 540 621 kHz
Switching frequency fSW
ROSC = 374kΩ 150 180 210 kHz
OSC voltage VOSC 1.20 1.23 1.26 V
Maximum duty cycle DMAX ROSC = 115kΩ 90 93 %
Cycle-by-cycle ISENSE current
Max duty cycle 175 220 265 mV
limit
COMP source current limit ICOMP SOLI 1V < COMP < 1.9V 70 μA
COMP sink current limit ICOMP SILI 1V < COMP < 1.9V 17 μA
COMP transconductance GCOMP ∆ICOMP = ±10μA 400 μA/V
Current Dimming
PWM input low threshold VPWM_LO VPWM falling 0.6 V
PWM input high threshold VPWM_HI VPWM rising 1.4 V
ADIM input low threshold VADIM_LO VADIM falling 0.6 V
ADIM input high threshold VADIM_HI VADIM rising 1.4 V
PIN FUNCTIONS
SOIC16 SOIC20
Name Description
Pin # Pin #
Step-up converter compensation. COMP compensates for the regulation
1 1 COMP
control loop. Connect a ceramic capacitor from COMP to GND.
Enable control input. A voltage on EN greater than 1.4V turns the MP3398D
2 2 EN
on; a voltage less than 0.6V turns the MP3398D off. Do not leave EN floating.
Input signal for PWM brightness control. By applying a PWM signal on
PWM, the LED current can be chopped, and the average current equals ISET x
DDIM, where ISET is the LED current value set by a resistor connected to PIN 6,
and DDIM is the duty cycle of the PWM dimming duty cycle.
Ensure that the PWM amplitude voltage level is greater than VPWM_HI and the
3 3 PWM low-level voltage is less than VPWM_LO. The input PWM signal frequency mainly
determines the LED current dimming ratio. A lower dimming frequency can
result in a smaller dimming current. In general, 200Hz to 2kHz is suitable for
most LED current dimming applications. If PWM is floating, weakly pull it to
GND internally. If PWM dimming is not required, pull PWM to a high voltage
(1.4V < VPWM < 5V).
BLOCK DIAGRAM
Selecting the Power MOSFET Please note that calculating the switching loss is
The MP3398D is capable of driving a wide the most difficult part in loss estimation. The
variety of N-channel power MOSFETs. The formula above provides a simplified equation. For
critical parameters for selecting a MOSFET are more accurate estimates, the equation becomes
maximum drain-to-source voltage (VDS(MAX)), much more complex.
maximum current (ID(MAX)), on-resistance (RDS(ON)), The total gate charge (QG) is used to calculate
gate-source charge (QGS) and gate-drain charge the gate drive loss and can be calculated with
(QGD), and total gate charge (QG). Equation (11):
Ideally, the off-state voltage across the MOSFET PDR = Q G × VDR × f SW (11)
should equal the output voltage. Considering the
voltage spike when the MOSFET turns off, Where VDR is the drive voltage.
VDS(MAX) should be greater than 1.5 times the
Selecting the Output Capacitor
output voltage.
The output capacitor keeps the output voltage
The maximum current through the power ripple small and ensures feedback loop stability.
MOSFET occurs at the minimum input voltage The output capacitor impedance must be low at
and the maximum output power. The maximum the switching frequency. Ceramic capacitors with
RMS current through the MOSFET is given by X7R dielectrics are recommended for their low
Equation (7): ESR characteristics. For most applications, a
= IIN(MAX) × DMAX
IRMS(MAX) (7) 4.7μF ceramic capacitor in parallel with a 22μF
electrolytic capacitor is sufficient.
DMAX can be calculated with Equation (8):
Setting the Over-Voltage Protection (OVP)
V − VIN(MIN)
DMAX ≈ OUT (8) Open-string protection is achieved through the
VOUT detection of the voltage on the OVP pin. In some
The current rating of the MOSFET should be cases, an LED string failure results in the
greater than 1.5 times IRMS. The on resistance of feedback voltage always being zero. The part
the MOSFET determines the conduction loss, then continues boosting the output voltage higher
which is given by Equation (9): and higher. If the output voltage reaches the
programmed OVP threshold, the protection is
Pcond = IRMS × R DS (ON) × k
2
(9) triggered.
Where k is the temperature coefficient of the To ensure that the chip functions properly, select
MOSFET. the resistor values for the OVP resistor divider to
The switching loss is related to QGD and QGS1, provide an appropriate set voltage. The
which determine the commutation time. QGS1 is recommended OVP point is about 1.1 to 1.2
the charge between the threshold voltage and times higher than the output voltage for normal
the plateau voltage when a driver charges the operation. The OVP voltage can be calculated
gate, which can be read in the VGS vs. QG chart in with Equation (12):
the MOSFET datasheet. QGD is the charge during RHIGH
the plateau voltage. These two parameters are VOVP= 1.23 × (1 + ) (12)
needed to estimate the turn-on and turn-off RLOW
losses, and can be calculated with Equation (10):
Q GS1 × R G
PSW = × VDS × IIN × f SW +
VDR − VTH
(10)
Q GD × R G
× VDS × IIN × f SW
VDR − VPLT
Where VTH is the threshold voltage, VPLT is the
plateau voltage, RG is the gate resistance, and
VDS is the drain-source voltage.
PACKAGE INFORMATION
SOIC16
0.291 0.394
(7.40) (10.00) 0.370
0.299 0.418 (9.40)
(7.60) (10.60)
PIN 1 ID
1 10
0.093(2.35)
0.104(2.65) 0.009(0.23)
SEATING PLANE
0.013(0.33)
0.013(0.33) 0.050(1.27) 0.004(0.10)
0.020(0.51) BSC 0.012(0.30) SEE DETAIL "A"
0.010(0.25)
x 45o NOTE:
0.030(0.75)
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.