KEMBAR78
Digital Design Verilog Assignment Solutions | PDF | Electronic Circuits | Electronic Design
Scribd
Upload
25 views3 pages

Digital Design Verilog Assignment Solutions

The document provides solutions to various digital design assignments using Verilog, covering topics such as critical path delays in adders, 2's complementers, and full adders for adding numbers. It also discusses comparators, multipliers, state diagrams, and finite state machines (FSMs) with detailed implementations. Additionally, it includes information on ripple counters, D flip-flops, and binary counters.

Uploaded by

ece.23beca47
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
25 views3 pages

Digital Design Verilog Assignment Solutions

The document provides solutions to various digital design assignments using Verilog, covering topics such as critical path delays in adders, 2's complementers, and full adders for adding numbers. It also discusses comparators, multipliers, state diagrams, and finite state machines (FSMs) with detailed implementations. Additionally, it includes information on ripple counters, D flip-flops, and binary counters.

Uploaded by

ece.23beca47
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

Digital Design with Verilog - Assignment Solutions

Q1. Critical Path Delay in Adders:

(a) Ripple-Carry Adder: 18.8 ns

(b) Carry Lookahead Adder (no fan-in limit): ~5.6 ns

(c) Fan-in 4: ~7.5 ns

Q2. 4-bit 2s Complementer using XOR gates:

- Use XOR to invert bits

- Add 1 using adder circuit

- Extendable to 5-bit by repeating structure

Q3. Add Three 4-bit Numbers:

(a) TNFA = Two Full Adders: (X+Y) + Z

(b) Use 4 TNFAs chained with carries to get 6-bit result

Q4. Count 1s in 7-bit Input Using Full Adders:

- Use binary tree of Full Adders

- Combine intermediate sums and carries to get 3-bit output

Q5. Use of Z, N, V for Comparisons:

-A=B Z=1

-A<B N V=1

- A > B Z = 0 and N V = 0

Q6. 2-bit Equality Comparator Using 8:1 MUX:

- Set select lines from A and B

- Use MUX inputs to output 1 only for equal conditions

Q7. Multiply BCD by 5:

- Shift left by 2 (4), then add original input

- Result = 2-digit BCD (max 45)


Q8. Number Representation Table (completed)

Q9. |A B| Circuit:

- Use subtractor AB and BA

- Use comparator to choose correct absolute difference

Q10. Parity with NAND Gates:

(a) Delay per bit: 3.3n ns

(b) Group 2 bits: Delay log2(n) 3.3 ns

Q11. Logic Using 2:1 MUX:

- NOT, AND, OR, D-Latch, D-FF all implemented by adjusting MUX inputs

Q12. 4-bit Comparator (Signed/Unsigned):

- Unsigned: Compare bits from MSB to LSB

- Signed: Consider sign bit separately

Q13. 4-bit Comparator using 22-bit Units:

(a) Lower bits affect output only when upper bits equal

(b) G0=0, E0=1, L0=0

(c,d,e) G, L, E = logical expressions with XOR, AND, OR

Q14. 8-bit Comparison Using 2:1 MUX:

- Cascade priority comparators using MUXes

- Use 3 MUXes per stage (total ~24)

Q15. State Diagram and Reduction:

- (a) Draw original diagram

- (b) Merge equivalent states

- (c) Draw reduced FSM

Q16. Output from Input String:

- FSM generates same output for both original and reduced tables

Q17. FSM with D Flip-Flops:


(a) Transition: 0001111000

(b) Alternate: 0011011000

Q18. Serial 2s Complementer:

- FSM: Wait for first 1, then invert rest

- Reset to clear FSM

Q19. Sequential Circuit with T Flip-Flops:

- Use excitation table to determine T inputs

- Build from state diagram

Q20. Serial Adder (Moore & Mealy):

- Moore: Output depends on state

- Mealy: Output depends on state + input

Q21. Ripple Counter Timing:

- 3-bit ripple counter waveforms for CLK, Q0, Q1, Q2

Q22. FSM for Vending Machine:

- Accepts quarters and dollars

- Dispense on 75c, return 25c for dollar

Q23. D-Latch with MUX and Transmission Gates:

- MUX-based selection of D vs Q

- TGs pass D based on EN

Q24. Edge-Triggered D Flip-Flops:

- Use master-slave TG latch structure

- Positive and negative edges depend on TG control

Q25. 4-bit Binary Counter with Parallel Load:

- Implements Clear, Load, Count

- Use flip-flops and control logic for A[3:0], C_out

You might also like