STM32WB50CG

STM32WB30CE
Multiprotocol wireless 32-bit MCU Arm®-based Cortex®-M4
with FPU, Bluetooth® 5.4 or 802.15.4 radio solution
Datasheet - production data

Features
• Include ST state-of-the-art patented
technology
• Radio
UFQFPN48
– 2.4 GHz
7 x 7 mm
– RF transceiver supporting Bluetooth® 5.4 solder pad
specification or IEEE 802.15.4-2011 PHY
and MAC, supporting Thread 1.3 and • Core: Arm® 32-bit Cortex®-M4 CPU with FPU,
Zigbee® 3.0 adaptive real-time accelerator (ART™
– RX sensitivity: -96 dBm (Bluetooth® Low Accelerator) allowing 0-wait-state execution
Energy at 1 Mbps), -100 dBm (802.15.4) from flash memory, frequency up to 64 MHz,
– Programmable output power up to +4 dBm MPU, 80 DMIPS and DSP instructions
with 1 dB steps • Performance benchmark
– Integrated balun to reduce BOM – 1.25 DMIPS/MHz (Drystone 2.1)
– Support for 1 Mbps – 219.48 CoreMark® (3.43 CoreMark/MHz at
– Support GATT caching 64 MHz)
– Support EATT (enhanced ATT) • Energy benckmark
– Support advertising extension – 303 ULPMark™ CP score
– Dedicated Arm® 32-bit Cortex® M0+ CPU • Supply and reset management
for real-time Radio layer
– Ultra-safe, low-power BOR (brownout
– Accurate RSSI to enable power control reset) with five selectable thresholds
– Suitable for systems requiring compliance – Ultra-low-power POR/PDR
with radio frequency regulations ETSI EN
– Programmable voltage detector (PVD)
300 328, EN 300 440, FCC CFR47 Part 15
and ARIB STD-T66 – VBAT mode with RTC and backup registers
– Support for external PA • Clock sources
– Available integrated passive device (IPD) – 32 MHz crystal oscillator with integrated
companion chip for optimized matching trimming capacitors (Radio and CPU clock)
solution (MLPF-WB-01E3) – 32 kHz crystal oscillator for RTC (LSE)
• Ultra-low-power platform – Internal low-power 32 kHz (±5%) RC (LSI1)
– 2.0 to 3.6 V power supply – Internal low-power 32 kHz (stability
– – 10 °C to +85 °C temperature range ±500 ppm) RC (LSI2)
– 14 nA shutdown mode – Internal multispeed 100 kHz to 48 MHz
oscillator, auto-trimmed by LSE (better than
– 700 nA Standby mode + RTC + 32 KB
±0.25% accuracy)
RAM
– High speed internal 16 MHz factory
– 2.25 µA Stop mode + RTC + 128 KB RAM
trimmed RC (±1%)
– Radio: Rx 7.9 mA / Tx at 0 dBm 8.8 mA
– 1x PLL for system clock, ADC

August 2023 DS13047 Rev 9 1/121

This is information on a product in full production. www.st.com
 STM32WB50CG STM32WB30CE

• Memories • Security and ID

– 1 MB flash memory with sector protection – Secure firmware installation (SFI) for
(PCROP) against R/W operations, enabling Bluetooth® Low Energy and 802.15.4 SW
radio stack and application stack
– 128 KB SRAM, including 64 KB with – 2x hardware encryption AES maximum
hardware parity check 256-bit for the application, the Bluetooth®
– 20x 32-bit backup register Low Energy and IEEE802.15.4
– Boot loader supporting USART, SPI, I2C – HW public key authority (PKA)
interfaces – Cryptographic algorithms: RSA,
– OTA (over the air) Bluetooth® Low Energy Diffie-Helman, ECC over GF(p)
and 802.15.4 update – True random number generator (RNG)
– 1 Kbyte (128 double words) OTP – Sector protection against R/W operation
• Rich analog peripherals (down to 2.0 V) (PCROP)
– 12-bit ADC 2.13 Msps, up to 16-bit with – CRC calculation unit
hardware oversampling, 200 µA/Msps – Die information: 96-bit unique ID
• System peripherals – IEEE 64-bit unique ID, possibility to derive
802.15.4 64-bit and Bluetooth® Low Energy
– Inter processor communication controller
48-bit EUI
(IPCC) for communication with Bluetooth®
Low Energy and 802.15.4 • Up to 30 fast I/Os, 28 of them 5 V-tolerant
– HW semaphores for resources sharing • Development support
between CPUs – Serial wire debug (SWD), JTAG for the
– 1x DMA controller (7x channels) supporting application processor
ADC, SPI, I2C, USART, AES, timers – Application cross trigger
– 1x USART (ISO 7816, IrDA, SPI Master, • ECOPACK2 compliant package
Modbus and Smartcard mode)
– 1x SPI 32 Mbit/s
– 1x I2C (SMBus/PMBus®)
– 1x 16-bit, four channels advanced timer
– 2x 16-bit, two channels timer
– 1x 32-bit, four channels timer
– 2x 16-bit ultra low power timer
– 1x independent Systick
– 1x independent watchdog
– 1x window watchdog

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STM32WB50CG STM32WB30CE Contents

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Arm® Cortex®-M4 core with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1 Adaptive real-time memory accelerator (ART Accelerator) . . . . . . . . . . 15
3.3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Security and safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Boot modes and FW update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.6 RF subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.1 RF front-end block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.2 Bluetooth Low Energy general description . . . . . . . . . . . . . . . . . . . . . . 19
3.6.3 802.15.4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.4 RF pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6.5 Typical RF application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.7.2 Linear voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7.3 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.8 VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.12 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 37

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Contents STM32WB50CG STM32WB30CE

3.13.2 Extended interrupts and events controller (EXTI) . . . . . . . . . . . . . . . . . 38

3.14 Analog to digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.15 True random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.16.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.16.2 General-purpose timers (TIM2, TIM16, TIM17) . . . . . . . . . . . . . . . . . . . 40
3.16.3 Low-power timer (LPTIM1 and LPTIM2) . . . . . . . . . . . . . . . . . . . . . . . . 41
3.16.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3.16.5 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.16.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.17 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 42
3.18 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.19 Universal synchronous/asynchronous receiver transmitter (USART) . . . 44
3.20 Serial peripheral interface (SPI1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.21 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.21.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 44

4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.1 Summary of main performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.2 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

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6.3.3 RF BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3.4 RF 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.3.5 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 63
6.3.6 Embedded reset and power control block characteristics . . . . . . . . . . . 63
6.3.7 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.3.8 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3.9 Wake-up time from Low-power modes and voltage scaling
transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.10 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.11 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.12 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.13 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.14 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.15 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.3.16 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.17 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.18 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.3.19 Analog switches booster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.3.20 Analog-to-Digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . 97
6.3.21 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.22 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.23 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.24 Communication interfaces characteristics . . . . . . . . . . . . . . . . . . . . . . 105

7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

7.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.2 UFQFPN48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
7.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114
7.3.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.3.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 114

8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

9 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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List of tables STM32WB50CG STM32WB30CE

List of tables

Table 1. STM32WB50CG and STM32WB30CE device features and peripheral counts . . . . . . . . . 11

Table 2. Access status vs. readout protection level and execution modes . . . . . . . . . . . . . . . . . . . 16
Table 3. RF pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 4. Typical external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 5. Features over all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. STM32WB50CG and STM32WB30CE modes overview . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7. STM32WB50CG and STM32WB30CE CPU1 peripherals interconnect matrix . . . . . . . . . 32
Table 8. DMA implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 9. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 10. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 11. Timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 12. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 13. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions . . . . . . . . . . . . . . . . . . . . . 47
Table 15. Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 16. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 17. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 19. Main performance at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 20. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 21. RF transmitter BLE characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 22. RF transmitter BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 23. RF receiver BLE characteristics (1 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 24. RF BLE power consumption for VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 25. RF transmitter 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 26. RF receiver 802.15.4 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 27. RF 802.15.4 power consumption for VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 28. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 29. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 30. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 31. Current consumption in Run and Low-power run modes, code with data processing
running from flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . . . 66
Table 32. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 33. Typical current consumption in Run and Low-power run modes, with different codes
running from flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V . . . . . . . . . . . . . 67
Table 34. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 35. Current consumption in Sleep and Low-power sleep modes, flash memory ON . . . . . . . . 68
Table 36. Current consumption in Low-power sleep modes, flash memory in Power down. . . . . . . . 69
Table 37. Current consumption in Stop 2 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 38. Current consumption in Stop 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 39. Current consumption in Stop 0 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 40. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 41. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 42. Current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 43. Current under Reset condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 44. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

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Table 45. Low-power mode wake-up timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table 46. Regulator modes transition times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 47. Wake-up time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 48. HSE crystal requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 49. HSE clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 50. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 51. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 52. HSI16 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 53. MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Table 54. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 55. LSI1 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 56. LSI2 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 57. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 58. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 59. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 60. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 61. EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz / 64 MHz, 32 MHz . . . . . . . . 89
Table 62. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 63. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 64. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 65. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 66. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 67. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 68. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 69. Analog switches booster characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 70. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 71. ADC sampling time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 72. ADC accuracy - Limited test conditions 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 73. ADC accuracy - Limited test conditions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 74. ADC accuracy - Limited test conditions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 75. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 76. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 77. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 78. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 79. IWDG min/max timeout period at 32 kHz (LSI1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 80. Minimum I2CCLK frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 81. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 82. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 83. JTAG characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 84. SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 85. UFQFPN48 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 86. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 87. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

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List of figures STM32WB50CG STM32WB30CE

List of figures

Figure 1. STM32WB50CGxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 2. STM32WB30CExx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3. STM32WB50CG and STM32WB30CE RF front-end block diagram . . . . . . . . . . . . . . . . . 19
Figure 4. External components for the RF part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 5. Power-up/down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 6. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 7. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 8. STM32WB50CG and STM32WB30CE UFQFPN48 pinout(1) (2). . . . . . . . . . . . . . . . . . . . . 46
Figure 9. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 13. Typical link quality indicator code vs. Rx level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 14. Typical energy detection (T = 27°C, VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 15. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 16. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 17. HSI16 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 18. Typical current consumption vs. MSI frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 19. HSI48 frequency vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 20. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 21. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 22. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 23. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Figure 24. SPI timing diagram - Slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 25. SPI timing diagram - Slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Figure 26. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Figure 27. UFQFPN48 outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Figure 28. UFQFPN48 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

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1 Introduction

This document provides the ordering information and mechanical device characteristics of
the STM32WB50CG and STM32WB30CE microcontrollers, based on Arm® cores(a).
This document must be read with the reference manual (RM0471), available from the
STMicroelectronics website www.st.com.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32WB50CG and STM32WB30CE errata sheet (ES0492), available from the
STMicroelectronics website www.st.com.
For information on the Arm® Cortex®-M4 and Cortex®-M0+ cores, refer, respectively, to the
Cortex®-M4 Technical Reference Manual and to the Cortex®-M0+ Technical Reference
Manual, both available on the www.arm.com website.
For information on 802.15.4 refer to the IEEE website (www.ieee.org).
For information on Bluetooth® refer to www.bluetooth.com.

a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.

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Description STM32WB50CG STM32WB30CE

2 Description

The STM32WB50CG and STM32WB30CE multiprotocol wireless and ultra-low-power

device embeds a powerful and ultra-low-power radio compliant with the Bluetooth® Low
Energy SIG specification 5.4 or with IEEE 802.15.4-2011. It contains a dedicated Arm®
Cortex®-M0+ for performing all the real-time low layer operation.
The devices are designed to be extremely low-power and are based on the high-
performance Arm® Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz.
This core features a Floating point unit (FPU) single precision that supports all Arm®
single-precision data-processing instructions and data types. It also implements a full set of
DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional
channels. The HSEM provides hardware semaphores used to share common resources
between the two processors.
The devices embed high-speed memories (1 Mbyte of flash memory for STM32WB50xx,
512 Kbytes for STM32WB30xx, 128 Kbytes of SRAM for STM32WB50xx, 96 Kbytes for
STM32WB30xx) and an extensive range of enhanced I/Os and peripherals.
Direct data transfer between memory and peripherals and from memory to memory is
supported by seven DMA channels with a full flexible channel mapping by the DMAMUX
peripheral.
The devices feature several mechanisms for embedded flash memory and SRAM: readout
protection, write protection and proprietary code readout protection. Portions of the memory
can be secured for Cortex® -M0+ exclusive access.
The AES encryption engine, PKA, and RNG enable lower layer MAC and upper layer
cryptography.
The devices offer a fast 16-bit ADC.
These devices embed a low-power RTC, one advanced 16-bit timer, one general-purpose
32-bit timer, two general-purpose 16-bit timers, and two 16-bit low-power timers.
The STM32WB50CG and STM32WB30CE also feature standard and advanced
communication interfaces, namely one USART (ISO 7816, IrDA, Modbus, and Smartcard
mode), one I2C (SMBus/PMBus), one SPI up to 32 MHz.
The STM32WB50CG and STM32WB30CE operate in the -10 to +85 °C (+105 °C junction)
temperature range from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving
modes enables the design of low-power applications.
The devices include independent power supplies for analog input for ADC.
A VBAT dedicated supply allows the device to back up the LSE 32.768 kHz oscillator, the
RTC and the backup registers, thus enabling the STM32WB50CG and STM32WB30CE to
supply these functions even if the main VDD is not present through a CR2032-like battery, a
Supercap or a small rechargeable battery.
The STM32WB50CG and STM32WB30CE are available in a 48-pin UFQFPN package.

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Table 1. STM32WB50CG and STM32WB30CE device features and peripheral counts

Feature STM32WB50CG STM32WB30CE

Flash memory density 1 M bytes 512 Kbytes

SRAM density 128 Kbytes 96 Kbytes
SRAM1 64 Kbytes 32 Kbytes
SRAM2 64 Kbytes 64 Kbytes
BLE 5.4
802.15.4 Yes
Advanced 1 (16 bits)
General purpose 2 (16 bits) + 1 (32 bits)
Timers
Low power 2 (16 bits)
SysTick 1
SPI 1
Communication
I2C 1
interface
USART(1) 1
RTC 1
Tamper pin 1
Wake-up pin 2
GPIOs 30
12-bit ADC 13 channels
Number of channels (incl. 3 internal)
Internal Vref Yes
Max CPU frequency 64 MHz
Ambient operating temperature:-10 to +85 °C
Operating temperature
Junction temperature: -10 to 105 °C
Operating voltage 2.0 to 3.6 V
Package UFQFPN48, 7 mm x 7 mm, 0.5 mm pitch, solder pad
1. USART peripheral can be used as SPI.

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Description STM32WB50CG STM32WB30CE

Figure 1. STM32WB50CGxx block diagram

APB asynchronous

asynchronous
RCC2

AHB
CTI
NVIC BLE IP 802.15.4

AHB Lite
LSI2
32 kHz
Cortex-M0+ BLE / 802.15.4 HSE2
RF IP 32 MHz

32 kB SRAM2a WKUP
Backup Memory BLE
LSE
32 kB SRAM2b RTC2 32 kHz
Shared Memory
1 MB Flash

Memory LSI1
JTAG/SWD

ARBITER
I-WDG 32 kHz

+ ART
PKA + RAM
TAMP
HSEM

AHB Lite (Shared)

RNG
NVIC
HSI 1%
IPCC PLL1 16 MHz
Cortex-M4
MSI up to
(DSP) RCC + CSS 48 MHz
CTI

FPU MPU Power Supply POR/

PWR PDR/BOR/PVD/AVD

EXTI

AES2 RC48
AHB Lite

DMA1 7 channels WWDG

64 KB SRAM1
DMAMUX Memory
DBG
GPIO Ports Temp (oC) sensor
A, B, C, E, H SPI1
ADC1 12-bit ULP
CRC 2.13 Msps / 13 ch
I2C1

APB
LPTIM1 TIM1 USART1

LPTIM2 SYSCFG
TIM2

TIM16, TIM17

MSv63012V2

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Figure 2. STM32WB30CExx block diagram

APB asynchronous

asynchronous
RCC2

AHB
CTI
NVIC BLE IP 802.15.4

AHB Lite
LSI2
32 kHz
Cortex-M0+ BLE / 802.15.4 HSE2
RF IP 32 MHz

32 KB SRAM2a WKUP
Backup BLE
LSE
RTC2 32 kHz
512 KB Flash
Shared Memory

32 kB SRAM2b

Arbiter + ART
LSI1
JTAG/SWD

I-WDG 32 kHz
PKA + RAM
TAMP
HSEM

AHB Lite (Shared)

RNG
NVIC
HSI 1%
IPCC PLL1 16 MHz
Cortex-M4
MSI up to
(DSP) RCC + CSS 48 MHz
CTI

FPU MPU Power Supply POR/

PWR
PDR/BOR/PVD/AVD

EXTI
AHB Lite

AES2 RC48
DMA1 7 channels WWDG
32 KB SRAM1
DMAMUX DBG
GPIO Ports Temp (oC) sensor
A, B, C, E, H SPI1
ADC1 12-bit ULP
CRC 2.13 Msps / 13 ch
I2C1
APB
LPTIM1 TIM1 USART1

LPTIM2 SYSCFG
TIM2

TIM16, TIM17

MS53595V1

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Functional overview STM32WB50CG STM32WB30CE

3 Functional overview

3.1 Architecture
The STM32WB50CG and STM32WB30CE multiprotocol wireless device embeds a
Bluetooth Low Energy or an 802.15.4 RF subsystem that interfaces with a generic
microcontroller subsystem using an Arm® Cortex®-M4 CPU (called CPU1) on which the
host application resides.
The RF subsystem is composed of an RF analog front end, Bluetooth Low Energy or
802.15.4 digital MAC blocks as well as of a dedicated Arm® Cortex®-M0+ microcontroller
(called CPU2), plus proprietary peripherals. The RF subsystem performs all of the Bluetooth
Low Energy or 802.15.4 low layer stack, reducing the interaction with the CPU1 to high level
exchanges.
Some functions are shared between the RF subsystem CPU (CPU2) and the Host CPU
(CPU1):
• Flash memories
• SRAM1, SRAM2a, and SRAM2b (SRAM2a can be retained in Standby mode)
• Security peripherals (RNG, PKA)
• Clock RCC
• Power control (PWR)
The communication and the sharing of peripherals between the RF subsystem and the
Cortex®-M4 CPU is performed through a dedicated inter processor communication
controller (IPCC) and semaphore mechanism (HSEM).

3.2 Arm® Cortex®-M4 core with FPU

The Arm® Cortex®-M4 with FPU is a processor for embedded systems. It has been
developed to provide a low-cost platform that meets the needs of MCU implementation, with
a reduced pin count and low-power consumption, while delivering outstanding
computational performance and an advanced response to interrupts.
The Arm® Cortex®-M4 with FPU 32-bit RISC processor features exceptional
code-efficiency, delivering the high-performance expected from an Arm® core in the
memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions enabling efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded Arm® core, the STM32WB50CG and STM32WB30CE are compatible
with all Arm® tools and software.
Figure 1 and Figure 2 show the general block diagram of, respectively, the STM32WB50CG
and STM32WB30CE devices.

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3.3 Memories

3.3.1 Adaptive real-time memory accelerator (ART Accelerator)

The ART Accelerator is a memory accelerator optimized for STM32 industry-standard Arm®
Cortex®-M4 processors. It balances the inherent performance advantage of the Arm®
Cortex®-M4 over flash memory technologies, which normally require the processor to wait
for the flash memory at higher frequencies.
To release the processor near 80 DMIPS performance at 64 MHz, the accelerator
implements an instruction prefetch queue and branch cache, which increases program
execution speed from the 64-bit flash memory. Based on CoreMark benchmark, the
performance achieved thanks to the ART accelerator is equivalent to 0 wait state program
execution from flash memory at a CPU frequency up to 64 MHz.

3.3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU1 accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to eight protected areas, which can be divided
up into eight subareas. The protection area sizes are between 32 bytes and the whole
4 Gbytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code must be
protected against the misbehavior of other tasks. It is usually managed by an RTOS
(real-time operating system). If a program accesses a memory location prohibited by the
MPU, the RTOS detects it and acts. In an RTOS environment, the kernel can dynamically
update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.

3.3.3 Embedded flash memory

The STM32WB50CG and STM32WB30CE devices feature, respectively, 1 Mbyte and
512 Kbytes of embedded flash memory available for storing programs and data, as well as
some customer keys.
Flexible protections can be configured thanks to option bytes:
• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or
written to if either debug features are connected, boot in SRAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex®-M4 and Cortex®-M0+
JTAG and serial wire), boot in SRAM and bootloader selection are disabled (JTAG
fuse). This selection is irreversible.

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Functional overview STM32WB50CG STM32WB30CE

Table 2. Access status vs. readout protection level and execution modes
Debug, boot from SRAM or boot
User execution
Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase

Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A

System 1 Yes No No Yes No No

memory 2 Yes No No N/A N/A N/A

Option 1 Yes Yes Yes Yes Yes Yes

bytes 2 Yes No (1)
No (1)
N/A N/A N/A
(2)
Backup 1 Yes Yes N/A No No N/A(2)
registers 2 Yes Yes N/A N/A N/A N/A
(2)
SRAM2a 1 Yes Yes Yes No No No(2)
SRAM2b 2 Yes Yes Yes N/A N/A N/A
1. The option byte can be modified by the RF subsystem.
2. Erased when RDP changes from Level 1 to Level 0.

• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas can be selected, with 4-Kbyte granularity.
• Proprietary code readout protection (PCROP): two parts of the flash memory can be
protected against read and write from third parties. The protected area is execute-only:
it can only be reached by the STM32 CPU, as an instruction code, while all other
accesses (DMA, debug and CPU data read, write and erase) are strictly prohibited.
Two areas can be selected, with 2-Kbyte granularity. An additional option bit
(PCROP_RDP) makes possible to select if the PCROP area is erased or not when the
RDP protection is changed from Level 1 to Level 0.
A section of the flash memory is secured for the RF subsystem CPU2, and cannot be
accessed by the host CPU1.
The whole nonvolatile memory embeds the error correction code (ECC) feature supporting:
• single error detection and correction
• double error detection
• the address of the ECC fail can be read in the ECC register
The embedded flash memory is shared between CPU1 and CPU2 on a time sharing basis.
A dedicated HW mechanism allows both CPUs to perform Write/Erase operations.

3.3.4 Embedded SRAM

The STM32WB50CG device features 128 Kbytes of embedded SRAM, split in three blocks:
• SRAM1: 64 Kbytes mapped at address 0x2000 0000
• SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,
with hardware parity check (this SRAM can be retained in Standby mode)
• SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and
mirrored at 0x1000 8000 with hardware parity check

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The STM32WB30CG device features 96 Kbytes of embedded SRAM, split in three blocks:
• SRAM1: 32 Kbytes mapped at address 0x2000 0000
• SRAM2a: 32 Kbytes located at address 0x2003 0000 also mirrored at 0x1000 0000,
with hardware parity check (this SRAM can be retained in Standby mode)
• SRAM2b: 32 Kbytes located at address 0x2003 8000 (contiguous with SRAM2a) and
mirrored at 0x1000 8000 with hardware parity check
SRAM2a and SRAM2b can be write-protected, with 1-Kbyte granularity. A section of the
SRAM2a and SRAM2b is secured for the RF sub-system and cannot be accessed by the
host CPU1.
The SRAMs can be accessed in read/write with 0 wait states for all CPU1 and CPU2 clock
speeds.

3.4 Security and safety

The STM32WB50CG and STM32WB30CE contain many security blocks both for the
Bluetooth Low Energy or IEEE 802.15.4 and the Host application.
It includes:
• Customer storage of the Bluetooth Low Energy or 802.15.4 keys
• Secure flash memory partition for RF subsystem-only access
• Secure SRAM partition, that can be accessed only by the RF subsystem
• True random number generator (RNG)
• Advance encryption standard hardware accelerators (AES-256bit, supporting chaining
modes ECB, CBC, CTR, GCM, GMAC, CCM)
• Private key acceleration (PKA) including:
– Modular arithmetic including exponentiation with maximum modulo size of 3136
bits
– Elliptic curves over prime field scalar multiplication, ECDSA signature, ECDSA
verification with maximum modulo size of 521 bits
• Cyclic redundancy check calculation unit (CRC)
A specific mechanism is in place to ensure that all the code executed by the RF subsystem
CPU2 can be secure, whatever the Host application.

3.5 Boot modes and FW update

At startup, BOOT0 pin and BOOT1 option bit are used to select one of three boot options:
• Boot from user flash
• Boot from system memory
• Boot from embedded SRAM
The devices always boot on CPU1 core. The embedded bootloader code makes it possible
to boot from various peripherals:
• UART
• I2C
• SPI

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Functional overview STM32WB50CG STM32WB30CE

Secure Firmware update (especially Bluetooth Low Energy or 802.15.4) from system boot
and over the air is provided.

3.6 RF subsystem
The STM32WB50CG and STM32WB30CE embed an ultra-low power multi-standard radio
Bluetooth Low Energy or 802.15.4 network processor, compliant with Bluetooth specification
5.4 and IEEE® 802.15.4-2011. The Bluetooth Low Energy features 1 Mbps transfer rate,
supports multiple roles simultaneously acting at the same time as Bluetooth Low Energy
sensor and hub device, embeds Elliptic Curve Diffie-Hellman (ECDH) key agreement
protocol, thus ensuring a secure connection.
The Bluetooth Low Energy stack or 802.15.4 Low Level layer run on an embedded Arm®
Cortex®-M0+ core (CPU2). The stack is stored on the embedded flash memory, which is
also shared with the Arm® Cortex®-M4 (CPU1) application, making it possible in-field stack
update.

3.6.1 RF front-end block diagram

The RF front-end is based on a direct modulation of the carrier in Tx, and uses a low IF
architecture in Rx mode.
Thanks to an internal transformer at RF pins, the circuit directly interfaces the antenna
(single ended connection, impedance close to 50 Ω). The natural bandpass behavior of the
internal transformer, simplifies outside circuitry aimed for harmonic filtering and out of band
interferer rejection.
In Transmit mode, the maximum output power is user selectable through the programmable
LDO voltage of the power amplifier. A linearized, smoothed analog control offers clean
power ramp-up.
In receive mode the circuit can be used in standard high performance or in reduced power
consumption (user programmable). The Automatic gain control (AGC) is able to reduce the
chain gain at both RF and IF locations, for optimized interference rejection. Thanks to the
use of complex filtering and highly accurate I/Q architecture, high sensitivity and excellent
linearity can be achieved.
The bill of material is reduced thanks to the high degree of integration. The radio frequency
source is synthesized form an external 32 MHz crystal that does not need any external
trimming capacitor network thanks to a dual network of user programmable integrated
capacitors.

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RF_TX_MOD_EXT_PA Figure 3. STM32WB50CG and STM32WB30CE RF front-end block diagram

control
AGC
Timer and Power
AGC
control

RF control

ADC
G
Interrupt BLE BP
Wakeup modulator LNA
filter
BLE

ADC
AHB controller
BLE G
APB demodulator
RF1
802.15.4
APB modulator
802.15.4
MAC
Modulator

Interrupt 802.15.4
demodulator PLL
Wakeup

PA
See
note

generator
PA ramp
Adjust Adjust

HSE Trimmed
bias

Max PA
LDO LDO LDO
level

VDD VDDRF

OSC_IN OSC_OUT

32 MHz

Note: UFQFPN48: VSS through exposed pad, and VSSRF pin must be connected to ground plane
MSv63013V2

3.6.2 Bluetooth Low Energy general description

The Bluetooth Low Energy block is a master/slave processor, compliant with Bluetooth
specification 5.4 standard.
It integrates a 2.4 GHz RF transceiver and a powerful Cortex®-M0+ core, on which a
complete power-optimized stack for Bluetooth Low Energy protocol runs, providing
master / slave role support
• GAP: central, peripheral, observer or broadcaster roles
• ATT/GATT: client and server
• SM: privacy, authentication and authorization
• L2CAP
• Link layer: AES-128 encryption and decryption

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In addition, according to Bluetooth specification 5.4, the Bluetooth Low Energy block
provides:
• Multiple roles simultaneous support
• Master/slave and multiple roles simultaneously
• LE data packet length extension (making it possible to reach 800 kbps at application
level)
• LE privacy 1.2
• LE secure connections
• Flexible Internet connectivity options
The devices support Piconet topology (master with up to eight slaves), Scatternet topology
(master with up to six slaves and dynamically as slave with up to two masters, or master
with up to four slaves and dynamically as slave with up to four masters), and multi slave
topology (slave with up to eight masters).
The device allows the applications to meet the tight peak current requirements imposed by
the use of standard coin cell batteries.
Ultra-low-power sleep modes and very short transition time between operating modes result
in very low average current consumption during real operating conditions, resulting in longer
battery life.
The Bluetooth Low Energy block integrates a full bandpass balun, thus reducing the need
for external components.
The link between the Cortex®-M4 application processor (CPU1) running the application, and
the Bluetooth Low Energy stack running on the dedicated Cortex®-M0+ (CPU2) is
performed through a normalized API, using a dedicated IPCC.

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3.6.3 802.15.4 general description

The STM32WB50CG and STM32WB30CE embed a dedicated 802.15.4 hardware MAC:
• Support for 802.15.4 release 2011
• Advanced MAC frame filtering; hardwired firewall: Programmable filters based on
source/destination addresses, frame version, security enabled, frame type
• 256-byte RX FIFO; Up to 8 frames capacity, additional frame information (timing, mean
RSSI, LQI)
• 128-byte TX FIFO with retention
– Content not lost, retransmissions possible under CPU2 control
• Automatic frame acknowledgment, with programmable delay
• Advanced channel access features
– Full CSMA-CA support
– Superframe timer
– Beaconing support (require LSE)
– Flexible TX control with programmable delay
• Configuration registers with retention available down to Standby mode for
software/auto-restore
• Autonomous sniffer, wake-up based on timer or CPU2 request
• Automatic frame transmission/reception/sleep periods, Interrupt to the CPU2 on
particular events

3.6.4 RF pin description

The RF block contains dedicated pins, listed in Table 3.
:

Table 3. RF pin list

Name Type Description

RF1 RF Input/output, must be connected to the antenna through a low-pass matching network
OSC_OUT
32 MHz main oscillator, also used as HSE source
OSC_IN I/O

RF_TX_
External PA transmit control
MOD_EXT_PA
VDDRF VDD Dedicated supply, must be connected to VDD
(1)
VSSRF VSS To be connected to GND
1. The exposed pad must be connected to GND plane for correct RF operation.

3.6.5 Typical RF application schematic

The schematic in Figure 4 and the external components listed in Table 3 are purely
indicative. For more details refer to the “Reference design” provided in separate documents.

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Functional overview STM32WB50CG STM32WB30CE

Figure 4. External components for the RF part

OSC_IN
X1 32 MHz
OSC_OUT
VDD
VDDRF

C1
STM32WB VSSRF
Antenna

microcontroller (including exposed pad)

Lf1
Cf1 Cf2

RF1
Antenna
Lf2 filter

MS53575V1

Table 4. Typical external components

Component Description Value

C1 Decoupling capacitance for RF 100 nF // 100 pF

X1 32 MHz crystal(1) 32 MHz
Antenna filter Antenna filter and matching network Refer to AN5165, on www.st.com
Antenna 2.4 GHz band antenna -
1. e.g. NDK reference: NX2016SA 32 MHz EXS00A-CS06654.

Note: For more details refer to AN5165 “Development of RF hardware using STM32WB
microcontrollers” available on www.st.com.

3.7 Power supply management

3.7.1 Power supply schemes

The devices have different voltage supplies (see Figure 6) and can operate within the
following voltage ranges:
• VDD = 2.0 to 3.6 V: external power supply for I/Os (VDDIO), the internal regulator and
system functions such as RF, reset, power management and internal clocks. It is
provided externally through VDD pins. VDDRF must be always connected to VDD pins.
• VDDA = 2.0 to 3.6 V: external analog power supply for ADC,. The VDDA voltage level
can be independent from the VDD voltage. When not used VDDA must be connected to
VDD.

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During power up/down, the following power sequence requirements must be respected:
• When VDD is below 1 V the other power supply (VDDA), must remain below
VDD + 300 mV
• When VDD is above 1 V all power supplies are independent.

Figure 5. Power-up/down sequence

V

3.6
VDDX(1)

VDD

VBOR0

0.3

Power-on Operating mode Power-down time

Invalid supply area VDDX < VDD + 300 mV VDDX independent from VDD
MSv47490V1

1. VDDX refers to VDDA.

During the power down phase, VDD can temporarily become lower than other supplies only
if the energy provided to the MCU remains below 1 mJ. This allows the external decoupling
capacitors to be discharged with different time constants during the power down transient
phase.
Note: VDD and VDDRF must be wired together, so they can follow the same voltage sequence.

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Functional overview STM32WB50CG STM32WB30CE

Figure 6. Power supply overview

Interruptible domain (VDD12I) On domain (VDD12O)

(CPU1, CPU2,

Level shifter
peripherals, SysConfig, EXTI,
IO SRAM1, RCC, PwrCtrl,
IOs
logic SRAM2b) LPTIM
Power Power
switch switch

VSS
VSS VSS
VDD MR

RFR

LPR
VDDRF
RF domain Backup domain
Radio VBKP12
SRAM2a

Power switch
VSSRF
VSS VSS
(including exposed pad)
Wakeup domain (VDDIO)
VDD HSI, HSE,
Power switch PLL,
VSW LSI1, LSI2,
VBAT IWDG, RF
VSS

Switch domain (VSW)

VBAT IO LSE, RTC,
IOs logic backup registers
VSS
VSS

VDDA Analog domain

ADC
=
VREF+ =
VREF-
VSS

MS53186V2

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3.7.2 Linear voltage regulator

Three embedded linear voltage regulators supply most of the digital and RF circuitries, the
main regulator (MR), the low-power regulator (LPR) and the RF regulator (RFR).
• The MR is used in the Run and Sleep modes and in the Stop 0 mode.
• The LPR is used in Low-Power Run, Low-Power Sleep, Stop 1 and Stop 2 modes. It is
also used to supply the SRAM2a in Standby with retention.
• The RFR is used to supply the RF analog part, its activity is automatically managed by
the RF subsystem.
All the regulators are in power-down in Standby and Shutdown modes: the regulator output
is in high impedance, and the kernel circuitry is powered down, inducing zero consumption.
VCORE can also be supplied by the low-power regulator, the main regulator being switched
off. The system is then in Low-power run mode. In this case the CPU is running at up to
2 MHz, and peripherals with independent clock can be clocked by HSI16 (in this mode the
RF subsystem is not available).

3.7.3 Power supply supervisor

An integrated ultra-low-power brown-out reset (BOR) is active in all modes except
Shutdown ensuring proper operation after power-on and during power down. The devices
remain in reset mode when the monitored supply voltage VDD is below a specified
threshold, without the need for an external reset circuit.
The lowest BOR level is 2.0 V at power on, and other higher thresholds can be selected
through option bytes.The device features an embedded programmable voltage detector
(PVD) that monitors the VDD power supply and compares it with the VPVD threshold. An
interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.

3.7.4 Low-power modes

These ultra-low-power devices support several low-power modes to achieve the best
compromise between low-power consumption, short startup time, available peripherals and
available wake-up sources.
By default, the microcontroller is in Run mode, after a system or a power on reset. It is up to
the user to select one of the low-power modes described below:
• Sleep
In Sleep mode, only the CPU1 is stopped. All peripherals, including the RF subsystem,
continue to operate and can wake up the CPU when an interrupt/event occurs.
• Low-power run
This mode is achieved with VCORE supplied by the low-power regulator to minimize
the regulator operating current. The code can be executed from SRAM or from the
flash memory, and the CPU1 frequency is limited to 2 MHz. The peripherals with
independent clock can be clocked by HSI16. The RF subsystem is not available in this
mode and must be OFF.
• Low-power sleep
This mode is entered from the low-power run mode. Only the CPU1 clock is stopped.
When wake-up is triggered by an event or an interrupt, the system reverts to the

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low-power run mode. The RF subsystem is not available in this mode and must be
OFF.
• Stop 0, Stop 1 and Stop 2
Stop modes achieve the lowest power consumption while retaining the content of all
the SRAM and registers. The LSE (or LSI) is still running.
The RTC can remain active (Stop mode with RTC, Stop mode without RTC).
Some peripherals with wake-up capability can enable the HSI16 RC during Stop modes
to detect their wake-up condition.
Three modes are available: Stop 0, Stop 1 and Stop 2. In Stop 2 mode, most of the
VCORE domain is put in a lower leakage mode.
Stop 1 offers the largest number of active peripherals and wake-up sources, a smaller
wake-up time but a higher consumption than Stop 2. In Stop 0 mode the main regulator
remains ON, allowing a very fast wake-up time but with higher consumption.
In these modes the RF subsystem can wait for incoming events in all Stop modes.
The system clock when exiting from Stop 0, Stop1 or Stop2 modes can be either MSI
up to 48 MHz or HSI16 if the RF subsystem is disabled. If the RF subsystem is used
the exits must be set to HSI16 only.
• Standby
The Standby mode is used to achieve the lowest power consumption with BOR. The
internal regulator is switched off so that the VCORE domain is powered off.
The RTC can remain active (Standby mode with RTC).
The brown-out reset (BOR) always remains active in Standby mode.
The state of each I/O during standby mode can be selected by software: I/O with
internal pull-up, internal pull-down or floating.
After entering Standby mode, SRAM1, SRAM2b and register contents are lost except
for registers in the Backup domain and Standby circuitry. Optionally, SRAM2a can be
retained in Standby mode, supplied by the low-power regulator (Standby with 32 KB
SRAM2a retention mode).
The device exits Standby mode when an external reset (NRST pin), an IWDG reset,
WKUP pin event (configurable rising or falling edge), or an RTC event occurs (alarm,
periodic wake-up, timestamp, tamper) or a failure is detected on LSE (CSS on LSE, or
from the RF system wake-up).
The system clock after wake-up is 16 MHz, derived from the HSI16. In this mode the
RF can be used.

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• Shutdown
This mode achieves the lowest power consumption. The internal regulator is switched
off so that the VCORE domain is powered off.
The RTC can remain active (Shutdown mode with RTC, Shutdown mode without RTC).
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode, therefore the switch to Backup domain is not supported.
SRAM1, SRAM2a, SRAM2b and register contents are lost except for registers in the
Backup domain.
The device exits Shutdown mode when an external reset (NRST pin), a WKUP pin
event (configurable rising or falling edge), or an RTC event occurs (alarm, periodic
wake-up, timestamp, tamper).
The system clock after wake-up is 4 MHz, derived from the MSI.
In this mode the RF is no longer operational.
When the RF subsystem is active, it changes the power state according to its needs (Run,
Stop, Standby). This operation is transparent for the CPU1 host application and managed by
a dedicated HW state machine. At any given time the effective power state reached is the
higher one needed by both the CPU1 and RF sub-system.
Table 5 summarizes the peripheral features over all available modes. Wake-up capability is
detailed in gray cells.

Table 5. Features over all modes(1)

Stop0/Stop1 Stop 2 Standby Shutdown
Low-power sleep
Low-power run

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Sleep

VBAT
Run

Peripheral
- - - -

CPU1 Y - Y - - - - - - - - - -
CPU2 Y - Y - - - - - - - - - -
Radio system
Y Y - - Y Y Y Y Y(2) Y(2)
(BLE, 802.15.4)
Flash memory Y(3) Y O(4) O(4) R - R - R - R - R
SRAM1 Y Y(5) Y Y(5) R - R - - - - - -
(5)
SRAM2a Y Y Y Y(5) R - R - R(6) - - - -
SRAM2b Y Y(5) Y Y(5) R - R - - - - - -
Backup registers Y Y Y Y R - R - R - R - R
Brown-out reset (BOR) Y Y Y Y Y Y Y Y Y Y - - -
Programmable voltage
O O O O O O O O - - - - -
detector (PVD)
DMA1 O O O O - - - - - - - - -
High speed internal
O O O O O(7) - O(7) - - - - - -
(HSI16)

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Functional overview STM32WB50CG STM32WB30CE

Table 5. Features over all modes(1) (continued)

Stop0/Stop1 Stop 2 Standby Shutdown

Low-power sleep
Low-power run

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Sleep

VBAT
Run
Peripheral
- - - -

Oscillator HSI48 O O - - - - - - - - - - -
(8)
High speed external (HSE) O O O O - - - - - - - - -
Low speed internal
O O O O O - O - O - - - -
(LSI1 or LSI2)
Low speed external (LSE) O O O O O - O - O - O - O
Multi speed internal (MSI)(9) 48 O 48 O - - - - - - - - -
PLL VCO maximum
344 O - - - - - - - - - - -
frequency
Clock security system (CSS) O O O O O O(10) O O(10) - - - - -
Clock security system on
O O O O O O O O O O - - -
LSE
RTC / Auto wake-up O O O O O O O O O O O O O
Number of RTC tamper pins 1 1 1 1 1 O 1 O 1 O 1 O 1
(11)
USART1 O O O O O O(11) - - - - - - -
I2C1 O O O O O(12) O(12) - - - - - - -
SPI1 O O O O - - - - - - - - -
ADC1 O O O O - - - - - - - - -
Temperature sensor O O O O - - - - - - - - -
Timers TIMx
O O O O - - - - - - - - -
(x=1, 2, 16, 17)
Low-power Timer 1 (LPTIM1) O O O O O O O O - - - - -
Low-power Timer 2 (LPTIM2) O O O O O O - - - - - - -
Independent watchdog
O O O O O O O O O O - - -
(IWDG)
Window watchdog (WWDG) O O O O - - - - - - - - -
SysTick timer O O O O - - - - - - - - -
True random number
O O - - - - - - - - - - -
generator (RNG)
AES2 hardware accelerator O O O O - - - - - - - - -
CRC calculation unit O O O O - - - - - - - - -
IPCC O - O - - - - - - - - - -
HSEM O - O - - - - - - - - - -

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Table 5. Features over all modes(1) (continued)

Stop0/Stop1 Stop 2 Standby Shutdown

Low-power sleep
Low-power run

Wake-up capability

Wake-up capability

Wake-up capability

Wake-up capability
Sleep

VBAT
Run
Peripheral
- - - -

PKA O O O O - - - - - - - - -

(13) 5 (14) 5
GPIOs O O O O O O O O -
pins pins
1. Legend: Y = Yes (enabled), O = Optional (disabled by default, can be enabled by software), R = Data retained,
- = Not available.
2. Standby with SRAM2a Retention mode only. Stop2 is the deepest low power mode supported when RF is active. When the
user application enters Standby mode, it must first stop all RF activities, and fully re-initialize the CPU2 when coming out of
Standby mode. The application can use the full non secure SRAM2a to store its own content (to be retained in Standby
mode).
3. Flash memory programming only possible in Run, not in Low Power Run.
4. The Flash memory can be configured in Power-down mode. By default, it is not in Power-down Run.
5. The SRAM clock can be gated on or off.
6. SRAM2a content is preserved when the bit RRS is set in PWR_CR3 register.
7. Some peripherals with wake-up from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
8. The HSE can be used by the RF subsystem according with the need to perform RF operation (Tx or Rx).
9. MSI maximum frequency.
10. In case RF will be used and HSE will fail.
11. UART reception is functional in Stop mode, and generates a wake-up interrupt on Start, address match or received frame
event.
12. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
13. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
14. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.

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Functional overview
Table 6. STM32WB50CG and STM32WB30CE modes overview
Mode Regulator CPU1 Flash SRAM Clocks DMA and peripherals Wake-up source Consumption(1) Wake-up time

Run MR Yes ON(2) ON Any All N/A 107 µA/MHz N/A

Any
LPRun LPR Yes ON(2) ON except All except RF, RNG N/A 103 µA/MHz 15.33 µs
PLL
Any interrupt
Sleep MR No ON(2) ON(3) Any All 41 µA/MHz 9 cycles
or event
Any
Any interrupt
LPSleep LPR No ON(2) ON(3) except All except RF, RNG 45 µA/MHz 9 cycles
or event
PLL
RF, BOR, PVD Reset pin, all I/Os,
LSE, RTC, IWDG RF, BOR, PVD
LSI, USART1(6) RTC, IWDG
DS13047 Rev 9

Stop 0 MR No OFF ON 105 µA 1.7 µs

HSE(4), I2C1(7) USART1
HSI16(5) LPTIMx (x=1, 2) I2C1
All other peripherals are frozen. LPTIMx (x=1, 2)
RF, BOR, PVD Reset pin, all I/Os
LSE, RTC, IWDG RF, BOR, PVD
LSI, USART1(6) RTC, IWDG 9.25 µA w/o RTC
Stop 1 LPR No OFF ON 4.7 µs
HSE(4), I2C1(7) USART1 9.45 µA w RTC
HSI16(5)

STM32WB50CG STM32WB30CE
LPTIMx (x=1, 2) I2C1
All other peripherals are frozen. LPTIMx (x=1, 2)
RF, BOR, PVD Reset pin, all I/Os
LSE, RTC, IWDG RF, BOR, PVD 1.85 µA w/o RTC
Stop 2 LPR No OFF ON 5.71 µs
LSI LPTIM1 RTC, IWDG 2.25 µA w RTC
All other peripherals are frozen. LPTIM1
 Table 6. STM32WB50CG and STM32WB30CE modes overview (continued)

STM32WB50CG STM32WB30CE
Mode Regulator CPU1 Flash SRAM Clocks DMA and peripherals Wake-up source Consumption(1) Wake-up time

SRAM2a RF, BOR, RTC, IWDG 0.32 µA w/o RTC

LPR
ON(8) All other peripherals are RF, Reset pin 0.60 µA w RTC
LSE,
Standby No OFF powered off. 2 I/Os (WKUPx)(9) 51 µs
LSI 0.11 µA w/o RTC
OFF OFF I/O configuration can be floating, BOR, RTC, IWDG
pull-up or pull-down 0.39 µA w RTC

RTC
All other peripherals are
2 I/Os (WKUPx)(9), 0.028 µA w/o RTC
Shutdown OFF No OFF OFF LSE powered off. -
RTC 0.315 µA w/ RTC
I/O configuration can be floating,
pull-up or pull-down(10)
1. Typical current at VDD = 2.4 V, 25 °C. for STOPx, SHUTDOWN and Standby, else VDD = 3.3 V, 25 °C.
2. The Flash memory controller can be placed in power-down mode if the RF subsystem is not in use and all the program is run from the SRAM.
3. The SRAM1 and SRAM2 clocks can be gated off independently.
DS13047 Rev 9

4. HSE (32 MHz) automatically used when RF activity is needed by the RF subsystem.
5. HSI16 (16 MHz) automatically used by some peripherals.
6. U(S)ART reception is functional in Stop mode, and generates a wake-up interrupt on Start, Address match or Received frame event.
7. I2C address detection is functional in Stop mode, and generates a wake-up interrupt in case of address match.
8. SRAM1 and SRAM2b are OFF.
9. The I/Os with wake-up from Standby/Shutdown capability are: PA0, PA2.
10. I/Os can be configured with internal pull-up, pull-down or floating but the configuration is lost immediately when exiting the Shutdown mode.

Functional overview
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3.7.5 Reset mode

To improve the consumption under reset, the I/Os state under and after reset is “analog
state” (the I/O Schmitt trigger is disabled). In addition, the internal reset pull-up is
deactivated when the reset source is internal.

3.8 VBAT operation

The VBAT pin allows to power the device VBAT domain (RTC, LSE and Backup registers)
from an external battery, an external supercapacitor, or from VDD when no external battery
nor an external supercapacitor are present. One anti-tamper detection pin is available in
VBAT mode.
VBAT operation is automatically activated when VDD is not present.
An internal VBAT battery charging circuit is embedded and can be activated when VDD is
present.
Note: When the microcontroller is supplied only from VBAT, external interrupts and RTC
alarm/events do not exit it from VBAT operation.

3.9 Interconnect matrix

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU1 resources and, consequently, reducing
power supply consumption. In addition, these hardware connections result in fast and
predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run and Sleep, Stop 0, Stop 1 and Stop 2 modes.

Table 7. STM32WB50CG and STM32WB30CE CPU1 peripherals interconnect matrix

Low-power run

Stop 0 / Stop 1
Low-power

Stop 2
Sleep
Run

Source Destination Action

TIMx Timers synchronization or chaining Y Y Y Y - -

TIMx ADC1 Conversion triggers Y Y Y Y - -
DMA Memory to memory transfer trigger Y Y Y Y - -
ADC TIM1 Timer triggered by analog watchdog Y Y Y Y - -
TIM16 Timer input channel from RTC events Y Y Y Y - -
RTC Low-power timer triggered by RTC
LPTIMERx Y Y Y Y Y Y(1)
alarms or tamper

All clock sources TIM2 Clock source used as input channel

Y Y Y Y - -
(internal and external) TIM16, 17 for RC measurement and trimming

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Table 7. STM32WB50CG and STM32WB30CE CPU1 peripherals interconnect matrix (continued)

Low-power run

Stop 0 / Stop 1
Low-power

Stop 2
Sleep
Run
Source Destination Action

CSS
CPU (hard fault)
TIM1
SRAM (parity error) Timer break Y Y Y Y - -
TIM16,17
Flash memory (ECC error)
PVD

TIMx External trigger Y Y Y Y - -

(1)
GPIO LPTIMERx External trigger Y Y Y Y Y Y
ADC1 Conversion external trigger Y Y Y Y - -
1. LPTIM1 only.

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3.10 Clocks and startup

The STM32WB50CG and STM32WB30CE devices integrate several clock sources:
• LSE: 32.768 kHz external oscillator, for accurate RTC and calibration with other
embedded RC oscillators
• LSI1: 32 kHz on-chip low-consumption RC oscillator
• LSI2: almost 32 kHz, on-chip high-stability RC oscillator, can be used by the RF
subsystem instead of LSE
• HSE: high quality 32 MHz external oscillator with trimming, needed by the RF
subsystem
• HSI16: 16 MHz high accuracy on-chip RC oscillator
• MSI: 100 kHz to 48 MHz multiple speed on-chip low power oscillator, can be trimmed
using the LSE signal
• HSI48: 48 MHz on-chip RC oscillator
The clock controller (see Figure 7) distributes the clocks coming from the different
oscillators to the core and the peripherals including the RF subsystem. It also manages
clock gating for low power modes and ensures clock robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: four different clock sources can be used to drive the master
clock SYSCLK:
– 16 MHz high-speed internal RC oscillator (HSI16), trimmable by software, that can
supply a PLL
– Multispeed internal RC oscillator (MSI), trimmable by software, able to generate
12 frequencies from 100 kHz to 48 MHz. When a 32.768 kHz clock source is
available in the system (LSE), the MSI frequency can be automatically trimmed by
hardware to reach better than ±0.25% accuracy. The MSI can supply a PLL.
– System PLL that can be fed by HSE, HSI16 or MSI, with a maximum frequency of
64 MHz.
• Auxiliary clock source: two ultralow-power clock sources that can be used to drive
the real-time clock:
– 32.768 kHz low-speed external crystal (LSE), supporting four drive capability
modes. The LSE can also be configured in bypass mode for an external clock.
– 32 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock accuracy is ±5%. The LSI source can be either the LSI1 or the LSI2
on-chip oscillator.
• Peripheral clock sources: Several peripherals (RNG, USARTs, I2C, LPTimers, ADC)
have their own independent clock whatever the system clock. A PLL having three
independent outputs for the highest flexibility can generate independent clocks for the
ADC and the RNG.
• Startup clock: after reset, the microcontroller restarts by default with an internal 4 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application

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program as soon as the code execution starts.

• Clock security system (CSS): this feature can be enabled by software. If an HSE
clock failure occurs, the master clock is automatically switched to HSI16 and a software
interrupt is generated if enabled. LSE failure can also be detected and an interrupt
generated.
• Clock-out capability:
– MCO (microcontroller clock output): it outputs one of the internal clocks for
external use by the application. Low frequency clocks (LSIx, LSE) are available
down to Stop 1 low power state.
– LSCO (low-speed clock output): it outputs LSI or LSE in all low-power modes
down to Standby.
Several prescalers allow the user to configure the AHB frequencies, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 64 MHz.

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Functional overview STM32WB50CG STM32WB30CE

Figure 7. Clock tree

LSI1 RC 32 kHz to IWDG

LSI

LSI2 RC 32 kHz
LSI
LSCO
LSE to RTC

OSC32_OUT LSE OSC to BLE wakeup

32.768 kHz LSE
OSC32_IN
to 802.15.4 wakeup
LSE CSS
LSI1
/32
CPU1 to CPU1, AHB1, AHB2, and SRAM1
LSI2 HCLK1
HPRE
/32 /1,2,...,512 to CPU1 FCLK
LSE

HSE to CPU1 system timer

/8
MCO SYSCLK
/1 - 16
APB1 PCLK1 to APB1
PLLRCLK
PPRE1
HSI16 SYS clock /1,2,4,8,16 x1 or to APB1 TIMx
source control x2
MSI
PLLRCLK APB2
RC48 PCLK2 to APB2
PPRE2
HSI16
OSC_OUT HSE OSC SYSCLK /1,2,4,8,16 x1 or to APB2 TIMx
32 MHz HSE HSEPRE/1,2 x2
OSC_IN
CPU2 to CPU2
HSE CSS MSI HCLK2
C2HPRE
1,2,...,512 to CPU2 FCLK
HSI16 RC
16 MHz to CPU2 system timer
/8
MSI RC AHB4
100 kHz - 48 MHz HCLK4 to AHB4, Flash memory, SRAM2
SHDHPRE
HSI48 RC /1,2,...,512
48 MHz to APB3
MSI HSI16
HCLK5 to AHB5
HSI16 HSE /2
/M
to RF

PLL MSI
PLLPCLK
xN /P
HSI48
/3
PLLQCLK
/Q to RNG
LSI
PLLRCLK PCLKn
/R LSE
SYSCLK to USART1
HSI16

LSE

PCLKn

PCLKn HSI16 to LPTIMx

to ADC SYSCLK to I2Cx LSI

SYSCLK HSI16 LSE

MSv63019V5

3.11 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be
achieved thanks to their mapping on the AHB2 bus.
The I/Os alternate function configuration can be locked, if needed, following a specific
sequence in order to avoid spurious writing to the I/Os registers.

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3.12 Direct memory access controller (DMA)

The device embeds one DMA. Refer to Table 8 for the features implementation.
Direct memory access (DMA) is used to provide high-speed data transfer between
peripherals and memory as well as between memories. Data can be quickly moved by DMA
without any CPU action. This keeps CPU resources free for other operations.
The DMA controller has seven channels in total, a full cross matrix allows any peripheral to
be mapped on any of the available DMA channels. The DMA has an arbiter for handling the
priority between DMA requests.
The DMA supports:
• seven independently configurable channels (requests)
• A full cross matrix between peripherals and all the DMA channels exist. There is also a
HW trigger possibility through the DMAMUX.
• Priorities between requests from DMA channels are software programmable (four
levels consisting in very high, high, medium and low) or hardware in case of equality
(request 1 has priority over request 2, etc.).
• Independent source and destination transfer size (byte, half word, word), emulating
packing and unpacking. Source/destination addresses must be aligned on the data
size.
• Support for circular buffer management.
• Three event flags (DMA half transfer, DMA transfer complete and DMA transfer error)
logically OR-ed together in a single interrupt request for each channel.
• Memory-to-memory transfer.
• Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral
transfers.
• Access to flash memory, SRAM, APB and AHB peripherals as source and destination.
• Programmable number of data to be transferred: up to 65536.

Table 8. DMA implementation

DMA features DMA1
Number of regular channels 7

A DMAMUX block makes it possible to route any peripheral source to any DMA channel.

3.13 Interrupts and events

3.13.1 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 63 maskable interrupt channels plus the 16 interrupt lines of the
Cortex®-M4 with FPU.

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The NVIC benefits are the following:

• Closely coupled NVIC gives low latency interrupt processing
• Interrupt entry vector table address passed directly to the core
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.

3.13.2 Extended interrupts and events controller (EXTI)

The EXTI manages wake-up through configurable and direct event inputs. It provides
wake-up requests to the Power control, and generates interrupt requests to the CPUx NVIC
and events to the CPUx event input.
Configurable events/interrupts come from peripherals able to generate a pulse, and make it
possible to select the Event/Interrupt trigger edge and/or a SW trigger.
Direct events/interrupts are coming from peripherals having their own clearing mechanism.

3.14 Analog to digital converter (ADC)

The device embeds a successive approximation analog-to-digital converter with the
following features:
• 12-bit native resolution, with built-in calibration
• Up to 16-bit resolution with 256 oversampling ratio
• 2.13 Msps maximum conversion rate with full resolution
– Down to 78 ns sampling time
– Increased conversion rate for lower resolution (up to 3.55 Msps for 6-bit
resolution)
• Up to ten external channels and three internal channels: internal reference voltages,
temperature sensor
• Single-ended and differential mode inputs
• Low-power design
– Capable of low-current operation at low conversion rate (consumption decreases
linearly with speed)
– Dual clock domain architecture: ADC speed independent from CPU frequency
• Highly versatile digital interface
– Single-shot or continuous/discontinuous sequencer-based scan mode: two groups
of analog signals conversions can be programmed to differentiate background and
high-priority real-time conversions
– The ADC supports multiple trigger inputs for synchronization with on-chip timers
and external signals
– Results stored into three data register or in SRAM with DMA controller support

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– Data pre-processing: left/right alignment and per channel offset compensation

– Built-in oversampling unit for enhanced SNR
– Channel-wise programmable sampling time
– Three analog watchdog for automatic voltage monitoring, generating interrupts
and trigger for selected timers
– Hardware assistant to prepare the context of the injected channels to allow fast
context switching

3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN17 input channel, which is
used to convert the sensor output voltage into a digital value.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored in the system memory area, accessible in read-only mode.

Table 9. Temperature sensor calibration values

Calibration value name Description Memory address

TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF 75A8 - 0x1FFF 75A9
VDDA = VREF+ = 3.0 V (± 10 mV)
TS ADC raw data acquired at a
TS_CAL2 temperature of 130 °C (± 5 °C), 0x1FFF 75CA - 0x1FFF 75CB
VDDA = VREF+ = 3.0 V (± 10 mV)

3.14.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for
the ADC. VREFINT is internally connected to the ADC1_IN0 input channel. The precise
voltage of VREFINT is individually measured for each part by ST during production test and
stored in the system memory area. It is accessible in read-only mode.

Table 10. Internal voltage reference calibration values

Calibration value name Description Memory address

Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF 75AA - 0x1FFF 75AB
VDDA = 3.6 V (± 10 mV)

3.15 True random number generator (RNG)

The devices embed a true RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.

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3.16 Timers and watchdogs

The STM32WB50CG and STM32WB30CE include one advanced 16-bit timer, one general-
purpose 32-bit timer, two 16-bit basic timers, two low-power timers, two watchdog timers
and a SysTick timer. Table 11 compares the features of the advanced control, general
purpose and low power timers.

Table 11. Timer features

DMA Capture/
Timer Counter Counter Prescaler Complementary
Timer request compare
type resolution type factor outputs
generation channels

Advanced Up, down,

TIM1 16-bits 4 3
control Up/down
General Up, down,
TIM2 32-bits 4 No
purpose Up/down
Any integer
General
TIM16 16-bits Up between 1 Yes 2 1
purpose
and 65536
General
TIM17 16-bits Up 2 1
purpose
LPTIM1
Low power 16-bits Up 1 1
LPTIM2

3.16.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM multiplexed on six
channels. They have complementary PWM outputs with programmable inserted
dead-times. They can also be seen as complete general-purpose timers. The four
independent channels can be used for:
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes) with full modulation capability (0 to
100%)
• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.16.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.

3.16.2 General-purpose timers (TIM2, TIM16, TIM17)

There are up to three synchronizable general-purpose timers embedded in the
STM32WB50CG and STM32WB30CE (see Table 11 for differences). Each general-purpose
timer can be used to generate PWM outputs, or act as a simple time base.
• TIM2
– Full-featured general-purpose timer

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– Features four independent channels for input capture/output compare, PWM or

one-pulse mode output. Can work together, or with the other general-purpose
timers via the Timer Link feature for synchronization or event chaining.
– The counter can be frozen in debug mode.
– Independent DMA request generation, support of quadrature encoders.
• TIM16 and TIM17
– General-purpose timers with mid-range features:
– 16-bit auto-reload upcounters and 16-bit prescalers.
– 1 channel and 1 complementary channel.
– All channels can be used for input capture/output compare, PWM or one-pulse
mode output.
– The timers can work together via the Timer Link feature for synchronization or
event chaining. The timers have independent DMA request generation.
– The counters can be frozen in debug mode.

3.16.3 Low-power timer (LPTIM1 and LPTIM2)

The devices embed two low-power timers, having an independent clock running in Stop
mode if they are clocked by LSE, LSIx or by an external clock. They are able to wake-up the
system from Stop mode.
LPTIM1 is active in Stop 0, Stop 1 and Stop 2 modes.
LPTIM2 is active in Stop 0 and Stop 1 modes.
The low-power timers support the following features:
• 16-bit up counter with 16-bit autoreload register
• 16-bit compare register
• Configurable output: pulse, PWM
• Continuous/ one shot mode
• Selectable software/hardware input trigger
• Selectable clock source
– Internal clock sources: LSE, either LSI1 or LSI2, HSI16 or APB clock
– External clock source over LPTIM input (working even with no internal clock
source running, used by pulse counter application)
• Programmable digital glitch filter
• Encoder mode (LPTIM1 only)

3.16.4 Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and an 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC (LSI) and as it operates independently
from the main clock, it can operate in Stop and Standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free running timer for
application timeout management. It is hardware or software configurable through the option
bytes. The counter can be frozen in debug mode.

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3.16.5 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.

3.16.6 SysTick timer

This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
• a 24-bit down counter
• autoreload capability
• a maskable system interrupt generation when the counter reaches 0
• a programmable clock source.

3.17 Real-time clock (RTC) and backup registers

The RTC is an independent BCD timer/counter, supporting the following features:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
• Two programmable alarms.
• On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
• One anti-tamper detection pin with programmable filter.
• Timestamp feature, which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
• 17-bit auto-reload wake-up timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 20 backup registers are supplied through a switch that takes power either
from the VDD supply (when present) or from the VBAT pin.
The backup registers are 32-bit registers used to store 80 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby or Shutdown mode.
The RTC clock sources can be:
• a 32.768 kHz external crystal (LSE)
• an external resonator or oscillator (LSE)
• one of the internal low power RC oscillators (LSI1 or LSI2, with typical frequency of
32 kHz)
• the high-speed external clock (HSE) divided by 32.

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The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by one of the LSIs, the RTC is not functional in VBAT mode, but is
functional in all low-power modes except Shutdown mode.
All RTC events (alarm, wake-up timer, timestamp or tamper) can generate an interrupt and
wake-up the device from the low-power modes.

3.18 Inter-integrated circuit interface (I2C)

The devices embed one I2C. Refer to Table 12 for the features implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Optional clock stretching
• System Management Bus (SMBus) specification rev 2.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Address resolution protocol (ARP) support
– SMBus alert
• Power System Management Protocol (PMBus™) specification rev 1.1 compatibility
• Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming. Refer to
Figure 7: Clock tree.
• Wake-up from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability

Table 12. I2C implementation

I2C features(1) I2C1

Standard-mode (up to 100 kbit/s) X

Fast-mode (up to 400 kbit/s) X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s) X
Programmable analog and digital noise filters X
SMBus/PMBus hardware support X

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Table 12. I2C implementation (continued)

I2C features(1) I2C1

Independent clock X
Wake-up from Stop 0 / Stop 1 mode on address match X
Wake-up from Stop 2 mode on address match -
1. X: supported.

3.19 Universal synchronous/asynchronous receiver transmitter

(USART)
The devices embed one universal synchronous receiver transmitter.
This interface provides asynchronous communication, IrDA SIR ENDEC support,
multiprocessor communication mode, single-wire half-duplex communication mode and has
LIN master/slave capability. It provides hardware management of the CTS and RTS signals,
and RS485 driver enable.
The USART is able to communicate at speeds of up to 4 Mbit/s, and also provides Smart
Card mode (ISO 7816 compliant) and SPI-like communication capability.
The USART supports synchronous operation (SPI mode), and can be used as an SPI
master.
The USART has a clock domain independent from the CPU clock, allowing it to wake up the
MCU from Stop mode using baudrates up to 200 kbaud. The wake up events from Stop
mode are programmable and can be:
• the start bit detection
• any received data frame
• a specific programmed data frame.
The USART interface can be served by the DMA controller.

3.20 Serial peripheral interface (SPI1)

The SPI interface enables communication up to 32 Mbit/s in master and up to 24 Mbit/s in
slave modes, in half-duplex, full-duplex and simplex modes. The 3-bit prescaler gives 8
master mode frequencies and the frame size is configurable from 4 bits to 16 bits. The SPI
interface supports NSS pulse mode, TI mode and Hardware CRC calculation.
The SPI interface can be served by the DMA controller.

3.21 Development support

3.21.1 Serial wire JTAG debug port (SWJ-DP)

The embedded Arm® SWJ-DP interface is a combined JTAG and serial wire debug port that
enables either a serial wire debug, or a JTAG probe to be connected to the target.

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Debug is performed using only two pins instead of the five required by the JTAG (JTAG pins
can then be reused as GPIOs with alternate function): the JTAG TMS and TCK pins are
shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is
used to switch between JTAG-DP and SW-DP.

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4 Pinouts and pin description

Figure 8. STM32WB50CG and STM32WB30CE UFQFPN48 pinout(1)(2)

PA15
PA14

PA13
PA12
PA11
VDD

VDD
PB7
PB6
PB5
PB4
PB3
48
47
46
45
44
43
42
41
40
39
38
37
VBAT 1 36 PA10
PC14-OSC32_IN 2 35 VDD
PC15-OSC32_OUT 3 34 VDD
PH3-BOOT0 4 33 VDD
PB8 5 32 VSS
PB9 6 31 VDD
NRST 7
UFQFPN48 30 PE4
VDDA 8 29 PB1
PA0 9 28 PB0
PA1 10 27 AT1
PA2 11 26 AT0
PA3 12 25 OSC_IN
13
14
15
16
17
18
19
20
21
22
23
24
PB2

RF1
VSSRF
VDDRF
VDD

OSC_OUT
PA4
PA5
PA6
PA7
PA8
PA9

MSv63017V2

1. The above figure shows the package top view.

2. The exposed pad must be connected to ground plane.

Table 13. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Unless otherwise specified in brackets below the pin name, the pin function during and after
Pin name
reset is the same as the actual pin name
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
TT 3.6 V tolerant I/O
RF RF I/O
I/O structure RST Bidirectional reset pin with weak pull-up resistor
Option for TT or FT I/Os
_f (1)
I/O, Fm+ capable
(2)
_a I/O, with Analog switch function supplied by VDDA
Notes Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
1. The related I/O structures in Table 14 are: FT_f, FT_fa.

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2. The related I/O structures in Table 14 are: FT_a, FT_fa, TT_a.

Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions

I/O structures
Pin (UFQFPN48)

Pin type

Notes
Number

Alternate functions Additional functions

Name (function
after reset)

1 VBAT S - - - -
(1)(2)
2 PC14-OSC32_IN I/O FT CM4_EVENTOUT OSC32_IN
(1)(2)
3 PC15-OSC32_OUT I/O FT CM4_EVENTOUT OSC32_OUT
4 PH3-BOOT0 I/O FT - CM4_EVENTOUT, LSCO(3) -
TIM1_CH2N, I2C1_SCL, TIM16_CH1,
5 PB8 I/O FT_f - -
CM4_EVENTOUT
TIM1_CH3N, I2C1_SDA, IR_OUT,
6 PB9 I/O FT_fa - -
TIM17_CH1, CM4_EVENTOUT
7 NRST I/O RST - - -
8 VDDA S - (4)
- -
ADC1_IN5,
9 PA0 I/O FT_a - TIM2_CH1, TIM2_ETR, CM4_EVENTOUT
RTC_TAMP2/WKUP1
TIM2_CH2, I2C1_SMBA, SPI1_SCK,
10 PA1 I/O FT_a - ADC1_IN6
CM4_EVENTOUT
11 PA2 I/O FT_a - LSCO(3), TIM2_CH3, CM4_EVENTOUT ADC1_IN7, WKUP4
12 PA3 I/O FT_a - TIM2_CH4, CM4_EVENTOUT ADC1_IN8
SPI1_NSS, LPTIM2_OUT,
13 PA4 I/O FT_a - ADC1_IN9
CM4_EVENTOUT
TIM2_CH1, TIM2_ETR, SPI1_SCK,
14 PA5 I/O FT_a - ADC1_IN10
LPTIM2_ETR, CM4_EVENTOUT
TIM1_BKIN, SPI1_MISO, TIM16_CH1,
15 PA6 I/O FT_a - ADC1_IN11
CM4_EVENTOUT
TIM1_CH1N, SPI1_MOSI, TIM17_CH1,
16 PA7 I/O FT_fa - ADC1_IN12
CM4_EVENTOUT
MCO, TIM1_CH1, USART1_CK,
17 PA8 I/O FT_a - ADC1_IN15
LPTIM2_OUT, CM4_EVENTOUT
TIM1_CH2, I2C1_SCL, USART1_TX,
18 PA9 I/O FT_fa - ADC1_IN16
CM4_EVENTOUT
RTC_OUT, LPTIM1_OUT, SPI1_NSS,
19 PB2 I/O FT_a - -
CM4_EVENTOUT
20 VDD S - - - -
(5)
21 RF1 I/O RF - -
22 VSSRF S - - - -
23 VDDRF S - - - -

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Pinouts and pin description STM32WB50CG STM32WB30CE

Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions (continued)

I/O structures
Pin (UFQFPN48)

Pin type

Notes
Number

Alternate functions Additional functions

Name (function
after reset)

24 OSC_OUT O RF (6) - -
25 OSC_IN I RF (6)
- -
(7)
26 AT0 O RF - -
(7)
27 AT1 O RF - -

(8) CM4_EVENTOUT,
28 PB0 I/O TT -
RF_TX_MOD_EXT_PA
(8)
29 PB1 I/O TT LPTIM2_IN1, CM4_EVENTOUT -
30 PE4 I/O FT - CM4_EVENTOUT -
31 VDD S - - - -
32 VSS S - - - -
33 VDD S - - - -
34 VDD S - - - -
35 VDD S - - - -
TIM1_CH3, I2C1_SDA, USART1_RX,
36 PA10 I/O FT_f - -
TIM17_BKIN, CM4_EVENTOUT
TIM1_CH4, TIM1_BKIN2, SPI1_MISO,
37 PA11 I/O FT - -
USART1_CTS, CM4_EVENTOUT
TIM1_ETR, SPI1_MOSI, USART1_RTS,
38 PA12 I/O FT - -
CM4_EVENTOUT
(9)
39 PA13(JTMS_SWDIO) I/O FT JTMS-SWDIO, IR_OUT, CM4_EVENTOUT -
40 VDD S - - - -
PA14 (9) JTCK-SWCLK, LPTIM1_OUT,
41 I/O FT -
(JTCK_SWCLK) I2C1_SMBA, CM4_EVENTOUT
PA15 (9) JTDI, TIM2_CH1, TIM2_ETR, SPI1_NSS,
42 I/O FT -
(JTDI) CM4_EVENTOUT, MCO
JTDO-TRACESWO, TIM2_CH2,
PB3
43 I/O FT_a - SPI1_SCK, USART1_RTS, -
(JTDO)
CM4_EVENTOUT
PB4 (9) NJTRST, SPI1_MISO, USART1_CTS,
44 I/O FT_a -
(NJTRST) TIM17_BKIN, CM4_EVENTOUT
LPTIM1_IN1, I2C1_SMBA, SPI1_MOSI,
45 PB5 I/O FT - USART1_CK, TIM16_BKIN, -
CM4_EVENTOUT
LPTIM1_ETR, I2C1_SCL, USART1_TX,
46 PB6 I/O FT_fa - -
TIM16_CH1N, MCO, CM4_EVENTOUT

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STM32WB50CG STM32WB30CE Pinouts and pin description

Table 14. STM32WB50CG and STM32WB30CE pin and ball definitions (continued)

I/O structures
Pin (UFQFPN48)

Pin type

Notes
Number

Alternate functions Additional functions

Name (function
after reset)

LPTIM1_IN2, TIM1_BKIN, I2C1_SDA,

47 PB7 I/O FT_fa - USART1_RX, TIM17_CH1N, PVD_IN
CM4_EVENTOUT
48 VDD S - - - -
1. PC14 and PC15 are supplied through the power switch. As this switch only sinks a limited amount of current (3 mA), the
use of the PC14 and PC15 GPIOs in output mode is limited:
- the speed must not exceed 2 MHz with a maximum load of 30 pF
- these GPIOs must not be used as current sources (e.g. to drive an LED).
2. After a Backup domain power-up, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the
RTC registers that are not reset by the system reset. For details on how to manage these GPIOs, refer to the Backup
domain and RTC register descriptions in the reference manual RM0471, available on www.st.com.
3. The clock on LSCO is available in Run, Stop, and on PA2 in Standby and Shutdown modes.
4. On UFQFPN48 VDDA is connected to VREF+.
5. RF pin, use the nominal PCB layout.
6. 32 MHz oscillator pins, use the nominal PCB layout according to reference design (see AN5165).
7. Reserved for production, must be kept unconnected.
8. High frequency (above 32 KHz) may impact the RF performance. Set output speed GPIOB_OSPEEDRy[1:0] to 00 (y = 0
and 1) during RF operation.
9. After reset, these pins are configured as JTAG/SW debug alternate functions, and the internal pull-up on PA15, PA13 and
PB4 pins and the internal pull-down on PA14 pin are activated.

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50/121

Pinouts and pin description

Table 15. Alternate functions
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF12 AF11 AF14 AF15

Port TIM2/
TIM1/
TIM1/ TIM16/
SYS_AF TIM2/ TIM1 I2C1 SPI1 RF USART1 IR TIM1 - EVENTOUT
TIM2 TIM17/
LPTIM1
LPTIM2

CM4_
PA0 - TIM2_CH1 - - - - - - - - - TIM2_ETR
EVENTOUT

CM4_
PA1 - TIM2_CH2 - - I2C1_SMBA SPI1_SCK - - - - - -
EVENTOUT

CM4_
PA2 LSCO TIM2_CH3 - - - - - - - - - -
EVENTOUT

CM4_
PA3 - TIM2_CH4 - - - - - - - - - -
EVENTOUT

CM4_
PA4 - - - - - SPI1_NSS - - - - - LPTIM2_OUT
EVENTOUT

CM4_
DS13047 Rev 9

PA5 - TIM2_CH1 TIM2_ETR - - SPI1_SCK - - - - - LPTIM2_ETR

EVENTOUT

CM4_
PA6 - TIM1_BKIN - - - SPI1_MISO - - - TIM1_BKIN - TIM16_CH1
EVENTOUT

CM4_
PA7 - TIM1_CH1N - - - SPI1_MOSI - - - - - TIM17_CH1
EVENTOUT
A
CM4_
PA8 MCO TIM1_CH1 - - - - - USART1_CK - - - LPTIM2_OUT
EVENTOUT

CM4_
PA9 - TIM1_CH2 - - I2C1_SCL - - USART1_TX - - - -
EVENTOUT

STM32WB50CG STM32WB30CE
CM4_
PA10 - TIM1_CH3 - - I2C1_SDA - - USART1_RX - - - TIM17_BKIN
EVENTOUT

CM4_
PA11 - TIM1_CH4 TIM1_BKIN2 - - SPI1_MISO - USART1_CTS - TIM1_BKIN2 - -
EVENTOUT

CM4_
PA12 - TIM1_ETR - - - SPI1_MOSI - USART1_RTS - - - -
EVENTOUT

JTMS- CM4_
PA13 SWDIO
- - - - - - - IR_OUT - - -
EVENTOUT

JTCK- CM4_
PA14 SWCLK
LPTIM1_OUT - - I2C1_SMBA - - - - - - -
EVENTOUT

CM4_
PA15 JTDI TIM2_CH1 TIM2_ETR - - SPI1_NSS MCO - - - - -
EVENTOUT
 Table 15. Alternate functions (continued)

STM32WB50CG STM32WB30CE
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF12 AF11 AF14 AF15

Port TIM2/
TIM1/
TIM1/ TIM16/
SYS_AF TIM2/ TIM1 I2C1 SPI1 RF USART1 IR TIM1 - EVENTOUT
TIM2 TIM17/
LPTIM1
LPTIM2

RF_TX_ CM4_
PB0 - - - - - -
MOD_EXT_PA
- - - - -
EVENTOUT

CM4_
PB1 - - - - - - - - - - - LPTIM2_IN1
EVENTOUT

RTC_ CM4_
PB2 OUT
LPTIM1_OUT - - - SPI1_NSS - - - - - -
EVENTOUT

JTDO-
CM4_
PB3 TRACE TIM2_CH2 - - - SPI1_SCK - USART1_RTS - - - -
EVENTOUT
SWO

CM4_
PB4 NJTRST - - - - SPI1_MISO - USART1_CTS - - - TIM17_BKIN
EVENTOUT
B
DS13047 Rev 9

CM4_
PB5 - LPTIM1_IN1 - - I2C1_SMBA SPI1_MOSI - USART1_CK - - - TIM16_BKIN
EVENTOUT

CM4_
PB6 MCO LPTIM1_ETR - - I2C1_SCL - - USART1_TX - - - TIM16_CH1N
EVENTOUT

CM4_
PB7 - LPTIM1_IN2 - TIM1_BKIN I2C1_SDA - - USART1_RX - - - TIM17_CH1N
EVENTOUT

CM4_
PB8 - TIM1_CH2N - - I2C1_SCL - - - - - - TIM16_CH1
EVENTOUT

CM4_
PB9 - TIM1_CH3N - - I2C1_SDA - - - IR_OUT - - TIM17_CH1
EVENTOUT

CM4_
PC14 - - - - - - - - - - - -
EVENTOUT

Pinouts and pin description

C
CM4_
PC15 - - - - - - - - - - - -
EVENTOUT

CM4_
E PE4 - - - - - - - - - - - -
EVENTOUT

CM4_
H PH3 LSCO - - - - - - - - - - -
EVENTOUT
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Memory mapping STM32WB50CG STM32WB30CE

5 Memory mapping

The STM32WB50CG and STM32WB30CE devices feature a single physical address space
that can be accessed by the application processor and by the RF subsystem.
A part of the Flash memory and of the SRAM2a and SRAM2b memories are made secure,
exclusively accessible by the CPU2, protected against execution, read and write from CPU1
and DMA.
In case of shared resources the SW should implement arbitration mechanism to avoid
access conflicts. This happens for peripherals Reset and clock controller (RCC), Power
controller (PWC), EXTI and Flash interface, and can be implemented using the built-in
semaphore block (HSEM).
By default the RF subsystem and CPU2 operate in secure mode. This implies that part of
the Flash and of the SRAM2 memories can only be accessed by the RF subsystem and by
the CPU2. In this case the Host processor (CPU1) has no access to these resources.
The detailed memory map and the peripheral mapping of the devices can be found in the
reference manual RM0471.

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6 Electrical characteristics

6.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.

6.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).

6.1.2 Typical values

Unless otherwise specified, typical data are based on VDD = VDDA = VDDRF = 3 V,
TA = 25 °C. They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2σ).

6.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.

6.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 9.

6.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 10.

Figure 9. Pin loading conditions Figure 10. Pin input voltage

MCU pin MCU pin

C = 50 pF VIN

MS19210V1 MS19211V1

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Electrical characteristics STM32WB50CG STM32WB30CE

6.1.6 Power supply scheme

Figure 11. Power supply scheme

VBAT

Backup circuitry
1.55 V to 3.6 V (LSE, RTC and
backup registers)
Power switch
VDD VCORE
n x VDD
Regulator

VDDIO1
OUT
Kernel logic

Level shifter
IO (CPU, digital
GPIOs
n x 100 nF + 1 x 4.7 μF logic
IN and memories

VSS

VDDA
VDDA

10 nF + 1 μF VREF+
ADC
VREF-

VSS

VDDRF
100 nF
+ 100 pF VSSRF Radio

Exposed pad VSS

To all modules
MS53513V2

Caution: Each power supply pair (such as VDD / VSS, VDDA / VSS) must be decoupled with filtering
ceramic capacitors as shown in Figure 11. These capacitors must be placed as close as
possible to (or below) the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.

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6.1.7 Current consumption measurement

Figure 12. Current consumption measurement scheme

IDDRF

VDDRF

IDDVBAT

VBAT
IDD

VDD

IDDA

VDDA

MSv63021V1

6.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 16, Table 17 and Table 18
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Device mission profile (application conditions) is compliant with JEDEC JESD47
Qualification Standard. Extended mission profiles are available on demand.

Table 16. Voltage characteristics(1)

Symbol Ratings Min Max Unit

External main supply voltage

VDDX - VSS -0.3 4.0
(including VDD, VDDA, VDDRF, VBAT)
Input voltage on FT_xxx pins min (VDD, VDDA, VDDRF) + 4.0(3)(4) V
VIN(2) Input voltage on TT_xx pins VSS-0.3 4.0
Input voltage on any other pin 4.0
Variations between different VDDX
|∆VDDx| - 50
power pins of the same domain
mV
Variations between all the different
|VSSx-VSS| - 50
ground pins
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 17 for the maximum allowed injected current values.
3. This formula has to be applied only on the power supplies related to the IO structure described in the pin definition table.
4. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.

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110
Electrical characteristics STM32WB50CG STM32WB30CE

Table 17. Current characteristics

Symbol Ratings Max Unit

∑IVDD Total current into sum of all VDD power lines (source)(1) 130
∑IVSS Total current out of sum of all VSS ground lines (sink)(1) 130
IVDD(PIN) Maximum current into each VDD power pin (source)(1) 100
IVSS(PIN) Maximum current out of each VSS ground pin (sink)(1) 100
Output current sunk by any I/O and control pin except FT_f 20
IIO(PIN) Output current sunk by any FT_f pin 20
mA
Output current sourced by any I/O and control pin 20
Total output current sunk by sum of all I/Os and control pins(2) 100
∑IIO(PIN)
(2)
Total output current sourced by sum of all I/Os and control pins 100
Injected current on FT_xxx, TT_xx, RST and B pins, except PB0 and PB1 –5 / +0(4)
IINJ(PIN)(3)
Injected current on PB0 and PB1 -5/0
∑|IINJ(PIN)| Total injected current (sum of all I/Os and control pins)(5) 25
1. All main power (VDD, VDDRF, VDDA, VBAT) and ground (VSS) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count packages.
3. Positive injection (when VIN > VDD) is not possible on these I/Os and does not occur for input voltages lower than the
specified maximum value.
4. A negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 16 for the maximum allowed
input voltage values.
5. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).

Table 18. Thermal characteristics

Symbol Ratings Value Unit

TSTG Storage temperature range –65 to +150

°C
TJ Maximum junction temperature 110

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STM32WB50CG STM32WB30CE Electrical characteristics

6.3 Operating conditions

6.3.1 Summary of main performance

Table 19. Main performance at VDD = 3.3 V

Parameter Test conditions Typ Unit

VBAT (VBAT = 1.8 V, VDD = 0 V) 0.002

Shutdown (VDD = 2.0 V) 0.014
Standby (VDD = 2.0 V, 32 KB SRAM2a retention) 0.35
Stop2 1.85
Core current
ICORE Sleep (16 MHz) 845
consumption
LP run (2 MHz) 320
Run (64 MHz) 8150
(1) µA
Radio RX 7900
Radio TX 0 dBm output power(1) 8800
Advertising with Stop2(2)
20
(Tx = 0 dBm; Period 1.28 s; 31 bytes, 3 channels)
BLE
Peripheral Advertising with Stop2(2)
IPERI current 4
(Tx = 0 dBm, 6 bytes; period 10.24 s, 3 channels)
consumption
LP timers - 6
RTC - 2.5
1. Power consumption including RF subsystem and digital processing.
2. Power consumption averaged over 100 s including Cortex M4, RF subsystem, digital processing and Cortex M0+.

6.3.2 General operating conditions

Table 20. General operating conditions

Symbol Parameter Conditions Min Max Unit

fHCLK Internal AHB clock frequency - 0 64

fPCLK1 Internal APB1 clock frequency - 0 64 MHz
fPCLK2 Internal APB2 clock frequency - 0 64
VDD Standard operating voltage - 2.0(1) 3.6
ADC used 2.0
VDDA Analog supply voltage 3.6 V
ADC not used(2) 2.0
VBAT Backup operating voltage - 1.55 3.6
VDDRF Minimum RF voltage - 2.0 3.6
TT_xx I/O –0.3 VDD + 0.3
V
VIN I/O input voltage min (min (VDD, VDDA) +
All I/O except TT_xx –0.3
3.6 V, 5.5 V)(3)(4)

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110
Electrical characteristics STM32WB50CG STM32WB30CE

Table 20. General operating conditions (continued)

Symbol Parameter Conditions Min Max Unit

Power dissipation at
PD UFQFPN48 - 803 mW
TA = 85 °C for suffix 5
Maximum power dissipation –10 85
TA Ambient temperature
Low-power dissipation(5) 105 °C
TJ Junction temperature range - –10 105
1. When RESET is released functionality is guaranteed down to VBOR0 Min.
2. When not used, VDDA must be connected to VDD.
3. This formula has to be applied only on the power supplies related to the IO structure described by the pin definition table.
Maximum I/O input voltage is the smallest value between min (VDD, VDDA) + 3.6 V and 5.5V.
4. For operation with voltage higher than min (VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be
disabled.
5. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.3:
Thermal characteristics).

6.3.3 RF BLE characteristics

Table 21. RF transmitter BLE characteristics

Symbol Parameter Test conditions Min Typ Max Unit

Fop Frequency operating range - 2402 - 2480

MHz
Fxtal Crystal frequency - - 32 -

∆F Delta frequency - - 250 - kHz

Rgfsk On air data rate - - 1 - Mbps

PLLres RF channel spacing - - 2 - MHz

Table 22. RF transmitter BLE characteristics (1 Mbps)(1)

Symbol Parameter Test conditions Min Typ Max Unit

Maximum output power - - 4.0 -

Prf 0 dBm output power - - 0 - dBm
Minimum output power - - -20 -
Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB
BW6dB 6 dB signal bandwidth Tx = Maximum output power - 670 - kHz
2 MHz Bluetooth® Low Energy:-20 dBm - -50 -
IBSE In band spurious emission dBm
≥ 3 MHz Bluetooth® Low Energy: -30 dBm - -53 -
fd Frequency drift Bluetooth® Low Energy: ±50 kHz -50 - +50 kHz
®
Bluetooth Low Energy: kHz/
maxdr Maximum drift rate -20 - +20
±20 kHz / 50 µs 50 µs

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STM32WB50CG STM32WB30CE Electrical characteristics

Table 22. RF transmitter BLE characteristics (1 Mbps)(1) (continued)

Symbol Parameter Test conditions Min Typ Max Unit
®
Bluetooth Low Energy:
fo Frequency offset -150 - +150
±150 kHz
kHz
Bluetooth® Low Energy:
∆f1 Frequency deviation average 225 - 275
between 225 and 275 kHz
Frequency deviation
∆fa Bluetooth® Low Energy:> 0.80 0.80 - - -
∆f2 (average) / ∆f1 (average)

Out of band < 1 GHz - - -61 -

OBSE(2) dBm
spurious emission ≥ 1 GHz - - -46 -
1. :Measured in conducted mode, based on reference design (see AN5165), using output power specific external RF filter and
impedance matching networks to interface with a 50 Ω antenna.
2. Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440
Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan).

Table 23. RF receiver BLE characteristics (1 Mbps)

Symbol Parameter Test conditions Typ Unit

PER <30.8%
Prx_max Maximum input signal 0
Bluetooth® Low Energy: min -10 dBm

PER <30.8%
Psens(1) High sensitivity mode -96
Bluetooth® Low Energy: max -70 dBm dBm

Rssimaxrange RSSI maximum value - -7

Rssiminrange RSSI minimum value - -94

Rssiaccu RSSI accuracy - 2

dB
®
C/Ico Co-channel rejection Bluetooth Low Energy: 21 dB 8

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Electrical characteristics STM32WB50CG STM32WB30CE

Table 23. RF receiver BLE characteristics (1 Mbps) (continued)

Symbol Parameter Test conditions Typ Unit

Adj ≥ 5 MHz
-53
Bluetooth® Low Energy: -27 dB
Adj ≤ -5 MHz
-53
Bluetooth® Low Energy:-27 dB
Adj = 4 MHz
-48
Bluetooth® Low Energy:-27 dB
Adj = -4 MHz
-33
Bluetooth® Low Energy:-15 dB
Adj = 3 MHz
C/I Adjacent channel interference -46
Bluetooth® Low Energy:-27 dB dB
Adj = 2 MHz
-39
Bluetooth® Low Energy:-17 dB
Adj = -2 MHz
-35
Bluetooth® Low Energy:-15 dB
Adj = 1 MHz
-2
Bluetooth® Low Energy: 15 dB
Adj = -1 MHz
2
Bluetooth® Low Energy: 15 dB
C/Image Image rejection (Fimage = -3 MHz) Bluetooth® Low Energy: -9 dB -29
|f2-f1| = 3 MHz
-34
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 4 MHz
P_IMD Intermodulation -30
Bluetooth® Low Energy: -50 dBm
|f2-f1| = 5 MHz
-32
Bluetooth® Low Energy:-50 dBm
30 to 2000 MHz
-3 dBm
Bluetooth® Low Energy: -30 dBm
2003 to 2399 MHz
-5
Bluetooth® Low Energy: -35 dBm
P_OBB Out of band blocking
2484 to 2997 MHz
-2
Bluetooth® Low Energy: -35 dBm
3 to 12.75 GHz
7
Bluetooth® Low Energy: -30 dBm
1. With ideal TX.

Table 24. RF BLE power consumption for VDD = 3.3 V(1)

Symbol Parameter Typ Unit

Itxmax TX maximum output power consumption 12

Itx0dbm TX 0 dBm output power consumption 8.8 mA
Irxlo Rx consumption 7.9
1. Power consumption including RF subsystem and digital processing.

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6.3.4 RF 802.15.4 characteristics

Table 25. RF transmitter 802.15.4 characteristics

Symbol Parameter Conditions Min Typ Max Unit

Fop Frequency operating range - 2405 - 2480

Fxtal Crystal frequency - - 32 - MHz
∆F Delta frequency - - 5 -
Roqpsk On Air data rate - - 250 - Kbps
PLLres RF channel spacing - - 5 - MHz
(1)
Maximum output power - - 4 -
Prf 0 dBm output power - - 0 - dBm
Minimum output power - - -20 -
Pband Output power variation over the band Tx = 0 dBm - Typical -0.5 - 0.4 dB
EVMrms EVM rms Pmax - 8 - %
Txpd Transmit power density |f - fc| > 3.5 MHz - -35 - dB
1. Measured in conducted mode, based on reference design (see AN5165), using output power specific
external RF filter and impedance matching networks to interface with a 50 Ω antenna.

Table 26. RF receiver 802.15.4 characteristics

Symbol Parameter Conditions Typ Unit

Prx_max Maximum input signal -10

PER < 1% dBm
Rsens Sensitivity -100

C/adj Adjacent channel rejection - 35

dB
C/alt Alternate channel rejection - 46

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110
Electrical characteristics STM32WB50CG STM32WB30CE

Figure 13. Typical link quality indicator code vs. Rx level

Figure 14. Typical energy detection (T = 27°C, VDD = 3.3 V)

Table 27. RF 802.15.4 power consumption for VDD = 3.3 V(1)

Symbol Parameter Typ Unit

Itxmax TX maximum output power consumption 10.7

Itx0dbm TX 0 dBm output power consumption 9.1 mA
Irxlo Rx consumption 9.2

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1. Power consumption including RF subsystem and digital processing.

6.3.5 Operating conditions at power-up / power-down

The parameters given in Table 28 are derived from tests performed under the ambient
temperature condition summarized in Table 20.

Table 28. Operating conditions at power-up / power-down

Symbol Parameter Conditions Min Max Unit

VDD rise time rate - - ∞

tVDD
VDD fall time rate 10 ∞
VDDA rise time rate - 0 ∞
tVDDA µs/V
VDDA fall time rate 10 ∞
VDDRF rise time rate - - ∞
tVDDRF
VDDRF fall time rate - ∞

6.3.6 Embedded reset and power control block characteristics

The parameters given in Table 29 are derived from tests performed under the ambient
temperature conditions summarized in Table 20: General operating conditions.

Table 29. Embedded reset and power control block characteristics

Symbol Parameter Conditions(1) Min Typ Max Unit

tRSTTEMPO(2) Reset temporization after BOR0 is detected VDD rising - 250 400 μs
Rising edge 1.62 1.66 1.70
VBOR0(2) Brown-out reset threshold 0
Falling edge 1.60 1.64 1.69
Rising edge 2.06 2.10 2.14
VBOR1 Brown-out reset threshold 1
Falling edge 1.96 2.00 2.04
Rising edge 2.26 2.31 2.35
VBOR2 Brown-out reset threshold 2
Falling edge 2.16 2.20 2.24
Rising edge 2.56 2.61 2.66
VBOR3 Brown-out reset threshold 3
Falling edge 2.47 2.52 2.57
V
Rising edge 2.85 2.90 2.95
VBOR4 Brown-out reset threshold 4
Falling edge 2.76 2.81 2.86
Rising edge 2.10 2.15 2.19
VPVD0 Programmable voltage detector threshold 0
Falling edge 2.00 2.05 2.10
Rising edge 2.26 2.31 2.36
VPVD1 PVD threshold 1
Falling edge 2.15 2.20 2.25
Rising edge 2.41 2.46 2.51
VPVD2 PVD threshold 2
Falling edge 2.31 2.36 2.41

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Table 29. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions(1) Min Typ Max Unit

Rising edge 2.56 2.61 2.66

VPVD3 PVD threshold 3
Falling edge 2.47 2.52 2.57
Rising edge 2.69 2.74 2.79
VPVD4 PVD threshold 4
Falling edge 2.59 2.64 2.69
V
Rising edge 2.85 2.91 2.96
VPVD5 PVD threshold 5
Falling edge 2.75 2.81 2.86
Rising edge 2.92 2.98 3.04
VPVD6 PVD threshold 6
Falling edge 2.84 2.90 2.96
Hysteresis in
- 20 -
continuous mode
Vhyst_BORH0 Hysteresis voltage of BORH0
Hysteresis in
- 30 - mV
other mode
Hysteresis voltage of BORH (except
Vhyst_BOR_PVD - - 100 -
BORH0) and PVD
BOR(3) (except BOR0) and PVD
IDD (BOR_PVD)(2) - - 1.1 1.6 µA
consumption from VDD
1. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.
2. Guaranteed by design.
3. BOR0 is enabled in all modes (except shutdown) and its consumption is therefore included in the supply current
characteristics tables.

6.3.7 Embedded voltage reference

The parameters given in Table 30 are derived from tests performed under the ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions.

Table 30. Embedded internal voltage reference

Symbol Parameter Conditions Min Typ Max Unit

VREFINT Internal reference voltage –10 °C < TA < +85 °C 1.182 1.212 1.232 V
ADC sampling time when reading
tS_vrefint (1) - 4(2) - -
the internal reference voltage
µs
Start time of reference voltage
tstart_vrefint - - 8 12(2)
buffer when ADC is enable
VREFINT buffer consumption from
IDD(VREFINTBUF) - - 12.5 20(2) µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT VDD = 3 V - 5 7.5(2) mV
over the temperature range
TCoeff Temperature coefficient –10 °C < TA < +85 °C - 30 50(2) ppm/°C
ACoeff Long term stability 1000 hours, T = 25 °C - 300 1000(2) ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200(2) ppm/V

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Table 30. Embedded internal voltage reference (continued)

Symbol Parameter Conditions Min Typ Max Unit

VREFINT_DIV1 1/4 reference voltage 24 25 26

%
VREFINT_DIV2 1/2 reference voltage - 49 50 51
VREFINT
VREFINT_DIV3 3/4 reference voltage 74 75 76
1. The shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design.

Figure 15. VREFINT vs. temperature

1.235

1.230

1.225

1.220
VREFINT (V)

1.215

1.210

1.205

1.200

1.195

1.190

1.185
o
40 -20 0 20 40 60 80 100 T ( C)
120 °C
Mean Min Max
MSv63022V1

6.3.8 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as shown in Figure 12: Current consumption
measurement scheme.

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Typical and maximum current consumption

The MCU is put under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0471 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
The parameters given in Table 31 to Table 42 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.

Table 31. Current consumption in Run and Low-power run modes, code with data processing
running from flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V
Conditions Typ Max(1)
Symbol Parameter Unit
- fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C

fHCLK = fHSI16 up to 64 MHz 8.15 8.25 8.40 9.30 9.60

16 MHz included,
Supply
f =f = 32 MHz
IDD(Run) current in HCLK HSE 32 MHz 4.20 4.25 4.40 4.25 4.63
fHSI16 + PLL ON above
Run mode
32 MHz
All peripherals disabled 16 MHz 2.25 2.30 2.40 2.65 2.91
mA
2 MHz 0.335 0.360 0.470 0.480 0.910
Supply
current in fHCLK = fMSI 1 MHz 0.170 0.210 0.325 0.270 0.730
IDD(LPRun)
Low-power All peripherals disabled 400 kHz 0.0815 0.120 0.230 0.140 0.590
run mode
100 kHz 0.0415 0.076 0.190 0.070 0.550
1. Guaranteed by characterization results, unless otherwise specified.

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Table 32. Current consumption in Run and Low-power run modes, code with data processing
running from SRAM1, VDD = 3.3 V
Conditions Typ Max(1)
Symbol Parameter Unit
- fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C

fHCLK = fHSI16 up to 64 MHz 8.80 8.90 9.00 10.50 10.80

16 MHz included,
Supply 32 MHz 4.50 4.55 4.70 4.63 4.89
fHCLK = fHSE = 32 MHz
IDD(Run) current in
fHSI16 + PLL ON above
Run mode
32 MHz 16 MHz 2.40 2.40 2.55 2.50 2.70
All peripherals disabled
mA
2 MHz 0.265 0.285 0.385 0.440 0.940
Supply
current in fHCLK = fMSI 1 MHz 0.135 0.170 0.270 0.290 0.760
IDD(LPRun)
Low-power All peripherals disabled 400 kHz 0.066 0.097 0.195 0.200 0.670
run mode
100 kHz 0.031 0.0625 0.160 0.170 0.470
1. Guaranteed by characterization results, unless otherwise specified.

Table 33. Typical current consumption in Run and Low-power run modes, with different codes
running from flash, ART enable (Cache ON Prefetch OFF), VDD = 3.3 V
Conditions TYP TYP
Symbol Parameter Unit Unit
- Frequency Code 25 °C 25 °C

Reduced code(1)
16 MHz included, fHSI16 +

8.15 127
All peripherals disabled
PLL ON above 32 MHz
fHCLK = fHSI16 up to

fHCLK = 64 MHz

Coremark 8.00 125

Supply current in
IDD(Run) Dhrystone 2.1 8.10 mA 127
Run mode
Fibonacci 7.60 119

While(1) 6.85 107 µA/MHz

Reduced code(1) 320 160

Coremark 350 175
Supply current in fHCLK = fMSI = 2 MHz
IDD(LPRun) Dhrystone 2.1 350 µA 175
Low-power run All peripherals disabled
Fibonacci 390 195
While(1) 225 113
1. Reduced code used for characterization results provided in Table 31 and Table 32.

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Table 34. Typical current consumption in Run and Low-power run modes,
with different codes running from SRAM1, VDD = 3.3 V
Conditions TYP TYP
Symbol Parameter Unit Unit
- Frequency Code 25 °C 25 °C

Reduced code(1)

16 MHz included, fHSI16 +

8.80 138

PLL ON above 32 MHz

All peripherals disable
fHCLK = fHSI16 up to

fHCLK = 64 MHz
Coremark 7.50 117
Supply current in
IDD(Run) Dhrystone 2.1 8.60 mA 134
Run mode
Fibonacci 7.90 123

While(1) 8.00 125 µA/MHz

Reduced code(1) 255 128

Coremark 205 103
Supply current in fHCLK = fMSI = 2 MHz
IDD(LPRun) Dhrystone 2.1 250 µA 125
Low-power run All peripherals disable
Fibonacci 230 115
While(1) 220 110
1. Reduced code used for characterization results provided in Table 31 and Table 32.

Table 35. Current consumption in Sleep and Low-power sleep modes, flash memory ON
Conditions TYP MAX(1)
Symbol Parameter Unit
- fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C

fHCLK = fHSI16 up to 64 MHz 2.65 2.70 2.80 3.00 3.33

16 MHz included,
fHCLK = fHSE up to
Supply 32 MHz
IDD(Sleep) current in fHSI16 + PLL ON 32 MHz 1.40 1.45 1.60 1.55 1.86
sleep mode, above 32 MHz

All peripherals mA
disabled 16 MHz 0.845 0.875 0.990 0.970 1.40

2 MHz 0.090 0.125 0.235 0.130 0.600

Supply
fHCLK = fMSI 1 MHz 0.058 0.093 0.205 0.090 0.570
current in low-
IDD(LPSleep) All peripherals
power sleep 400 kHz 0.044 0.0725 0.185 0.070 0.540
disabled
mode
100 kHz 0.0315 0.0635 0.0175 0.055 0.530
1. Guaranteed by characterization results, unless otherwise specified.

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Table 36. Current consumption in Low-power sleep modes, flash memory in Power down
Conditions TYP MAX(1)
Symbol Parameter Unit
- fHCLK 25 °C 55 °C 85 °C 25 °C 85 °C

2 MHz 94.0 115 200 135 610

fHCLK = fMSI
Supply current in 1 MHz 56.5 86.0 170 94.2 560
IDD(LPSleep) low-power sleep All µA
mode peripherals 400 kHz 40.5 66.5 150 68.0 540
disabled
100 kHz 27.5 57.5 140 54.6 539

1. Guaranteed by characterization results, unless otherwise specified.

Table 37. Current consumption in Stop 2 mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

Supply current 2.4 V 1.10 1.85 3.20 6.00 22.0 - - -

IDD in Stop 2
BLE disabled 3.0 V 1.10 1.85 3.25 6.10 22.0 1.60 4.17 57.9
(Stop 2) mode, RTC
disabled 3.6 V 1.15 1.95 3.35 6.25 23.0 1.69 4.40 58.6
2.4 V 1.45 2.25 3.55 6.40 22.5 - - -
RTC clocked
Supply current 3.0 V 1.50 2.30 3.70 6.55 22.5 2.11 4.64 58.3
IDD by LSI
in Stop 2 3.6 V 1.75 2.50 3.95 6.85 23.5 2.26 5.12 59.7
(Stop 2
mode, RTC
with RTC clocked by 2.4 V 1.45 2.25 3.65 6.40 22.5 - - - µA
enabled, BLE
RTC) LSE quartz(2)
disabled 3.0 V 1.55 2.45 3.80 6.65 23.0 2.01 4.31 58.0
in low drive
mode 3.6 V 1.70 2.55 4.05 6.95 23.5 2.16 4.40 81.6
Supply current
IDD
during Wake-up clock is
(wake-up
wake-up from MSI = 32 MHz. 3.0 V - 320 - - - - - -
from
Stop 2 mode See(3).
Stop 2)
bypass mode
1. Guaranteed based on test during characterization, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
3. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 45.

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Table 38. Current consumption in Stop 1 mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

Supply 2.4 V 5.10 9.25 15.5 28.5 96.5 - - -

IDD current in
BLE disabled 3.0 V 5.15 9.30 15.5 28.5 97.0 7.07 28.5 346.8
(Stop 1) Stop 1 mode,
RTC disabled 3.6 V 5.25 9.45 16.0 29.0 97.5 7.30 28.8 351.0
2.4 V 5.40 9.45 16.0 28.5 97.0 - - -
RTC clocked by
Supply 3.0 V 5.70 9.55 16.5 29.0 98.5 7.69 29.7 347.2
IDD LSI
current in 3.6 V 5.85 10.0 16.5 29.5 96.5 8.08 29.8 349.9
(Stop 1
Stop 1 mode,
with 2.4 V 5.40 9.70 16.0 29.0 96.5 - - - µA
RTC enabled, RTC clocked by
RTC)
BLE disabled LSE quartz(2) in 3.0 V 5.75 9.70 16.0 29.0 97.5 7.40 28.9 346.6
Low drive mode
3.6 V 5.90 10.0 16.5 29.5 99.0 7.58 29.2 349.0
Supply
IDD
current during Wake-up clock
(wake-
wake-up from MSI = 32 MHz. 3.0 V - 124 - - - - - -
up from
Stop 1 See (3).
Stop1)
bypass mode
1. Guaranteed based on test during characterization, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
3. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 45.

Table 39. Current consumption in Stop 0 mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C

Supply current 2.4 V 97.5 105 110 125 195 - - -

in Stop 0 mode,
- 3.0 V 98.5 105 110 125 195 117.3 134.3 461.8
RTC disabled,
IDD BLE disabled 3.6 V 100 105 115 125 200 165.0 135.7 494.0
µA
(Stop 0) Supply current
Wake-up clock
during wake-up
MSI = 32 MHz. 3.0 V - 349 - - - - - -
from Stop 0
See (2).
Bypass mode
1. Guaranteed by characterization results, unless otherwise specified.
2. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 45.

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Table 40. Current consumption in Standby mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C
Supply BLE disabled, 2.4 V 0.270 0.350 0.540 0.955 3.50 - - -
current in no independent 3.0 V 0.270 0.370 0.575 1.00 3.85 0.380 0.945 8.505
Standby mode watchdog
IDD (backup 3.6 V 0.300 0.410 0.645 1.15 4.20 0.400 1.040 8.980
(Standby) registers and BLE disabled, 2.4 V 0.280 0.595 0.790 1.20 4.00 - - -
SRAM2a with 3.0 V 0.290 0.670 0.855 1.35 4.15 0.730 1.253 8.774
retained), independent
RTC disabled watchdog 3.6 V 0.295 0.770 0.990 1.50 4.60 0.851 1.356 9.360
RTC clocked by 2.4 V 0.630 0.705 0.910 1.30 3.80 - - -
LSI, no 3.0 V 0.725 0.825 1.050 1.50 3.95 0.930 1.463 8.977 µA
Supply independent
current in watchdog 3.6 V 0.860 0.970 1.200 1.70 4.25 1.050 1.628 9.634
Standby mode
IDD (backup RTC clocked by 2.4 V 0.635 0.790 0.975 1.40 4.10 - - -
(Standby with registers and LSI, with 3.0 V 0.725 0.915 1.100 1.55 4.50 1.028 1.573 9.072
RTC) SRAM2a independent
watchdog 3.6 V 0.870 1.050 1.300 1.80 4.90 1.144 1.723 9.730
retained),
RTC enabled RTC clocked by 2.4 V 0.665 0.755 0.960 1.35 4.05 - - -
BLE disabled LSE quartz (2) in 3.0 V 0.775 0.880 1.100 1.55 4.40 0.600 1.100 8.719
low drive mode 3.6 V 0.935 1.050 1.300 1.80 5.00 0.750 1.171 9.460
Supply 2.4 V 0.165 0.245 0.375 0.650 2.15 - - -
current to be
subtracted in
IDD 3.0 V 0.155 0.250 0.385 0.630 2.25 - - -
(3) Standby mode - µA
(SRAM2a)
when
SRAM2a is 3.6 V 0.155 0.235 0.375 0.670 2.20 - - -
not retained
Supply
IDD Wake-up clock
current during
(wake-up is HSI16. 3.0 V - 1.73 - - - - - - mA
wake-up from
from Standby) See (4).
Standby mode
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
3. The supply current in Standby with SRAM2a mode is: IDD(Standby) + IDD(SRAM2a). The supply current in Standby with
RTC with SRAM2a mode is: IDD(Standby + RTC) + IDD(SRAM2a).
4. Wake-up with code execution from flash memory. Average value given for a typical wake-up time as specified in Table 45.

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Table 41. Current consumption in Shutdown mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VDD 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 85 °C
Supply current 2.4 V 0.059 0.014 0.055 0.120 0.785 - - -
in Shutdown
IDD mode (backup
- 3.0 V 0.064 0.037 0.070 0.180 1.000 - 0.185 2.670
(Shutdown) registers
retained) RTC
3.6 V 0.071 0.093 0.140 0.280 1.300 - 0.247 3.120
disabled
µA
Supply current 2.4 V 0.425 0.405 0.460 0.540 1.200 - - -
RTC clocked
in Shutdown
IDD by LSE
mode (backup
(Shutdown quartz (2) in 3.0 V 0.535 0.535 0.595 0.700 1.500 - 0.664 2.990
with RTC) registers low drive
retained) RTC mode 3.6 V 0.695 0.720 0.790 0.940 2.000 - 0.790 3.730
enabled
1. Guaranteed by characterization results, unless otherwise specified.
2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with
two 6.8 pF loading capacitors.

Table 42. Current consumption in VBAT mode

Conditions TYP MAX(1)
Symbol Parameter Unit
- VBAT 0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 40 °C 55 °C 85 °C
2.4 V 1.00 2.00 5.00 12.0 60.0 - - - - -
RTC disabled 3.0 V 2.00 4.00 7.00 16.0 75.0 - - - - -
Backup
domain 3.6 V 7.00 15.0 23.0 42.0 170 - - - - -
IDD(VBAT) nA
supply RTC enabled 2.4 V 385 395 400 415 475 - - - - -
current and clocked 3.0 V 495 505 515 530 600 - - - - -
by LSE
quartz(2) 3.6 V 630 645 660 685 830 - - - - -

1. Guaranteed by characterization results, unless otherwise specified.

2. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.

Table 43. Current under Reset condition

TYP MAX(1)
Symbol Conditions Unit
0 °C 25 °C 40 °C 55 °C 85 °C 0 °C 25 °C 40 °C 55 °C 85 °C
2.4 V - - - - - - - - - -
IDD(RST) 3.0 V - 550 - - - - 750 - - - µA
3.6 V - 750 - - - - - - - -
1. Guaranteed by characterization results, unless otherwise specified.

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I/O system current consumption

The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull resistors generate current consumption when the pin is
externally held to the opposite level. The value of this consumption can be simply computed
by using the pull-up/pull-down resistors values given in Table 65: I/O static characteristics.
For the output pins, all the internal or external pull-down/pull-down and the external load
must be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins, which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 44) the I/Os used by an application also contribute to the current consumption. When
an I/O pin switches, it uses the current from the I/O supply voltage to supply the I/O pin
circuitry and to charge/discharge the capacitive load (internal and external) connected to the
pin: ISW = VDD x fSW x C, where
• ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
• VDD is the I/O supply voltage
• fSW is the I/O switching frequency
• C is the total capacitance seen by the I/O pin: C = CIO + CEXT
• CIO is the I/O pin capacitance
• CEXT is the PCB board capacitance plus any connected external device pin
capacitance.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.

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On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 44. The MCU is placed
under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 16:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in
Table 44. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.

Table 44. Peripheral current consumption

Low-power
Peripheral Run Unit
run and sleep

Bus Matrix(1) 2.40 1.80

CRC 0.465 0.380
AHB1 DMA1 1.90 1.80
DMAMUX 4.15 4.45
All AHB1 peripherals 8.75 8.65
ADC independent clock domain 2.55 2.10
(2)
AHB2 ADC clock domain 2.25 1.90
All AHB2 peripherals 3.45 2.7 µA/MHz
TRNG independent clock domain 3.80 N/A
TRNG clock domain 2.00 N/A
SRAM2 1.70 1.35
AHB Shared FLASH 8.35 8.45
AES2 6.95 7.00
PKA 4.40 4.25
All AHB shared peripherals 17.5 16.0

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Table 44. Peripheral current consumption (continued)

Low-power
Peripheral Run Unit
run and sleep

RTC 1.10 1.25

I2C1 independent clock domain 2.50 4.40
I2C1 clock domain 4.80 5.50
LPTIM1 independent clock domain 2.10 3.00
LPTIM1 clock domain 3.60 3.80
APB1
TIM2 5.65 4.90
LPTIM2 clock domain 3.95 4.50
LPTIM2 independent clock domain 2.20 3.80
WWDG 0.335 0.965
All APB1 peripherals 17.0 13.55 µA/MHz
AHB to APB2(3) 1.10 1.35
TIM1 8.20 7.25
TIM17 2.85 2.40
TIM16 2.75 2.55
APB2
USART1 independent clock domain 4.40 7.00
USART1 clock domain 8.80 7.75
SPI1 1.75 1.45
All APB2 on 25.5 22
ALL 72.2 62.9
1. The BusMatrix is automatically active when at least one master is ON (CPU, DMA).
2. GPIOs consumption during read and write accesses.
3. The AHB to APB2 bridge is automatically active when at least one peripheral is ON on the APB2.

6.3.9 Wake-up time from Low-power modes and voltage scaling

transition times
The wake-up times given in Table 45 are the latency between the event and the execution of
the first user instruction.
The device goes in Low-power mode after the WFE (Wait For Event) instruction.

Table 45. Low-power mode wake-up timings(1)

Symbol Parameter Conditions Typ Max Unit

Wake-up time from

tWUSLEEP Sleep mode - 9 10
to Run mode No. of
CPU
Wake-up time from Wake-up in flash with memory in power-down cycles
tWULPSLEEP Low-power sleep mode during low-power sleep mode (FPDS = 1 in 9 10
to Low-power run mode PWR_CR1) and with clock MSI = 2 MHz

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Table 45. Low-power mode wake-up timings(1) (continued)

Symbol Parameter Conditions Typ Max Unit

Wake up time from Wake-up clock MSI = 32 MHz 2.38 2.96

Stop 0 mode
-
to Run mode in flash Wake-up clock HSI16 = 16 MHz 1.69 2.00
tWUSTOP0 memory
Wake up time from Wake-up clock MSI = 32 MHz 2.63 3.00
Stop 0 mode -
to Run mode in SRAM1 Wake-up clock HSI16 = 16 MHz 1.80 2.00

Wake up time from Wake-up clock MSI = 32 MHz 4.67 5.56

Stop 1 mode -
to Run in flash memory Wake-up clock HSI16 = 16 MHz 5.09 6.03

Wake up time from Wake-up clock MSI = 32 MHz 4.88 5.55 µs

Stop 1 mode -
to Run in SRAM1 Wake-up clock HSI16 = 16 MHz 5.29 5.95

tWUSTOP1 Wake up time from

Stop 1 mode to
7.96 9.59
Low-power run mode Regulator in
in flash memory Low-power
Wake-up clock MSI = 4 MHz
Wake up time from mode (LPR = 1
Stop 1 mode to in PWR_CR1)
8.00 9.47
Low-power run mode
in SRAM1
Wake up time from Wake-up clock MSI = 32 MHz 5.27 6.07
Stop 2 mode
-
to Run mode in flash Wake-up clock HSI16 = 16 MHz 5.71 6.52
tWUSTOP2 memory µs
Wake up time from Wake-up clock MSI = 32 MHz 5.20 5.94
Stop 2 mode to Run -
mode in SRAM1 Wake-up clock HSI16 = 16 MHz 5.64 6.42

Wake-up time from

tWUSTBY Standby mode - Wake-up clock HSI16 = 16 MHz 51.0 58.1 µs
to Run mode
1. Guaranteed by characterization results (VDD = 3 V, .T = 25 °C).

Table 46. Regulator modes transition times(1)

Symbol Parameter Conditions Typ Max Unit

Wake-up time from Low-power run mode

tWULPRUN Code run with MSI 2 MHz 15.33 16.30 µs
to Run mode(2)
1. Guaranteed by characterization results (VDD = 3 V, T = 25 °C).
2. Time until REGLPF flag is cleared in PWR_SR2.

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Table 47. Wake-up time using USART(1)

Symbol Parameter Conditions Typ Max Unit

Wake-up time needed to calculate the maximum Stop mode 0 - 1.7

tWUUSART USART baud rate allowing to wake-up up from Stop µs
mode when USART clock source is HSI16 Stop mode 1/2 - 8.5

1. Guaranteed by design.

6.3.10 External clock source characteristics

High-speed external user clock generated from an external source
The high-speed external (HSE) clock is supplied with a 32 MHz crystal oscillator or a sine or
a square wave.
The STM32WB50CG and STM32WB30CE include internal programmable capacitances
that can be used to tune the crystal frequency to compensate the PCB parasitic one.
The characteristics in Table 48 and Table 50 are measured over recommended operating
conditions, unless otherwise specified. Typical values are referred to TA = 25 °C and
VDD = 3.0 V.

Table 48. HSE crystal requirements(1) (2)

Symbol Parameter Conditions Min Typ Max Unit

fNOM Oscillator frequency - - 32 - MHz

Includes initial accuracy, stability over
(3)
fTOL Frequency tolerance temperature, aging and frequency pulling - - ppm
due to incorrect load capacitance.
CL Load capacitance - 6 - 8 pF
ESR Equivalent series resistance - - - 100 Ω
1. 32 MHz XTAL is validated for the specific reference NX2016SA.
2. For information about the HSE crystal refer to AN5165 “Development of RF hardware using STM32WB microcontrollers”,
available on www.st.com.
3. Refer to the standard specification: 50 ppm for BLE, 40 ppm for 802.15.4.

Table 49. HSE clock source characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSE_ext Oscillator frequency - - 32 - MHz

Includes initial accuracy, stability (2)
fTOLHSE Frequency tolerance - - ppm
over temperature and aging
VHSE Clock input voltage limits Sine or square wave, AC-coupled(3) 0.4 - 1.6 VPP
DuCy(HSE) Duty cycle - 45 50 55 %
tr, tf Rise and fall times 10% - 90% square wave - - 15 * VPP ns

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Table 49. HSE clock source characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Offset = 10 kHz - - -127

φn(HSE) Phase noise for 32 MHz Offset = 100 kHz - - -135 dBc/Hz
Offset = 1 MHz - - -138
1. Guaranteed by design.
2. Refer to the standard specification: 50 ppm for BLE, 40 ppm for 802.15.4.
3. Only AC coupled is supported (capacitor 470 pF to 100 nF).

Table 50. HSE oscillator characteristics

Symbol Parameter Conditions Min Typ Max Unit

Startup time VDDRF stabilized, XOTUNE = 000000,

tSUA(HSE) - 1000 -
for 80% amplitude stabilization -10 to +85 °C range
µs
Startup time VDDRF stabilized, XOTUNE = 000000,
tSUR(HSE) - 250 -
for XOREADY signal -10 to +85 °C range
IDDRF(HSE) HSE current consumption(1) HSEGMC = 000, XOTUNE = 000000 - 50 - µA
XOTg(HSE) XOTUNE granularity - 1 5
ppm
XOTfp(HSE) XOTUNE frequency pulling ±20 ±40 -
Capacitor bank
XOTnb(HSE) XOTUNE number of tuning bits - 6 - bit
XOTst(HSE) XOTUNE setting time - - 0.1 ms
1. Current consumption in standalone mode. The current consumption at device level is 350 µA in design simulation.

Note: For information about the trimming of the oscillator refer to AN5165 “Development of RF
hardware using STM32WB microcontrollers”, available on www.st.com.

Low-speed external user clock generated from an external source

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. The information provided in this section is based on design simulation results
obtained with typical external components specified in Table 51. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).

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Table 51. Low-speed external user clock characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

LSEDRV[1:0] = 00
- 250 -
Low drive capability
LSEDRV[1:0] = 01
- 315 -
Medium low drive capability
IDD(LSE) LSE current consumption nA
LSEDRV[1:0] = 10
- 500 -
Medium high drive capability
LSEDRV[1:0] = 11
- 630 -
High drive capability
LSEDRV[1:0] = 00
- - 0.50
Low drive capability
LSEDRV[1:0] = 01
- - 0.75
Medium low drive capability
Gmcritmax Maximum critical crystal gm µA/V
LSEDRV[1:0] = 10
- - 1.70
Medium high drive capability
LSEDRV[1:0] = 11
- - 2.70
High drive capability
tSU(LSE)(2) Startup time VDD stabilized - 2 - s
Includes initial accuracy, stability
ftolLSE Frequency tolerance over temperature, aging and -500 - +500 ppm
frequency pulling
1. Guaranteed by design.
2. tSU(LSE) is the startup time measured from the moment it is enabled (by software) until a stable 32 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.

Note: For information on selecting the crystal refer to AN2867 “Oscillator design guide for STM8S,
STM8A and STM32 microcontrollers” available from www.st.com.

Figure 16. Typical application with a 32.768 kHz crystal

Resonator with integrated

capacitors
CL1

OSC32_IN fLSE

32.768 kHz Drive

resonator programmable
amplifier

OSC32_OUT
CL2

MS30253V2

Note: An external resistor is not required between OSC32_IN and OSC32_OUT, and it is
forbidden to add one.

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6.3.11 Internal clock source characteristics

The parameters given in Table 52 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 20: General operating
conditions. The provided curves are characterization results, not tested in production.

High-speed internal (HSI16) RC oscillator

Table 52. HSI16 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI16 HSI16 frequency VDD = 3.0 V, TA = 30 °C 15.88 - 16.08 MHz

Trimming code is not a
0.2 0.3 0.4
multiple of 64
TRIM HSI16 user trimming step
Trimming code is a
-4 -6 -8
multiple of 64
DuCy(HSI16)(2) Duty cycle - 45 - 55 %

HSI16 oscillator frequency drift over TA = 0 to 85 °C -1 - 1

∆Temp(HSI16)
temperature TA = -10 to 85 °C -2 - 1.5
∆VDD(HSI16) HSI16 oscillator frequency drift over VDD VDD = 2 V to 3.6 V -0.1 - 0.05
tsu(HSI16)(2) HSI16 oscillator start-up time - - 0.8 1.2
μs
tstab(HSI16)(2) HSI16 oscillator stabilization time - - 3 5
IDD(HSI16)(2) HSI16 oscillator power consumption - - 155 190 μA
1. Guaranteed by characterization results.
2. Guaranteed by design.

Figure 17. HSI16 frequency vs. temperature

MHz
16.4
+2%
16.3
+1.5%
16.2 +1%

16.1

16

15.9

-1%
15.8
-1.5%
15.7
-2%
15.6
0 20 40 60 80 100
min mean max
MSv63023V1

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Multi-speed internal (MSI) RC oscillator

Table 53. MSI oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Range 0 98.7 100 101.3

Range 1 197.4 200 202.6
kHz
Range 2 394.8 400 405.2
Range 3 789.6 800 810.4
Range 4 0.987 1 1.013
Range 5 1.974 2 2.026
MSI mode
Range 6 3.948 4 4.052
Range 7 7.896 8 8.104
MHz
Range 8 15.79 16 16.21
Range 9 23.69 24 24.31

MSI frequency Range 10 31.58 32 32.42

after factory Range 11 47.38 48 48.62
fMSI calibration, done
at VDD = 3 V and Range 0 - 98.304 -
TA = 30 °C Range 1 - 196.608 -
kHz
Range 2 - 393.216 -
Range 3 - 786.432 -
Range 4 - 1.016 -
PLL mode Range 5 - 1.999 -
XTAL =
32.768 kHz Range 6 - 3.998 -
Range 7 - 7.995 -
MHz
Range 8 - 15.991 -
Range 9 - 23.986 -
Range 10 - 32.014 -
Range 11 - 48.005 -
MSI oscillator TA = -0 to 85 °C -3.5 - 3
∆TEMP(MSI)(2) frequency drift MSI mode %
over temperature TA = -10 to 105 °C -8 - 6

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Table 53. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

VDD =
-1.2 -
2 to 3.6 V
Range 0 to 3 0.5
VDD =
-0.5 -
2.4 to 3.6 V

MSI oscillator VDD =

-2.5 -
frequency drift 2 to 3.6 V
∆VDD(MSI)(2) MSI mode Range 4 to 7 0.7
over VDD VDD =
(reference is 3 V) -0.8 -
2.4 to 3.6 V %
VDD =
-5 -
2 to 3.6 V
Range 8 to 11 1
VDD =
-1.6 -
2.4 to 3.6 V
Frequency
∆FSAMPLING
variation in MSI mode TA = -10 to 85 °C - 1 2
(MSI)(2)(4)
sampling mode(3)
RMS cycle-to-
CC jitter(MSI)(4) PLL mode Range 11 - - 60 -
cycle jitter ps
P jitter(MSI)(4) RMS period jitter PLL mode Range 11 - - 50 -
Range 0 - - 10 20
Range 1 - - 5 10

MSI oscillator Range 2 - - 4 8

tSU(MSI)(4) μs
start-up time Range 3 - - 3 7
Range 4 to 7 - - 3 6
Range 8 to 11 - - 2.5 6
10 % of final
- - 0.25 0.5
frequency
MSI oscillator PLL mode 5 % of final
tSTAB(MSI)(4) - - 0.5 1.25 ms
stabilization time Range 11 frequency
1 % of final
- - - 2.5
frequency

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Table 53. MSI oscillator characteristics(1) (continued)

Symbol Parameter Conditions Min Typ Max Unit

Range 0 - - 0.6 1
Range 1 - - 0.8 1.2
Range 2 - - 1.2 1.7
Range 3 - - 1.9 2.5
Range 4 - - 4.7 6
MSI oscillator Range 5 - - 6.5 9
MSI and
IDD(MSI)(4) power µA
PLL mode Range 6 - - 11 15
consumption
Range 7 - - 18.5 25
Range 8 - - 62 80
Range 9 - - 85 110
Range 10 - - 110 130
Range 11 - - 155 190
1. Guaranteed by characterization results.
2. This is a deviation for an individual part once the initial frequency has been measured.
3. Sampling mode means Low-power run/Low-power sleep modes with Temperature sensor disable.
4. Guaranteed by design.

Figure 18. Typical current consumption vs. MSI frequency

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High-speed internal 48 MHz (HSI48) RC oscillator

Table 54. HSI48 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

fHSI48 HSI48 frequency VDD = 3.0 V, TA = 30 °C - 48 - MHz

(2) (2)
TRIM HSI48 user trimming step - - 0.11 0.18
USER TRIM
HSI48 user trimming coverage ±32 steps ±3(3) ±3.5(3) -
COVERAGE
DuCy(HSI48) Duty cycle - 45(2) - 55(2)
VDD = 3.0 V to 3.6 V,
Accuracy of the HSI48 oscillator - - ±3(3) %
TA = –10 to 85 °C
ACCHSI48_REL over temperature
(factory calibrated) VDD = 2 V to 3.6 V,
- - ±4.5(3)
TA = –10 to 85 °C

HSI48 oscillator frequency drift VDD = 3 V to 3.6 V - 0.025(3) 0.05(3)

DVDD(HSI48)
with VDD VDD = 2 V to 3.6 V - 0.05(3) 0.1(3)
tsu(HSI48) HSI48 oscillator start-up time - - 2.5(2) 6(2) μs
IDD(HSI48) HSI48 oscillator power consumption - - 340(2) 380(2) μA
Next transition jitter
NT jitter - - ±0.15(2) -
Accumulated jitter on 28 cycles(4)
ns
Paired transition jitter
PT jitter - - ±0.25(2) -
Accumulated jitter on 56 cycles(4)
1. VDD = 3 V, TA = –10 to 85 °C unless otherwise specified.
2. Guaranteed by design.
3. Guaranteed by characterization results.
4. Jitter measurement are performed without clock source activated in parallel.

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Figure 19. HSI48 frequency vs. temperature

%
6

-2

-4

-6
-10 10 30 50 70 90 °C

Avg min max

MSv63024V1

Low-speed internal (LSI) RC oscillator

Table 55. LSI1 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TA = 30 °C 31.04 - 32.96

fLSI LSI1 frequency kHz
VDD = 2 to 3.6 V, TA = -10 to 85 °C 29.5 - 34
tSU(LSI1)(2) LSI1 oscillator start-up time - - 80 130
μs
(2)
tSTAB(LSI1) LSI1 oscillator stabilization time 5% of final frequency - 125 180
LSI1 oscillator power
IDD(LSI1)(2) - - 110 180 nA
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.

Table 56. LSI2 oscillator characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

VDD = 3.0 V, TA = 30 °C 21.6 - 44.2

fLSI2 LSI2 frequency kHz
VDD = 2 to 3.6 V, TA = -10 to 85 °C 21.2 - 44.4
tSU(LSI2)(2) LSI2 oscillator start-up time - 0.7 - 3.5 ms
LSI2 oscillator power
IDD(LSI2)(2) - - 500 1180 nA
consumption
1. Guaranteed by characterization results.
2. Guaranteed by design.

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6.3.12 PLL characteristics

The parameters given in Table 57 are derived from tests performed under temperature and
VDD supply voltage conditions summarized in Table 20: General operating conditions.

Table 57. PLL characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

PLL input clock(2) - 2.66 - 16 MHz

fPLL_IN
PLL input clock duty cycle - 45 - 55 %
fPLL_P_OUT PLL multiplier output clock P - 2 - 64
fPLL_Q_OUT PLL multiplier output clock Q - 8 - 64
MHz
fPLL_R_OUT PLL multiplier output clock R - 8 - 64
fVCO_OUT PLL VCO output - 96 - 344
tLOCK PLL lock time - - 15 40 μs
RMS cycle-to-cycle jitter - 40 -
Jitter System clock 64 MHz ps
RMS period jitter - 30 -
VCO freq = 96 MHz - 200 260
PLL power consumption
IDD(PLL) VCO freq = 192 MHz - 300 380 μA
on VDD(1)
VCO freq = 344 MHz - 520 650
1. Guaranteed by design.
2. Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between the two PLLs.

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6.3.13 Flash memory characteristics

Table 58. Flash memory characteristics(1)

Symbol Parameter Conditions Typ Max Unit

tprog 64-bit programming time - 81.7 90.8 µs

One row (64 double word) Normal programming 5.2 5.5

tprog_row
programming time Fast programming 3.8 4.0

One page (4 KByte) Normal programming 41.8 43.0

tprog_page ms
programming time Fast programming 30.4 31.0
tERASE Page (4 KByte) erase time - 22.0 24.5
tME Mass erase time - 22.1 25.0
Write mode 3.4 -
IDD Average consumption from VDD mA
Erase mode 3.4 -
1. Guaranteed by design.

Table 59. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit

NEND Endurance TA = –10 to +85 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
tRET Data retention (2)
10 kcycles at TA = 55 °C 30 Years
(2)
10 kcycles at TA = 85 °C 15
1. Guaranteed by characterization results.
2. Cycling performed over the whole temperature range.

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6.3.14 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 60. They are based on the EMS levels and classes
defined in application note AN1709 “EMC design guide for STM8, STM32 and Legacy
MCUs”, available on www.st.com.

Table 60. EMS characteristics

Symbol Parameter Conditions Level/Class

VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin
VFESD fHCLK = 64 MHz, 2B
to induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be VDD = 3.3 V, TA = +25 °C,
VEFTB applied through 100 pF on VDD and VSS fHCLK = 64 MHz, 5A
pins to induce a functional disturbance conforming to IEC 61000-4-4

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flow must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (e.g. control registers)

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Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or on the oscillator pins for
1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see AN1015 “Software techniques for improving
microcontrollers EMC performance”, available on www.st.com).

Electromagnetic interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling two LEDs through the I/O ports). This emission test is compliant with the
IEC 61967-2 standard, which specifies the test board and the pin loading.

Table 61. EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32 MHz / 64 MHz, 32 MHz
Monitored Peripheral ON
Symbol Parameter Conditions Unit
frequency band SMPS OFF or ON

0.1 MHz to 30 MHz 11

VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz 5
Peak(1) UFQFPN48 package dBµV
SEMI 130 MHz to 1 GHz 0
compliant with IEC
61967-2 1 GHz to 2 GHz 8
Level(2) 0.1 MHz to 2 GHz 1.5 -
1. Refer to AN1709, “EMI radiated test” section.
2. Refer to AN1709, “EMI level classsification section.

6.3.15 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.

Table 62. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Class Unit
value(1)

Electrostatic discharge voltage TA = +25 °C, conforming to

VESD(HBM) 2 2000
(human body model) ANSI/ESDA/JEDEC JS-001
V
Electrostatic discharge voltage TA = +25 °C, conforming to
VESD(CDM) C2a 500
(charge device model) ANSI/ESD STM5.3.1 JS-002
1. Guaranteed by characterization results.

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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• a supply overvoltage is applied to each power supply pin
• a current injection is applied to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 63. Electrical sensitivities

Symbol Parameter Conditions Class

LU Static latch-up class TA = +85 °C conforming to JESD78A II

6.3.16 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3.3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of the -5 µA / 0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
The characterization results are given in Table 64.
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.

Table 64. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection

Injected current on all pins except PB0, PB1 -5 N/A(2)

IINJ mA
Injected current on PB0, PB1 pins -5 0
1. Guaranteed by characterization results.
2. Injection not possible.

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6.3.17 I/O port characteristics

For information on the GPIO configuration, refer to AN4899 STM32 microcontroller GPIO
hardware settings and low-power consumption, available on www.st.com.

General input/output characteristics

Unless otherwise specified, the parameters given in Table 65 are derived from tests
performed under the conditions summarized in Table 20: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.

Table 65. I/O static characteristics

Symbol Parameter Conditions Min Typ Max Unit

I/O input
- - 0.3 x VDD
low level voltage(1)
VIL
I/O input
0.39 x VDD - 0.06
low level voltage(2)
V
I/O input
0.7 x VDD - -
high level voltage(1) 2 V < VDD < 3.6 V
VIH
I/O input
0.49 x VDD + 0.26 - -
high level voltage(2)
TT_xx, FT_xxx
Vhys and NRST I/Os - 200 - mV
input hysteresis
0 ≤ VIN ≤ Max(VDDXXX)(3) - - ±100
Max(VDDXXX) ≤ VIN ≤
FT_xx - - 650
Max(VDDXXX) +1 V(2)(3)(4)
input leakage current
Max(VDDXXX) +1 V < VIN ≤
- - 200(7)
5.5 V(2)(3)(4)(5)(6)
0 ≤ VIN ≤ Max(VDDXXX)(3) - - ±150
Ilkg FT_lu, FT_u and Max(VDDXXX) ≤ VIN ≤ nA
- - 2500
PB2 I/Os input Max(VDDXXX) +1 V(2)(3)
leakage current
Max(VDDXXX) +1 V < VIN ≤
- - 250
5.5 V(1)(3)(4)(8)
VIN ≤ Max(VDDXXX)(3) - - ±150
TT_xx
input leakage current Max(VDDXXX) ≤ VIN < - - 2000
3.6 V(3)
Weak pull-up
RPU VIN = VSS 25 40 55
equivalent resistor(1)
kΩ
Weak pull-down
RPD VIN = VDD 25 40 55
equivalent resistor(1)
I/O pin
CIO - - 5 - pF
capacitance(9)
1. Tested in production.
2. Guaranteed by design, not tested in production.
3. Represents the pad leakage of the I/O itself. The total product pad leakage is given by
ITotal_Ileak_max = 10 μA + number of I/Os where VIN is applied on the pad x Ilkg(Max).

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4. Max(VDDXXX) is the maximum value among all the I/O supplies.

5. VIN must be lower than [Max(VDDXXX) + 3.6 V].
6. Refer to Figure 20: I/O input characteristics.
7. To sustain a voltage higher than Min(VDD, VDDA) + 0.3 V, the internal pull-up and pull-down resistors must be disabled. All
FT_xx IO except FT_lu, FT_u and PB2.
8. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS, whose
contribution to the series resistance is minimal (~10%).
9. RF I/O structure excluded.

All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 20 .

Figure 20. I/O input characteristics

Vil-Vih (all IO except BOOT0)
3

2.5

TTL requirement Vih min = 2V

2

cmos vil spec 30%

cmos vih spec 70%
Voltage

1.5 ttl vil spec ttl

ttl vih spec ttl
datasheet Vil_rule
datasheet Vih_rule
1

TTL requirement Vil min = 0.8V

0.5

0
2 2.5 3 3.5
MSv63025V1

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ± 20 mA (with a relaxed VOL / VOH).
In the user application, the number of I/O pins that can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2.
• The sum of the currents sourced by all the I/Os on VDD, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 16: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating ΣIVSS (see
Table 16: Voltage characteristics).

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Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT or TT
unless otherwise specified).

Table 66. Output voltage characteristics(1)

Symbol Parameter Conditions Min Max Unit

VOL(2) Output low level voltage for an I/O pin CMOS port (3)
- 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 0.4 -

VOL(2) Output low level voltage for an I/O pin TTL port(3) - 0.4
|IIO| = 8 mA
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V 2.4 -

VOL(2) Output low level voltage for an I/O pin |IIO| = 20 mA - 1.3
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2.7 V VDD - 1.3 - V

VOL(2) Output low level voltage for an I/O pin |IIO| = 4 mA - 0.4
VOH(2) Output high level voltage for an I/O pin VDD ≥ 2 V VDD - 0.45 -
|IIO| = 20 mA
- 0.4
Output low level voltage for an FT I/O VDD ≥ 2.7 V
VOLFM+(2)
pin in FM+ mode (FT I/O with “f” option) |I | = 10 mA
IO - 0.4
VDD ≥ 2 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified
in Table 16: Voltage characteristics, and the sum of the currents sourced or sunk by all the I/Os (I/O ports
and control pins) must always respect the absolute maximum ratings Σ IIO.
2. Guaranteed by design.
3. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Table 67.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 20: General
operating conditions.

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Table 67. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit

C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5

C = 50 pF, 2 V ≤ VDD ≤ 2.7 V - 1
Fmax Maximum frequency MHz
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 1.5
00
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25
C = 50 pF, 2 V ≤ VDD ≤ 2.7 V - 52
Tr/Tf Output rise and fall time ns
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 17
C = 10 pF, 2 V ≤ VDD ≤ ≤2.7 V - 37
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 25
C = 50 pF, 2 V ≤ VDD ≤ ≤2.7 V - 10
Fmax Maximum frequency MHz
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 15
01
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 9
C = 50 pF, 2 V ≤ VDD ≤ 2.7 V - 16
Tr/Tf Output rise and fall time ns
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.5
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 9
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 50
C = 50 pF, 2 V ≤ VDD ≤ 2.7 V - 25
Fmax Maximum frequency MHz
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 100(3)
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 37.5
10
C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.8
C = 50 pF, 2 V ≤ VDD ≤ 2.7 V - 11
Tr/Tf Output rise and fall time ns
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.5
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 5
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 120(3)
C = 30 pF, 2 V ≤ VDD ≤ 2.7 V - 50
Fmax Maximum frequency MHz
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 180(3)
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 75(3)
11
C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.3
C = 30 pF, 2 V ≤ VDD ≤ 2.7 V - 6
Tr/Tf Output rise and fall time ns
C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 1.7
C = 10 pF, 2 V ≤ VDD ≤ 2.7 V - 3.3
1. The maximum frequency is achieved with a duty cycle between 45 and 55%, when loaded by the specified
capacitance.
2. The fall and rise time are defined, respectively, between 90 and 10%, and between 10 and 90% of the
output waveform.

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3. This value represents the I/O capability but the maximum system frequency is limited to 64 MHz.

6.3.18 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pull-up resistor, RPU.
Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 20: General operating conditions.

Table 68. NRST pin characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

NRST input
VIL(NRST) - - - 0.3 x VDD
low level voltage
V
NRST input
VIH(NRST) - 0.7 x VDD - -
high level voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input
VF(NRST) - - - 70
filtered pulse
ns
NRST input
VNF(NRST) 2 V ≤ VDD ≤ 3.6 V 350 - -
not filtered pulse
1. Guaranteed by design.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10%).

Figure 21. Recommended NRST pin protection

External
reset circuit(1) VDD

RPU
NRST(2) Internal reset
Filter

0.1 μF(3)

MS19878V3

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 68, otherwise the reset will not be taken into account by the device.
3. The external capacitor on NRST must be placed as close as possible to the device.

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6.3.19 Analog switches booster

Table 69. Analog switches booster characteristics(1)

Symbol Parameter Min Typ Max Unit

VDD Supply voltage 2 - 3.6 V

tSU(BOOST) Booster startup time - - 240 µs
Booster consumption for
- - 500
2.0 V ≤ VDD ≤ 2.7 V
IDD(BOOST) µA
Booster consumption for
- - 900
2.7 V ≤ VDD ≤ 3.6 V
1. Guaranteed by design.

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6.3.20 Analog-to-Digital converter characteristics

Unless otherwise specified, the parameters given in Table 70 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 20: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.

Table 70. ADC characteristics(1) (2)

Symbol Parameter Conditions Min Typ Max Unit

VDDA Analog supply voltage - 2 - 3.6 V

fADC ADC clock frequency - - - 32 MHz
Resolution = 12 bits - - 2.13
Resolution = 10 bits - - 2.46
fs Sampling rate Msps
Resolution = 8 bits - - 2.91
Resolution = 6 bits - - 3.55
fADC = 32 MHz
External trigger - - 2.13 MHz
fTRIG Resolution = 12 bits
frequency
Resolution = 12 bits - - 15 1 / fADC
(VREF++ (VREF++
(VREF++
VCMIN Input common mode Differential mode VREF-) / 2 VREF-) / 2
VREF-) / 2
- 0.18 + 0.18 V
Conversion voltage
VAIN (3) - 0 - VREF+
range(2)
External input
RAIN - - - 50 kΩ
impedance
Internal sample and hold
CADC - - 5 - pF
capacitor
Conversion
tSTAB Power-up time - 1
cycle
fADC = 32 MHz 3.625 µs
tCAL Calibration time
- 116 1 / fADC

Trigger conversion CKMODE = 00 1.5 2 2.5

latency CKMODE = 01 - - 2.0
tLATR Regular and injected
channels without CKMODE = 10 - - 2.25
conversion abort CKMODE = 11 - - 2.125
1 / fADC
Trigger conversion CKMODE = 00 2.5 3 3.5
latency CKMODE = 01 - - 3.0
tLATRINJ Injected channels
aborting a regular CKMODE = 10 - - 3.25
conversion CKMODE = 11 - - 3.125
fADC = 32 MHz 0.078 - 20.0 µs
ts Sampling time
- 2.5 - 640.5 1 / fADC

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Table 70. ADC characteristics(1) (2) (continued)

Symbol Parameter Conditions Min Typ Max Unit

ADC voltage regulator

tADCVREG_STUP - - - 20 µs
start-up time
fADC = 32 MHz
0.469 - 20.41 µs
Total conversion time Resolution = 12 bits
tCONV
(including sampling time) ts + 12.5 cycles for successive
Resolution = 12 bits 1 / fADC
approximations = 15 to 653
fs = 2.13 Msps - 340 415
ADC consumption from
IDDA(ADC) fs = 1 Msps - 160 220
the VDDA supply
fs = 10 ksps - 16 50
fs = 2.13 Msps - 64 80
ADC consumption from
IDDV_S(ADC) the VREF+ single ended fs = 1 Msps - 30 40 µA
mode
fs = 10 ksps - 0.6 2
fs = 2.13 Msps - 128 155
ADC consumption from
IDDV_D(ADC) the VREF+ differential fs = 1 Msps - 60 70
mode
fs = 10 ksps - 1.3 3
1. Guaranteed by design
2. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the SYSCFG_CFGR1 when
VDDA < 2.4V). It is disable when VDDA ≥ 2.4 V.
3. VREF+ is internally connected to VDDA and VREF- is internally connected to VSS.

Table 71. ADC sampling time(1)(2)

RAIN
Resolution (bits) Minimum sampling time (ns) Sampling cycles
(kΩ)

0 57 2.5
0.05 62 2.5
0.1 67 2.5
0.2 76 2.5
0.5 104 6.5
12 1 151 6.5
5 526 24.5
10 994 47.5
20 1932 92.5
50 4744 247.5
100 9430 640.5

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Table 71. ADC sampling time(1)(2) (continued)

RAIN
Resolution (bits) Minimum sampling time (ns) Sampling cycles
(kΩ)

0 47 2.5
0.05 51 2.5
0.1 55 2.5
0.2 62 2.5
0.5 85 6.5
10 1 124 6.5
5 431 24.5
10 816 47.5
20 1584 92.5
50 3891 247.5
100 7734 247.5
0 37 2.5
0.05 40 2.5
0.1 43 2.5
0.2 49 2.5
0.5 67 2.5
8 1 97 6.5
5 337 12.5
10 637 24.5
20 1237 47.5
50 3037 247.5
100 6038 247.5
1. Guaranteed by design.
2. VDD = 2 V, Cpcb = 4.7 pF, 105 °C, booster enabled.

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Table 72. ADC accuracy - Limited test conditions 1(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Total Single ended - 4 5

ET unadjusted
error Differential - 3.5 4.5

Single ended - 1 2.5

EO Offset error
Differential - 1.5 2.5
Single ended - 2.5 4.5

ADC clock frequency ≤ 32 MHz,

EG Gain error LSB

Sampling rate ≤ 2.13 Msps,

Differential - 2.5 3.5

Differential Single ended - 1 1.5

VDDA = 3 V,
ED

TA = 25 °C
linearity error Differential - 1 1.2

Integral Single ended - 1.5 2.5

EL
linearity error Differential - 1 2

Effective Single ended 10.4 10.5 -

ENOB bits
number of bits Differential 10.8 10.9 -
Signal-to-noise Single ended 64.4 65 -
SINAD and distortion
ratio Differential 66.8 67.4 -
dB
Signal-to-noise Single ended 65 66 -
SNR
ratio Differential 67 68 -
ADC clock frequency ≤ 32 MHz,
Sampling rate ≤ 2.13 Msps,

Single ended - -74 -73

VDDA = 3 V,
TA = 25 °C

Total harmonic
THD dB
distortion

Differential - -79 -76

1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative injection current: Injecting negative current on any analog input pins must be
avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins that may potentially inject
negative current.
4. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling.

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Table 73. ADC accuracy - Limited test conditions 2(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Total Single ended - 4 6.5

ET unadjusted
error Differential - 3.5 5.5

Single ended - 1 5
EO Offset error
Differential - 1.5 3
Single ended - 2.5 6

ADC clock frequency ≤ 32 MHz,

EG Gain error LSB

Sampling rate ≤ 2.13 Msps,

Differential - 2.5 3.5

Differential Single ended - 1 1.5

ED

VDDA ≥ 2 V
TA = 25 °C
linearity error Differential - 1 1.2

Integral Single ended - 1.5 3.5

EL
linearity error Differential - 1 2.5

Effective Single ended 10 10.5 -

ENOB bits
number of bits Differential 10.7 10.9 -
Signal-to-noise Single ended 62 65 -
SINAD and distortion
ratio Differential 66 67.4 -
dB
Signal-to-noise Single ended 64 66 -
SNR
ratio Differential 66.5 68 -
ADC clock frequency ≤ 32 MHz,
Sampling rate ≤ 2.13 Msps,

Single ended - -74 -67

VDDA ≥ 2 V
TA = 25 °C

Total harmonic
THD dB
distortion

Differential - -79 -71

1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative injection current: Injecting negative current on any analog input pins must be
avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins that may potentially inject
negative current.
4. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling.

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Table 74. ADC accuracy - Limited test conditions 3(1)(2)(3)

Symbol Parameter Conditions(4) Min Typ Max Unit

Total Single ended - 4.5 6.5

ET unadjusted
error Differential - 4.5 5.5

Single ended - 2.5 5

EO Offset error
Differential - 2.5 3
Single ended - 3.5 6

ADC clock frequency ≤ 32 MHz,

EG Gain error LSB

2 V ≤ VDDA = VREF+ ≤ 3.6 V,

Sampling rate ≤ 2.13 Msps,
Differential - 3.5 5

Differential Single ended - 1.2 1.5

ED
linearity error Differential - 1 1.2

Integral Single ended - 2.5 3.5

EL
linearity error Differential - 2 2.5

Effective Single ended 10 10.4 -

ENOB bits
number of bits Differential 10.6 10.7 -
Signal-to-noise Single ended 62 64 -
SINAD and distortion
ratio Differential 65 66 -
dB
Signal-to-noise Single ended 63 65 -
SNR
ratio Differential 66 67 -
ADC clock frequency ≤ 32 MHz,

2 V ≤ VDDA = VREF+ ≤ 3.6 V,

Sampling rate ≤ 2.13 Msps,

Single ended - -71 -67

Total harmonic
THD dB
distortion

Differential - -72 -71

1. Guaranteed by design.
2. ADC DC accuracy values are measured after internal calibration.
3. ADC accuracy vs. negative injection current: Injecting negative current on any analog input pins must be
avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins that may potentially inject
negative current.
4. The I/O analog switch voltage booster is enabled when VDDA < 2.4 V (BOOSTEN = 1 in the
SYSCFG_CFGR1 when VDDA < 2.4 V). It is disabled when VDDA ≥ 2.4 V. No oversampling.

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Figure 22. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
(1) Example of an actual transfer curve
2n-1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+

(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA

MSv19880V6

Figure 23. Typical connection diagram using the ADC

VDDA(4) VREF+(4)

I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing

VSS VSS VSSA

MSv67871V3

1. Refer to Table 70: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 65: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value downgrades conversion accuracy. To remedy this, fADC must be reduced.
3. Refer to Table 65: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 11: Power supply scheme.

General PCB design guidelines

Power supply decoupling has to be performed as shown in Figure 11: Power supply
scheme. The 10 nF capacitor needs to be ceramic (good quality), placed as close as
possible to the chip.

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6.3.21 Temperature sensor characteristics

Table 75. TS characteristics

Symbol Parameter Min Typ Max Unit

TL(1) VTS linearity with temperature - ±1 ±2 °C

(2)
Avg_Slope Average slope 2.3 2.5 2.7 mV / °C
V30 Voltage at 30 °C (±5 °C)(3) 0.742 0.760 0.785 V

tSTART (TS_BUF)(1) Sensor buffer start-up time in continuous mode(4) - 8 15

tSTART(1) Start-up time when entering in continuous mode(4) - 70 120 µs

tS_temp(1) ADC sampling time when reading the temperature 5 - -

Temperature sensor consumption from VDD, when

IDD(TS)(1) - 4.7 7 µA
selected by ADC
1. Guaranteed by design.
2. Guaranteed by characterization results.
3. Measured at VDDA = 3.0 V ± 10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte. Refer to Table 9:
Temperature sensor calibration values.
4. Continuous mode means Run/Sleep modes, or temperature sensor enable in Low-power run/Low-power sleep modes.

6.3.22 VBAT monitoring characteristics

Table 76. VBAT monitoring characteristics(1)

Symbol Parameter Min Typ Max Unit

R Resistor bridge for VBAT - 3 x 39 - kΩ

Q Ratio on VBAT measurement - 3 - -
(2)
Er Error on Q -10 - 10 %
tS_vbat(2) ADC sampling time when reading VBAT 12 - - µs
1. 1.55 V < VBAT < 3.6 V.
2. Guaranteed by design.

Table 77. VBAT charging characteristics

Symbol Parameter Conditions Min Typ Max Unit

VBRS = 0 - 5 -
RBC Battery charging resistor kΩ
VBRS = 1 - 1.5 -

6.3.23 Timer characteristics

The parameters given in the following tables are guaranteed by design. Refer to
Section 6.3.17 for details on the input/output alternate function characteristics (output
compare, input capture, external clock, PWM output).

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Table 78. TIMx(1) characteristics

Symbol Parameter Conditions Min Max Unit

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 64 MHz 15.625 - ns

Timer external clock frequency - 0 fTIMxCLK/2

fEXT MHz
on CH1 to CH4 fTIMxCLK = 64 MHz 0 40
TIM1, TIM16, TIM17 - 16
ResTIM Timer resolution bit
TIM2 - 32
- 1 65536 tTIMxCLK
tCOUNTER 16-bit counter clock period
fTIMxCLK = 64 MHz 0.015625 1024 µs

Maximum possible count with - - 65536 × 65536 tTIMxCLK

tMAX_COUNT
32-bit counter fTIMxCLK = 64 MHz - 67.10 s
1. TIMx, is used as a general term where x stands for 1, 2, 16 or 17.

Table 79. IWDG min/max timeout period at 32 kHz (LSI1)(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0] = 0x000 Max timeout RL[11:0] = 0xFFF Unit

/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings still depend on the phasing of the APB interface clock vs. the LSI clock, hence there is always a full RC
period of uncertainty.

6.3.24 Communication interfaces characteristics

I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): bit rate up to 100 kbit/s
• Fast-mode (Fm): bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): bit rate up to 1 Mbit/s.

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Table 80. Minimum I2CCLK frequency in all I2C modes

Symbol Parameter Condition Min Unit

Standard-mode - 2
Analog filter ON, DNF = 0 9
I2CCLK Fast-mode
f(I2CCLK) Analog filter OFF, DNF = 1 9 MHz
frequency
Analog filter ON, DNF = 0 19
Fast-mode Plus
Analog filter OFF, DNF = 1 16

The I2C timings requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual RM0471).
The SDA and SCL I/O requirements are met with the following restriction: the SDA and SCL
I/O pins are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present. The 20 mA output drive
requirement in Fast-mode Plus is supported partially.
This limits the maximum load Cload supported in Fast-mode Plus, given by these formulas:
• tr(SDA/SCL) = 0.8473 x Rp x Cload
• Rp(min) = [VDD - VOL(max)] / IOL(max)
where Rp is the I2C lines pull-up. Refer to Section 6.3.17 for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter, refer to Table 81 for its characteristics.

Table 81. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit

Maximum pulse width of spikes that

tAF 50(2) 110(3) ns
are suppressed by the analog filter
1. Guaranteed by design.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered.

SPI characteristics
Unless otherwise specified, the parameters given in Table 82 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 20: General operating conditions.
• Output speed is set to OSPEEDRy[1:0] = 11
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD
Refer to Section 6.3.17 for more details on the input/output alternate function characteristics
(NSS, SCK, MOSI, MISO for SPI).

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Table 82. SPI characteristics(1)

Symbol Parameter Conditions Min Typ Max Unit

Master mode
32
2.0 < VDD < 3.6 V
Master transmitter mode
32
2.0 < VDD < 3.6 V
fSCK Slave receiver mode
SPI clock frequency - - 32 MHz
1/tc(SCK) 2.0 < VDD < 3.6 V
Slave mode transmitter/full duplex
32(2)
2.7 < VDD < 3.6 V
Slave mode transmitter/full duplex
20.5(2)
2.0 < VDD < 3.6 V
tsu(NSS) NSS setup time Slave mode, SPI prescaler = 2 4 x TPCLK - -
th(NSS) NSS hold time Slave mode, SPI prescaler = 2 2 x TPCLK - -
-
tw(SCKH)
SCK high and low time Master mode TPCLK - 1.5 TPCLK TPCLK + 1
tw(SCKL)
tsu(MI) Master mode 1.5 - -
Data input setup time
tsu(SI) Slave mode 1 - -
th(MI) Master mode 5 - -
Data input hold time ns
th(SI) Slave mode 1 - -
ta(SO) Data output access time 9 - 34
Slave mode
tdis(SO) Data output disable time 9 - 16
Slave mode 2.7 < VDD < 3.6 V - 14.5 15.5
tv(SO)
Data output valid time Slave mode 2.0 < VDD < 3.6 V - 15.5 24
tv(MO) Master mode (after enable edge) - 2.5 3 ns
th(SO) Slave mode (after enable edge) 8 - -
Data output hold time
th(MO) Master mode (after enable edge) 1 - -
1. Guaranteed by characterization results.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI), which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50 %.

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Figure 24. SPI timing diagram - Slave mode and CPHA = 0

NSS input
SCK input

MISO MSB OUT BIT6 OUT LSB OUT

OUTPUT
(SI)

MOSI
MSB IN BIT1 IN LSB IN
INPUT
(SI)

Figure 25. SPI timing diagram - Slave mode and CPHA = 1

NSS input

tSU(NSS) tc(SCK) th(NSS)

SCK input

CPHA=1
CPOL=0 tw(SCKH)
CPHA=1 tw(SCKL)
CPOL=1

tr(SCK)
tv(SO) th(SO) tdis(SO)
ta(SO) tf(SCK)
MISO
MSB OUT BIT6 OUT LSB OUT
OUTPUT
tsu(SI) th(SI)
MOSI
INPUT MSB IN BIT 1 IN LSB IN

ai14135b

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

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Figure 26. SPI timing diagram - master mode

High
NSS input
tc(SCK)
SCK Output

CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output

CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT

tv(MO) th(MO)

ai14136c

1. Measurement points are set at CMOS levels: 0.3 VDD and 0.7 VDD.

JTAG/SWD interface characteristics

Unless otherwise specified, the parameters given in Table 83 and Table 84 are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 20: General operating conditions. with the following
configuration:
• Capacitive load C = 30 pF
• Measurement points are done at CMOS levels: 0.5 ₓ VDD

Table 83. JTAG characteristics

Symbol Parameter Conditions Min Typ Max Unit

2.7 < VDD < 3.6 V - - 29

1/tc(TCK) TCK clock frequency MHz
2.0 < VDD < 3.6 V - - 21
tisu(TMS) TMS input setup time - 2.5 - -
tih(TMS) TMS input hold time - 2 - -
tisu(TDI) TDI input setup time - 1.5 - -
tih(TDI) TDI input hold time - 2 - - ns
2.7 < VDD < 3.6 V - 13.5 16.5
tov(TDO) TDO output valid time
2.0 < VDD < 3.6 V - 13.5 23
toh(TDO) TDO output hold time - 11 - -

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Table 84. SWD characteristics

Symbol Parameter Conditions Min Typ Max Unit

2.7 < VDD < 3.6 V - - 55

1/tc(SWCLK) SWCLK clock frequency MHz
2.0 < VDD < 3.6 V - - 35
tisu(TMS) SWDIO input setup time - 2.5 - -
tih(TMS) SWDIO input hold time - 2 - -
2.7 < VDD < 3.6 V - 16 18 ns
tov(TDO) SWDIO output valid time
2.0 < VDD < 3.6 V - 16 28
toh(TDO) SWDIO output hold time - 13 - -

Refer to Section 6.3.17 for more details on the input/output alternate function characteristics
(CK, SD, WS).

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7 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

7.1 Device marking

Refer to “Reference device marking schematics for STM32 microcontrollers and
microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1 as
well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.

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7.2 UFQFPN48 package information

UFQFPN48 is a 7 x 7mm, 0.5 mm pitch, ultra thin fine pitch quad flat package.

Figure 27. UFQFPN48 outline

Pin 1 identifier
laser marking area
D

A
E E
T Seating
plane
ddd A1
e b

Detail Y
D
Y

Exposed pad
area D2
1

L
48
C 0.500x45°
pin1 corner R 0.125 typ.

E2 Detail Z

48
Z
A0B9_ME_V3

1. Drawing is not to scale.

2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life.
3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and
solder this back-side pad to PCB ground.

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Table 85. UFQFPN48 mechanical data

millimeters inches(1)
Symbol
Min Typ Max Min Typ Max

A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
D 6.900 7.000 7.100 0.2717 0.2756 0.2795
E 6.900 7.000 7.100 0.2717 0.2756 0.2795
D2 5.500 5.600 5.700 0.2165 0.2205 0.2244
E2 5.500 5.600 5.700 0.2165 0.2205 0.2244
L 0.300 0.400 0.500 0.0118 0.0157 0.0197
T - 0.152 - - 0.0060 -
b 0.200 0.250 0.300 0.0079 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.

Figure 28. UFQFPN48 recommended footprint

7.30

6.20

48 37

1 36

0.20 5.60

7.30
5.80
6.20

5.60
0.30

12 25

13 24

0.50 0.75
0.55
5.80
A0B9_FP_V2

1. Dimensions are expressed in millimeters.

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7.3 Thermal characteristics

The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 24: General operating conditions.
The maximum chip-junction temperature, TJ max, in degrees Celsius, can be calculated
using the equation:
TJ max = TA max + (PD max x ΘJA)
where:
• TA max is the maximum ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/O max),
• PINT max is the product of IDD and VDD, expressed in Watt. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins:
• PI/O max = Σ (VOL × IOL) + Σ ((VDD – VOH) × IOH)
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Note: As the radiated RF power is quite low (< 4 mW), it is not necessary to remove it from the
chip power consumption.

Table 86. Package thermal characteristics

Symbol Parameter Value Unit

Thermal resistance junction-ambient

ΘJA 24.9
UFQFPN48 - 7 mm x 7 mm
Thermal resistance junction-board
ΘJB 13.0 °C/W
UFQFPN48 - 7 mm x 7 mm
Thermal resistance junction-case
ΘJC 1.3
UFQFPN48 - 7 mm x 7 mm

7.3.1 Reference document

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org

7.3.2 Selecting the product temperature range

When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the device at maximum dissipation, it is useful to
calculate the exact power consumption and junction temperature to determine which
temperature range will be best suited to the application.
The following example shows how to calculate the temperature range needed for a given
application.

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Example: High-performance application

Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL = 0.4 V and maximum eight I/Os used at the same time in
output at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V = 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW:
PDmax = 175 + 272 = 447 mW
Using the values obtained in Table 86 TJmax is calculated as follows:
– For UFQFPN48, 24.9 °C/W
TJmax = 82 °C + (24.9 °C/W × 447 mW) = 82 °C + 22 °C = 93 °C
This is within the range of the suffix 5 version parts (–10 < TJ < 105 °C), see Section 8.
In this case, parts must be ordered at least with the temperature range suffix 5 (see
Section 8).

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8 Ordering information

Example: STM32 WB 50 C G U 5 A TR

Device family
STM32 = Arm® based 32-bit microcontroller

Product type
WB = Wireless Bluetooth®

Device subfamily
50 = Die 5, full set of features
30 = Die 3, full set of features

Pin count
C = 48 pins

Flash memory size

G = 1 Mbytes
E = 512 Kbytes

Package
U = UFQFPN48 7 x 7 mm

Temperature range
5 = Industrial temperature range, -10 to 85 °C (105 °C junction)

Identification code
A = proprietary identification code
blank = non-proprietary identification code

Packing
TR = tape and reel
xxx = programmed parts

For a list of available options (speed, package, etc.) or for further information on any aspect
of this device contact your nearest ST sales office.

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9 Important security notice

The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.

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10 Revision history

Table 87. Document revision history

Date Revision Changes

08-Jul-2019 1 Initial release.

Updated Section 2: Description, I/O system current consumption and
Example: High-performance application.
Updated Table 1: STM32WB50CG and STM32WB30CE device features
and peripheral counts, Table 5: Features over all modes, Table 20:
General operating conditions, Table 21: RF transmitter BLE
characteristics, Table 39: Current consumption in Stop 0 mode, Table 43:
18-Feb-2020 2 Current under Reset condition, Table 56: LSI2 oscillator characteristics,
Table 82: SPI characteristics and Table 86: Package thermal
characteristics.
Updated Figure 1: STM32WB50CGxx block diagram, Figure 6: Power
supply overview, Figure 7: Clock tree and Figure 11: Power supply
scheme.
Added JTAG/SWD interface characteristics and footnote 3 to Table 13.
Updated Table 1: STM32WB50CG and STM32WB30CE device features
and peripheral counts.
Updated Figure 8: STM32WB50CG and STM32WB30CE UFQFPN48
13-Mar-2020 3 pinout(1)(2).
Updated Table 48: HSE crystal requirements.
Removed former footnote 3 from Table 13.
Minor text edits across the whole document.

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Table 87. Document revision history (continued)

Date Revision Changes

Added STM32WB30CE device.

Updated Features, Section 2: Description, Section 3.3.4: Embedded
SRAM, Section 3.6.5: Typical RF application schematic, Section 6.3.10:
External clock source characteristics, Section 7.2: UFQFPN48 package
information and Section 8: Ordering information.
Updated Table 1: STM32WB50CG and STM32WB30CE device features
and peripheral counts, footnote of Table 3: RF pin list, Table 14:
STM32WB50CG and STM32WB30CE pin and ball definitions and its
footnotes, Table 15: Alternate functions, footnote 1 of Table 16: Voltage
characteristics, footnote 1 of Table 17: Current characteristics, Table 20:
General operating conditions, Table 22: RF transmitter BLE
characteristics (1 Mbps), Table 23: RF receiver BLE characteristics (1
03-Jul-2020 4 Mbps), Table 26: RF receiver 802.15.4 characteristics, footnote 3 of
Table 48: HSE crystal requirements, Table 58: Flash memory
characteristics and Table 86: Package thermal characteristics.
Added footnotes to Table 19: Main performance at VDD = 3.3 V,
Table 24: RF BLE power consumption for VDD = 3.3 V, Table 27: RF
802.15.4 power consumption for VDD = 3.3 V and Table 76: VBAT
monitoring characteristics.
Updated Figure 6: Power supply overview, Figure 11: Power supply
scheme and Figure 22: ADC accuracy characteristics.
Added Figure 2: STM32WB30CExx block diagram and Figure 30:
STM32WB30CE UFQFPN48 marking example (package top view).
Added Table 49: HSE clock source characteristics.
Minor text edits across the whole document.
Updated document title, Features, Section 1: Introduction, Section 2:
Description, Section 3.3.4: Embedded SRAM, Section 3.6: RF
subsystem, Section 3.6.2: Bluetooth Low Energy general description,
Section 3.7.3: Power supply supervisor, Section 3.14: Analog to digital
converter (ADC), Section 6.1.2: Typical values, Section 6.3.10: External
clock source characteristics, Section 7.2: UFQFPN48 package
information and Section 8: Ordering information.
Updated Table 1: STM32WB50CG and STM32WB30CE device features
and peripheral counts, Table 3: RF pin list, Table 5: Features over all
modes, Table 6: STM32WB50CG and STM32WB30CE modes overview,
13-Apr-2021 5
Table 14: STM32WB50CG and STM32WB30CE pin and ball definitions,
Table 15: Alternate functions, Table 19: Main performance at VDD = 3.3
V, Table 29: Embedded reset and power control block characteristics,
Table 44: Peripheral current consumption, Table 49: HSE clock source
characteristics, footnote 2 of Table 51: Low-speed external user clock
characteristics and Table 76: VBAT monitoring characteristics.
Added Table 47: Wake-up time using USART.
Updated Figure 3: STM32WB50CG and STM32WB30CE RF front-end
block diagram, Figure 7: Clock tree and Figure 22: ADC accuracy
characteristics.
Updated Features, Section 3.6.2: Bluetooth Low Energy general
description and Section 3.10: Clocks and startup.
13-Jan-2022 6 Updated Table 20: General operating conditions.
Updated Figure 22: ADC accuracy characteristics, Figure 23: Typical
connection diagram using the ADC and its footnotes.

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Table 87. Document revision history (continued)

Date Revision Changes

Updated document title, Features, Section 2: Description, Section 3.6:

RF subsystem, Section 3.6.2: Bluetooth Low Energy general description
and Section 7.3: Thermal characteristics.
Updated footnote 2 of Table 19: Main performance at VDD = 3.3 V,
footnotes of Table 48: HSE crystal requirements, and added footnote to
Table 50: HSE oscillator characteristics.
Updated Table 61: EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32
08-Jun-2022 7 MHz / 64 MHz, 32 MHz, Table 65: I/O static characteristics and its
footnote 7.
Updated Figure 7: Clock tree, Figure 24: SPI timing diagram - Slave
mode and CPHA = 0, Figure 25: SPI timing diagram - Slave mode and
CPHA = 1, and Figure 29: STM32WB50CG UFQFPN48 marking
example (package top view).
Added Section 9: Important security notice.
Minor text edits across the whole document.
Updated Features, Section 6.2: Absolute maximum ratings, I/O system
current consumption, and Section 6.3.17: I/O port characteristics.
Updated footnote 2 of Table 5: Features over all modes, footnote 1 of
Table 48: HSE crystal requirements, and footnote 1 of Table 67: I/O AC
04-Apr-2023 8 characteristics.
Added footnote to Table 65: I/O static characteristics.
Updated Table 61: EMI characteristics for fHSE / fCPUM4, fCPUM0 = 32
MHz / 64 MHz, 32 MHz.
Minor text edits across the whole document.
Updated document title, Features, Section 2: Description, Section 3.6:
RF subsystem, Section 3.6.2: Bluetooth Low Energy general description,
and Section 3.16: Timers and watchdogs.
Updated Table 1: STM32WB50CG and STM32WB30CE device features
18-Aug-2023 9 and peripheral counts, Table 19: Main performance at VDD = 3.3 V, and
Table 51: Low-speed external user clock characteristics.
Added Section 7.1: Device marking.
Removed former Device marking for UFQFPN48.

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IMPORTANT NOTICE – PLEASE READ CAREFULLY

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