INDIAN INSTITUTE OF TECHNOLOGY TIRUPATI
Digital Systems Lab
(EE206P)
PART A: Digital Circuits on Breadboard (Using Discrete Hardware Components)
1. To understand the basic gate operations using Diode-Resistor Logic(DRL)
2. To understand basic gate operation using Resistor-Transistor Logic(RTL)
3. A) To understand basic gates operation using IC packages and verify the truth tables,
B) To realize all logic gates using NAND and NOR gates,
C) To design and set up half/full adder/subtractor using XOR gate and NAND Gates.
4. A) To know about the seven-segment display and its types,
B) To identify whether the given seven-segment display is Common Anode(CA) type or
Common Cathode(CC) type and also will verify the working condition of the same,
C) To set up and test a 7-segment static display system to display numbers from 0 to 9 using
IC7447.
5. A)To verify the various functions of IC 74153(MUX) and IC 74139(DEMUX),
B) Half/Full Adder and Half/Full Subtractor using IC 74153 and IC 74139.
PART B: Digital System Design using Verilog HDL Language (ModelSim
Simulator-Programming)
1. A)Introduction to Verilog HDL programming language,
B) Installation of Modelsim Software (Student Version),
C)To write Verilog code for all the gates, verifying the truth table of the gates by simulating it
on ModelSim software.
2. Modeling different types of gates: (A) 2-input NAND (B) 2-input OR gate (C) 2-input NOR
gate (D) NOT gate (E) 2-input XOR gate (F) 2-input XNOR gate
3. Modeling by creating a test bench for (A) Half-adder (B) Full-adder (C) Half-subtractor (B)
Full-subtractor
4. Write a Verilog HDL code for a multiplexer, decoder, encode, comparator and Verify the
functionality of your implementation by simulating it using a test bench for all the possible
inputs.
5. Modeling a 4-bit PARALLEL ADDER and Modeling a 4-bit adder-subtractor circuit
6. Write a Verilog HDL code for the N-Bit adder and verify the functionality of your
implementation by simulating it using a test bench.
7. Write a Verilog HDL code for the N-Bit subtractor and verify the functionality of your
implementation by simulating it using a test bench.
8. Write a Verilog HDL code for the N-bit comparator and Verify the functionality
of your implementation by simulating it using a test bench.
9. Write a single Verilog HDL code that can perform N-bit addition, N-bit subtraction and N-bit
comparison. Also, verify the functionality of your implementation by simulating it using a test
bench.
10. Simulation & Verifying the functionality of Sequential circuits by writing test bench
A) SR, JK, D and T Flip Flops
B) Counters, moore and mealy models designs…etc
11. Advanced Digital Systems Verilog Programming on….
A) Summation, B) Factorial C)InnoProduct D)Swapping E) Summation with seven
Segment Display.
PART C: Synthesis and implementation of Digital Circuits on FPGA Boards (Vivado 2019.1
Software)
1. A) Installation of Vivado Software,
B)All gates implementation on ZYBO board using Vivado Software.
2. BCD To Seven segment display on EDGE ARTIX7 FPGA Board.
3. Designing of Digital Clock on FPGA Board(EDGE ARTIX7)
4. Sine Wave on a PC Monitor via the VGA DisplayPort
5. Ultrasonic Sensor Application to measure distance on FPGA
6. Implementation of the UART transmitter/Receiver to transfer the data from PC to FPGA and Vice Versa.
Note: 80% attendance is compulsory
Evaluation
● Seven Experiments 7*10= 70 Marks
3 Marks for showing output
5 Marks for Quiz/Viva
2 Marks for Report (individual & not copied)
● Surprised Quiz (3 Nos) 3*5=15 Marks
● Final/End Sem Lab Exam 15 Marks
