Morgan Kaufmann Publishers February 1, 2025

COMPUTER ORGANIZATION AND DESIGN 6th

Edition
The Hardware/Software Interface

TOPIC 01
Introduction

COMPUTER ORGANIZATION AND DESIGN 6th

Edition
The Hardware/Software Interface

Chapter 1
Computer Abstractions
and Technology

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Morgan Kaufmann Publishers February 1, 2025

§1.1 Introduction
The Computer Revolution
◼ Progress in computer technology
◼ Underpinned by domain-specific
accelerators
◼ Makes novel applications feasible
◼ Computers in automobiles
◼ Cell phones
◼ Human genome project
◼ World Wide Web
◼ Search Engines
◼ Computers are pervasive

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Classes of Computers
◼ Personal computers
◼ General purpose, variety of software
◼ Subject to cost/performance tradeoff

◼ Server computers
◼ Network based
◼ High capacity, performance, reliability
◼ Range from small servers to building sized

The web server that powered the first web pages

on the WWW. Note the sticker with the warning
to not turn it off. https://cds.cern.ch/

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Classes of Computers
◼ Supercomputers
◼ Type of server
◼ High-end scientific and
engineering calculations
◼ Highest capability but represent
a small fraction of the overall https://www.kaust.edu.sa/en/news/
kaust-s-shaheen-iii-confirmed-as-
the-middle-east-s-most-powerful-
computer market supercomputer

◼ Embedded computers Supercomputing applications

◼ Hidden as components of
systems
◼ Stringent
power/performance/cost
constraints
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The PostPC Era

cellphone - a telephone with no landline connection.

smartphone - includes web browsing, software applications and mobile OS.
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The PostPC Era

◼ Personal Mobile Device (PMD)
◼ Battery operated
◼ Connects to the Internet
◼ Hundreds of dollars
◼ Smart phones, tablets, electronic glasses
◼ Cloud computing
◼ Large collections of servers that provide services over Internet;
◼ Warehouse Scale Computers (WSC)
◼ Software as a Service (SaaS)
◼ Portion of software run on a PMD and a portion run in the Cloud
◼ Amazon and Google

https://www.ictinnovations.c
om/difference-between-
saas-iaas-and-paas

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https://data-flair.training/blogs/features-of-cloud-computing/

What You Will Learn

◼ How programs are translated into the
machine language
◼ And how the hardware executes them
◼ The hardware/software interface
◼ What determines program performance
◼ And how it can be improved
◼ How hardware designers improve
performance
◼ What is parallel processing?
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Understanding Program Performance

◼ Algorithm
◼ Determines number of operations executed
◼ Programming language, compiler, architecture
◼ Determine number of machine instructions executed
per operation
◼ Processor and memory system
◼ Determine how fast instructions are executed
◼ I/O system (including OS)
◼ Determines how fast I/O operations are executed

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§1.2 Seven Great Ideas in Computer Architecture

Seven Great Ideas

◼ Use abstraction to simplify design

◼ Make the common case fast

◼ Performance via parallelism

◼ Performance via pipelining

◼ Performance via prediction

◼ Hierarchy of memories
◼ Dependability via redundancy

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Seven Great Ideas (cont.)

Use abstraction to simplify design Make the common case fast
◼ Both computer architects and ◼ The common case is often
programmers had to invent simpler than the rare case and
techniques to make themselves hence is often easier to enhance.
more productive.
◼ This common sense advice
◼ Abstractions is a major productivity implies that you know what the
technique for hardware and common case is, which is only
software, to represent the design at possible with careful
different levels of representation. experimentation and
measurement.
◼ Lower-level details are hidden to
offer a simpler model at higher
levels.

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Seven Great Ideas (cont.)

Performance via parallelism Performance via pipelining

◼ computer architects have ◼ A particular pattern of

offered designs that get more parallelism is so prevalent in
performance by performing computer architecture
operations in parallel
◼ A way of speeding up
execution of instructions

◼ Key idea: overlap execution

of multiple instructions

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Seven Great Ideas (cont.)

Performance via prediction Hierarchy of memories
◼ In some cases it can be faster ◼ Programmers want memory to
on average to guess and start be fast, large, and cheap.
working rather than wait until
you know for sure, assuming ◼ There are conflicting demands to
that the mechanism to recover memory speed, capacity, cost
from a misprediction is not too
expensive and your prediction
is relatively accurate. ◼ Hierarchy of memories, with the
fastest, smallest, and most
expensive memory per bit at the
top of the hierarchy and the
slowest, largest, and cheapest
per bit at the bottom.

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Seven Great Ideas (cont.)

◼ Dependability via redundancy

◼ Computers not only need to be fast; they need to be dependable.

◼ Since any physical device can fail, we make systems dependable
by including redundant components
◼ These extra components can take over when a failure occurs
and to help detect failures.

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§1.3 Below Your Program

Below Your Program
◼ Application software
◼ Written in high-level language
◼ System software
◼ Compiler: translates HLL code to
machine code
◼ Operating System: service code
◼ Handling input/output
◼ Managing memory and storage
◼ Scheduling tasks & sharing resources
◼ Hardware
◼ Processor, memory, I/O controllers

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Levels of Program Code

◼ High-level language
◼ Level of abstraction closer
to problem domain
◼ Provides for productivity
and portability
◼ Assembly language
◼ Textual (or symbolic)
representation of
instructions
◼ Hardware representation
◼ Binary digits (bits)
◼ Encoded instructions and
data
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§1.4 Under the Covers

Components of a Computer
The BIG Picture ◼ Same components for
all kinds of computer
◼ Desktop, server,
embedded
◼ Input/output includes
◼ User-interface devices
◼ Display, keyboard, mouse
◼ Storage devices
◼ Hard disk, CD/DVD, flash
FIGURE 1.5 The organization of a computer, showing the
five classic components, input, output, memory , ◼ Network adapters
datapath, and control (last two, combined and called
the processor). ◼ For communicating with
The processor gets instructions and data from memory. other computers
Input writes data to memory , and output reads data from
memory . Control sends the signals that determine the
operations of the datapath, memory , input, and output.
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Touchscreen
◼ PostPC device
◼ Supersedes keyboard
and mouse
◼ Resistive and
Capacitive types
◼ Most tablets, smart
phones use capacitive
◼ Capacitive allows
multiple touches
simultaneously

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Opening the Box

FIGURE 1.7 Components of the Apple iPhone Xs
Max cell phone. At the left is the capacitive
multitouch screen and LCD display. Next to it is
the battery. To the far right is the metal frame that
attaches the LCD to the back of the iPhone. The
small components surrounding in the center are
what we think of as the computer; they are not
simple rectangles to fit compactly inside the case
next to the battery. Figure 1.8 shows a close-up
of the board to the left of the metal case, which is
the logic printed circuit board that contains the
processor and the memory.

FIGURE 1.8 The logic board of Apple iPhone Xs

Max in Figure 1.7. The large integrated circuit in
the middle is the Apple A12 chip, which contains
two large ARM processor cores and four little
ARM processor cores that run at 2.5 GHz, as well
as 2 GiB of main memory inside the package.
Figure 1.9shows a photograph of the processor
chip inside the A12 package. A similar-sized chip
on a symmetric board attached to the back is the
64 GiB flash memory chip for nonvolatile storage.
The other chips on the board include power
management integrated controller and audio
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Inside the Processor (CPU)

◼ Datapath
◼ The component of the processor that performs
arithmetic operations.
◼ Control
◼ The component of the processor that
commands the datapath, memory, and I/O
devices according to the instructions of the
program.
◼ Cache memory
◼ A small, fast memory (SRAM) that acts as a
buffer for a slower , larger memory .
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Inside the Processor

◼ A12 processor
FIGURE 1.9 The processor integrated circuit
inside the A12 package. The size of chip is 8.4
by 9.91 mm, and it was manufactured originally
in a 7-nm process (see Section 1.5). It has two
identical ARM big processors or cores in the
lower middle of the chip, four small cores on the
lower right of the chip, a graphical processor unit
(GPU) on the far right (see Section 6.6), and a
domain-specific accelerator for neural networks
(see Section 6.7), called the NPU, on the far left.
In the middle are second-level cache memories
(L2) for the big and small cores (see Chapter 5).
At the top and bottom of the chip are interfaces
to main memory (DDR DRAM).

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Abstractions
The BIG Picture

◼ Abstraction helps us deal with complexity

◼ Hide lower-level detail
◼ Instruction set architecture (ISA)
◼ The hardware/software interface
◼ Application binary interface
◼ The ISA plus system software interface
◼ Implementation
◼ The details underlying and interface
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A Safe Place for Data

◼ Volatile main memory
◼ Loses instructions and data when power off
◼ Non-volatile secondary memory
◼ Magnetic disk
◼ Flash memory
◼ Optical disk (CDROM, DVD)

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Networks
◼ Communication, resource sharing,
nonlocal access
◼ Local area network (LAN): Ethernet
◼ Wide area network (WAN): the Internet
◼ Wireless network: WiFi, Bluetooth

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§1.5 Technologies for Building Processors and Memory

Technology Trends
◼ Electronics
technology
continues to evolve
◼ Increased capacity
and performance
◼ Reduced cost
DRAM capacity

Year Technology Relative performance/cost

1951 Vacuum tube 1
1965 Transistor 35
1975 Integrated circuit (IC) 900
1995 Very large scale IC (VLSI) 2,400,000
2013 Ultra large scale IC 250,000,000,000

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Semiconductor Technology
◼ Silicon: A natural element that is a
semiconductor.
◼ With a special chemical process, it is
possible to add materials to silicon that
allow tiny areas to transform into one of
three devices:
◼ Conductors
◼ Insulators
◼ Switch

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Manufacturing ICs

◼ Yield: proportion of working dies per wafer

From Sand to Silicon: The Making of a Microchip | Intel
https://www.youtube.com/watch?v=_VMYPLXnd7E
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Intel® Core 10th Gen

◼ 300mm wafer, 506 chips, 10nm technology

◼ Each chip is 11.4 x 10.7 mm
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§1.6 Performance
Defining Performance
◼ Which airplane has the best performance?
Performance ~ speed,
fastest is highest cruising
speed, taking a single
passenger from one point
to another in the least time.

Performance ~ transporting
500 passengers from one
point to another. Airbus A380-
800 is the fastest

We can define computer

performance in several
different ways (response time,
throughput, elapse time, CPU
time etc).

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CPU Clocking
◼ Operation of digital hardware governed by a constant-
rate clock
Clock period

Clock (cycles)

Data transfer
and computation
Update state

◼ Clock period: duration of a clock cycle

◼ e.g., 250ps = 0.25ns = 250×10–12s
◼ Clock frequency (rate): cycles per second.
◼ Clock rate is the inverse of the clock period.
◼ e.g., 4.0GHz = 4000MHz = 4.0×109Hz
◼ 1Hz=1cycle per second
◼ Higher clock frequencies result in faster performance, but with
higher energy consumption and heat production.
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CPU Time
CPU Time = CPU Clock Cycles  Clock Cycle Time
CPU Clock Cycles
=
Clock Rate

◼ CPU time - The actual time the CPU spends computing

for a specific task, excluding time spent waiting for I/O or
running other programs.
◼ Performance improved by
◼ Reducing number of clock cycles
◼ Increasing clock rate
◼ Hardware designer must often trade off clock rate against cycle
count

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Instruction Count and CPI

The number of clock cycles required for a program can
be written as follows :
Clock Cycles = Instruction Count  Cycles per Instruction
CPU Time = Instruction Count  CPI  Clock Cycle Time
Instruction Count  CPI
=
Clock Rate
◼ Instruction Count for a program
◼ Determined by program, ISA and compiler
◼ Average cycles per instruction (CPI)
◼ Determined by CPU hardware
◼ If different instructions have different CPI
◼ Average CPI affected by instruction mix
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Performance Summary
The BIG Picture

Instructions Clock cycles Seconds

CPU Time =  
Program Instruction Clock cycle

◼ Performance depends on
◼ Algorithm: affects IC, possibly CPI
◼ Programming language: affects IC, CPI
◼ Compiler: affects IC, CPI
◼ Instruction set architecture: affects IC, CPI, Tc (Clock
Cycle Time)

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§1.8 The Sea Change: The Switch to Multiprocessors

Uniprocessor Performance

Constrained by power, instruction-level parallelism,

memory latency

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Multiprocessors
◼ Multicore microprocessors
◼ More than one processor per chip
◼ Requires explicitly parallel programming
◼ Compare with instruction level parallelism
◼ Hardware executes multiple instructions at once
◼ Hidden from the programmer
◼ Hard to do
◼ Programming for performance
◼ Load balancing
◼ Optimizing communication and synchronization

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The latest as of January 2025

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§1.12 Concluding Remarks

Concluding Remarks
◼ Cost/performance is improving
◼ Due to underlying technology development
◼ Hierarchical layers of abstraction
◼ In both hardware and software
◼ Instruction set architecture
◼ The hardware/software interface
◼ Execution time: the best performance
measure
◼ Power is a limiting factor
◼ Use parallelism to improve performance
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