Module-5

Introduction to the ARM Instruction

set
Contents
Introduction
Data processing instructions
Load –Store instruction
Software interrupt instructions
Program status register instructions
Loading constants
ARMv5E extensions
Conditional Execution
Introduction
ARM instructions process data held in registers and only
access memory with load and store instructions.
ARM instructions commonly take two or three operands.
For instance the ADD instruction below adds the two values
stored in registers r1and r2 (the source registers).
It writes the result to register r3 (the destination register).
Data processing instructions
The data processing instructions manipulate data within
registers.
They are move instructions, arithmetic instructions, logical
instructions, comparison instructions, and multiply instructions.
Most data processing instructions can process one of their
operands using the barrel shifter.
If you use the S suffix on a data processing instruction, then it
updates the flags in the cpsr.
Move and logical operations update the carry flag C, negative
flag N, and zero flag Z.
Move Instructions
It copies N into a destination register Rd, where N is a register
or immediate value.
This instruction is useful for setting initial values and
transferring data between registers. Example
Barrel Shifter
A unique and powerful feature of the ARM processor is the
ability to shift the 32-bit binary pattern in one of the source
registers left or right by a specific number of positions before it
enters the ALU.
This shift increases the power and flexibility of many data
processing operations.
Pre-processing or shift occurs within the cycle time of the
instruction.
This is particularly useful for loading constants into a register
and achieving fast multiplication or division by a power of 2.
Barrel Shifter and ALU

Pre-processing or shift

The example multiplies register r5 by four and then

places the result into register r7.
Barrel shifter operations
Example : MOVS r0, r1, LSL #1
This example of a MOVS
instruction shifts register r1
left by one bit.
This multiplies register r1by
a value 2 (10000 0008).
As you can see, the C flag is
updated in the cpsr
because the S suffix is
present in the instruction
mnemonic.
Logical shift left by one
Arithmetic Instructions
The arithmetic instructions implement addition and
subtraction of 32-bit signed and unsigned values.
Example: SUB r0, r1, r2
Example: SUBS r1, r1, #1
Example: Using the Barrel Shifter with
Arithmetic
Instructions
Logical Instructions
Logical instructions perform bitwise logical operations on the
two source registers.
Comparison Instructions
The comparison instructions are used to compare or test a
register with a 32-bit value.
They update the cpsr flag bits according to the result, but do
not affect other registers.
After the bits have been set, the information can then be used
to change program flow by using conditional execution.
You do not need to apply the S suffix for comparison
instructions to update the flags.
Comparison Instructions

The CMP is effectively a subtract instruction with the result discarded;

similarly the TST instruction is a logical AND operation, and TEQ is a logical
exclusive OR operation.
For each, the results are discarded but the condition bits are updated in the
cpsr.
It is important to understand that comparison instructions only modify the
condition flags of the cpsr and do not affect the registers being compared.
Multiply Instructions
The multiply instructions multiply the contents of a pair of
registers and, depending upon the instruction, accumulate the
results in with another register.
The long multiplies accumulate onto a pair of registers
representing a 64-bit value.
The final result is placed in a destination register or a pair of
registers.
Multiply Instructions
The long multiply instructions (SMLAL, SMULL, UMLAL, and
UMULL) produce a 64-bit result.
The result is too large to fit a single 32-bit register so the result
is placed in two registers labelled RdLo and RdHi.
RdLo holds the lower 32 bits of the 64-bit result, and RdHi holds
the higher 32 bits of the 64-bit result.
Branch Instructions
A branch instruction changes the flow of execution or is used
to call a routine.
This type of instruction allows programs to have subroutines, if-
then-else structures, and loops.
The change of execution flow forces the program counter pc
to point to a new address.
The address label is stored in the instruction as a signed pc-
relative offset and must be within approximately 32 MB of the
branch instruction.
Branch Instructions
Examples of branch instructions
The forward branch skips three instructions.
The backward branch creates an infinite loop.
Branches are used to change execution flow.
Most assemblers hide the details of a branch
instruction encoding by using labels.
In this example, forward and backward are
the labels.
The branch labels are placed at the beginning
of the line and are used to mark an address
that can be used later by the assembler to
calculate the branch offset.
Load-Store Instructions
Load-store instructions transfer data between memory and
processor registers.
There are three types of load-store instructions: single-register
transfer, multiple-register transfer, and swap.
Single-Register Transfer
These instructions are used for moving a single data item in
and out of a register.
The datatypes supported are signed and unsigned words (32-
bit), half-words (16-bit), and bytes.
Single register transfer
LDR and STR instructions can load
and store data on a boundary
alignment that is the same as the
datatype size being loaded or stored.
Single-Register Load-Store Addressing
Modes
The ARM instruction set provides different modes for
addressing memory.
These modes incorporate one of the indexing methods:
preindex with writeback, preindex, and postindex
Preindex with writeback calculates an
address from a base register plus
address offset and then updates that
address base register with the new
address.
In contrast, the preindex offset is the
same as the preindex with writeback
but does not update the address
base register.
Postindex only updates the address
base register after the address is
used.
The preindex mode is useful for
accessing an element in a data
structure.
Multiple-Register Transfer
Load-store multiple instructions can transfer multiple registers
between memory and the processor in a single instruction.
The transfer occurs from a base address register Rn pointing
into memory.
Multiple-register transfer instructions are more efficient from
single-register transfers for moving blocks of data around
memory and saving and restoring context and stacks.
Load-store multiple instructions can increase interrupt latency.
ARM implementations do not usually interrupt instructions
while they are executing.
Stack Operations
The ARM architecture uses the load-store multiple instructions to
carry out stack operations.
The pop operation (removing data from a stack) uses a load
multiple instruction;
The push operation (placing data onto the stack) uses a store
multiple instruction.
Ascending (A) stacks grow towards higher memory addresses; in
contrast, descending (D) stacks grow towards lower memory
addresses.
W hen you use a full stack (F), the stack pointer sp points to an
address that is the last used or full location (i.e., sp points to the last
item on the stack).
Addressing modes for stack operations