KEMBAR78
FPGASystemDesign ModelQuestionPaper VTU2022 | PDF
Scribd
Upload
90 views2 pages

FPGASystemDesign ModelQuestionPaper VTU2022

The document is a model question paper for the subject FPGA System Design using Verilog for the 6th semester under the VTU 2022 scheme. It consists of two parts, with each part containing various questions related to FPGA architecture, programming technologies, design examples, and concepts such as floating-point representation and microprogramming. The questions require both theoretical explanations and practical Verilog coding tasks.

Uploaded by

Narasimha Murthy B
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
90 views2 pages

FPGASystemDesign ModelQuestionPaper VTU2022

The document is a model question paper for the subject FPGA System Design using Verilog for the 6th semester under the VTU 2022 scheme. It consists of two parts, with each part containing various questions related to FPGA architecture, programming technologies, design examples, and concepts such as floating-point representation and microprogramming. The questions require both theoretical explanations and practical Verilog coding tasks.

Uploaded by

Narasimha Murthy B
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Model Question Paper

Subject: FPGA System Design using Verilog (BEC613D)

6th Semester - VTU 2022 Scheme

PART - A (5 × 10 = 50 Marks)

1. a) Differentiate between PLA, PAL, CPLD, and FPGA.

b) Explain the architecture of Xilinx 9500 CPLD with a neat diagram.

2. a) Discuss the various programming technologies used in FPGAs.

b) Compare SRAM, antifuse, and flash technologies used in PLDs.

3. Design a shift-and-add binary multiplier using FSM. Write Verilog code and explain its working

with an example.

4. a) Design a traffic light controller using Verilog HDL.

b) Explain the hardware realization of FSM with control and datapath.

5. a) What is an SM chart? Explain its features with an example.

b) Convert the given SM chart to a microprogrammed control unit.

6. a) Differentiate between horizontal and vertical microprogramming.

b) Explain microinstruction formats and address sequencing.

7. a) Describe IEEE 754 single-precision floating-point format.

b) Write the steps involved in floating-point addition with an example.

8. a) Explain the algorithm for floating-point multiplication.

b) Write a Verilog module for a floating-point multiplier.

PART - B (5 × 10 = 50 Marks)

9. a) Describe the basic architecture of an FPGA with the help of logic blocks, interconnects, and I/O

blocks.

b) Write short notes on:


i) Logic Cell Array

ii) Look-Up Table

10. a) Design a serial adder using FSM.

b) Write Verilog code for a sequence detector that detects "1011".

11. a) Explain the differences between SM chart and conventional flowchart.

b) Write short notes on control memory and control signals.

12. a) Differentiate between fixed-point and floating-point representation.

b) What are rounding and normalization in floating-point operations?

13. a) Explain FPGA design flow with necessary steps.

b) Write a simple Verilog code for implementing a 4-bit ALU on FPGA.

14. a) Discuss the architecture of Xilinx Virtex FPGA.

b) What are IP cores? Explain their usage in FPGA design.

15. a) Compare CPLD and FPGA architectures.

b) Explain placement, routing, and configuration in FPGA design flow.

You might also like