Combinational Circuit vs Sequential Circuit:
Combinational Circuit is the one in which the output is only dependent on the present input.
Ex: Adder
But a sequential circuit the output depends on the present input as well as previous input.
Ex: Counter.
Clock:
It is a signal having 50% duty cycle. In a sequential circuit, there are a lot of processes going on, the output of a circuit is
Input to another circuit . We use clock to control over these circuits
• It decide the time of the input.
• We can decide the speed of the circuit by changing the frequency.
Difference between Clock and Enable?
Difference between edge triggering and level triggering?
Difference between latch and Flip-flop?
What is propagation delay and how to mitigate it?
Difference Between clock Skew and delay?
Number:
Syntex: <size>’<base><number>
1’b1 – Binary 1`/ logic 1,
8’h21 – 8 bit number 00100001
12’ha35 - 12 bit num 101000110101
4’d1 – 4 bit num 0001
Verilog:
•Supports 4 levels of abstraction
•Switch level → implementation through switches
•Gate level → logic gates
•Data flow level → Ex: Assign
•Behavioral level → behavior of the circuit
Switch level:
•Model can be implemented in terms of switches
•nmos, pmos are used as switches
not(y,a);
not(y,a);
Gate level:
•Module is implemented in terms of logic gate
•Lowest level of abstraction
•Basic logic gates are available as predefined primitives
syntex: Primitive_name instance_name (output, inputs)
and G1 (Out, A, B);
nand G2 (Y, A, B);
not(y,a);
or(y,a,b);
nor(y,a,b);
xor(y,a,b);
xnor(y,a,b);
not(y,a);
not(y,a);
module circuit_e1 (
input wire a,
input wire b,
input wire c,
input wire d,
output wire F
);
wire w1, w2, w3;
and a1 (w1, a, b);
xor x1 (w2, W1, W3);
or o1 (w3, c, d);
and a2 (f, w2, W3);
endmodule
Data Flow Level:
•Register transfer level
•Module is designed by specifying data flow
•Signals are assigned by assign
•Design is implemented using continuous assignments
•All such assignments are concurrent in nature
•Keyword assign is used
assign Z = X & Y;
assign P = Q | R;
assign z= ~y;
assign P = (~Q | R);
assign Z = ~(X & Y);
assign Z = X ^ Y;
assign Z = ~(X ^ Y);
Behavioral Level:
•Highest level of abstraction
•Describes the system by its behavior,
•function, Tasks and blocks area used
•Two important constructs are:
•initial
•always
Reg and Wire data type:
wire
•Purpose: Used to represent combinational connections between components.
•Default Type: It's the default data type for continuous assignments.
•Requires Driver: Needs a continuous assignment using assign or an output from a module or gate.
reg
•Purpose: Used to store values in procedural blocks like always blocks (typically for sequential logic).
•Not a register by default: Despite the name, it does not necessarily mean hardware register
•it's just a variable that can hold a value.
• used inside always or initial blocks.
Note:
For combinational circuits Wire data type is used cause we don’t want to store any value (like a wire connection)
For Sequential Circuit reg data type is used cause we have to save a value.
For combinational circuit “assign”, “always@(*)” is used and for equation ‘=‘ is used.
For sequential circuit “always@)(<sensitivity list>) is used and for equation ‘<=‘ is used.
4*1 MUX:
module mux4x1 (
input wire [1:0] sel, // 2-bit select input
input wire a, // Data input 0
input wire b, // Data input 1
input wire c, // Data input 2
input wire d, // Data input 3
output reg y // Output (reg type because it's assigned in always block)
);
always @(*) begin
case (sel)
2'b00: y = a;
2'b01: y = b;
2'b10: y = c;
2'b11: y = d;
default: y = 1'b0; // Optional: define a safe default
endcase
end
endmodule
D Flip-Flop:
module dff (
input wire clk,
input wire rst_n,
input wire d,
output reg q
);
always @(posedge clk, negedge rst_n)
begin
if(~rst_n)
q<=0;
else
q<=d;
end
endmodule
Counter: Synchronous reset
module counter # (
parameter COUNTER_WIDTH = 2
)(
input wire clk,
input wire reset_b,
input wire clear,
input wire increment,
output reg [COUNTER_WIDTH-1:0] count
);
always @(posedge clk or negedge reset_b) begin
if(~reset_b) begin
count <= 'b0;
end
else begin
count <= clear ? 'b0 : count + increment;
end
end
endmodule
Counter: Asynchronous reset
module counter # (
parameter COUNTER_WIDTH = 2
)(
input wire clk,
input wire reset_b,
input wire clear,
input wire increment,
output reg [COUNTER_WIDTH-1:0] count
);
always @(posedge clk) begin
if(~reset_b) begin
count <= 'b0;
end
else begin
count <= clear ? 'b0 : count + increment;
end
end
endmodule
module mux2_1(
input wire in0, module dff_w_mux (
input wire in1, input wire clk,
input wire sel, input wire rst_n,
output reg mux_out input wire sel,
); input wire in0,
always @(*)begin input wire in1,
if(sel) begin
mux_out = in1; output wire dff_w_mux_out
end );
else begin
mux_out = in0; wire mux_out;
end
end mux2_1 mux (
endmodule .mux_out(mux_out),
.sel(sel),
module dff ( .in0(in0),
input wire clk, .in1(in1)
input wire rst_n, );
input wire d,
output reg q dff d-flop (
); .clk(clk),
always @(posedge clk, negedge rst_n) .rst_n(rst_n),
begin .d(mux_out),
if(~rst_n) .q(dff_w_mux_out )
q<=0; );
else
q<=d; endmodule
end
endmodule
