KEMBAR78
Gokul D 3rd Assignment - Tessolve-Verilog | PDF | Computing | Computer Programming
Scribd
Upload
10 views2 pages

Gokul D 3rd Assignment - Tessolve-Verilog

The document outlines a Verilog assignment focused on various concepts such as parameters, arithmetic operations, inferred latches, and multiplexer design. It includes specific tasks like developing code for an ALU, understanding inferred latches, and correcting coding styles for always blocks. Additionally, it emphasizes the importance of using non-blocking assignments for sequential logic and provides links to relevant resources for further learning.

Uploaded by

gocool24072002
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
10 views2 pages

Gokul D 3rd Assignment - Tessolve-Verilog

The document outlines a Verilog assignment focused on various concepts such as parameters, arithmetic operations, inferred latches, and multiplexer design. It includes specific tasks like developing code for an ALU, understanding inferred latches, and correcting coding styles for always blocks. Additionally, it emphasizes the importance of using non-blocking assignments for sequential logic and provides links to relevant resources for further learning.

Uploaded by

gocool24072002
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 2

TEESOLVE SEMICONDUCTOR

Training
VERILOG ASSIGNMENT-3

Q.No. Questions
1) a Develop verilog code to understand the bellow concept of parameter
) and `define.
 Parameter--- https://www.edaplayground.com/x/atFp
 `define--- https://www.edaplayground.com/x/P_8K
2) a Write arithmetic and logic operations in a separate task/function,
) implement an ALU by calling those task/function.
 https://www.edaplayground.com/x/e7w8

3) a What is inferred latch and how it is created? Develop example verilog


) code with and without infer latch.

 Inferred latch--- https://www.edaplayground.com/x/8unr


 Non-inferred latch--- https://www.edaplayground.com/x/udt7
 with inferred latch--- https://www.edaplayground.com/x/Y8HS

How many flip-flops will be needed when following two codes are
b synthesized?
) i) always @(posedge clk) begin
B = A;
C = B;
end
ii) always @(posedge clk) begin
B <= A;
C <= B;
End

In first case, blocking assignments are used and hence the value of A
will be assigned to B and the new value will be reflected onto C in same
cycle and hence the variable B and C results in a wire. Sp, only one flip
flow will be needed. In second case, old value of B is sampled before
the new value is reflected in each cycle. Hence value of A reflects to C
only in 2 cycles, resulting in two flip-flops.

4) a Write a Verilog module for the 3:1 multiplexer using conditional


) operator.
 https://www.edaplayground.com/x/LmcD
5) a What will bethe value of X1 andX2 which aremodelled using following
) two always blocks. What is wrong with following coding style?
always @(posedge clk or posedge reset)
if (reset) X1= 0; // reset
else X1= X2;
always @(posedge clk or posedge reset)
if(reset) X2= 1; // set
else X2= X1;

Here's the corrected code with blocking assignments (=) and separate
sensitivity lists for clk and reset:
always @(posedge clk) begin
if (reset)
X1 <= 0; // reset
else
X1 <= X2;
end

always @(posedge clk or posedge reset) begin


if (reset)
X2 <= 1; // set
else
X2 <= X1;
end
Non-blocking assignments (<=) are used for sequential logic inside
always blocks.
Blocking assignments (=) are used for combinational logic.
Separate sensitivity lists are used for clk and reset to avoid
unintentional latches.
It's important to note that without additional information about the
surrounding code and the intended functionality, it's not possible to
determine the specific values of X1 and X2. The provided code only
describes the logic for updating their values based on clock edges and
the reset signal.
6) a How event is used to synchronous two processes? Develop a verilog
) code to understand the usage of ‘event’ data type.
 https://www.edaplayground.com/x/HeQu

You might also like