361

Computer Architecture
Lecture 9: Designing Single Cycle Control

361 control.1

Recap: The MIPS Subset

31 26 21 16 11 6 0
° ADD and subtract op rs rt rd shamt funct
• add rd, rs, rt 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
• sub rd, rs, rt
31 26 21 16 0
° OR Imm: op rs rt immediate
• ori rt, rs, imm16 6 bits 5 bits 5 bits 16 bits

° LOAD and STORE

• lw rt, rs, imm16
• sw rt, rs, imm16

° BRANCH:
• beq rs, rt, imm16

° JUMP: 31 26 0
• j target op target address
6 bits 26 bits

361 control.2

1
 Recap: A Single Cycle Datapath
° We have everything except control signals (underline)
• Today’s lecture will show you how to generate the control signals

Branch Instruction<31:0>
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Jump Fetch Unit
Rd Rt
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
busA Zero MemWr MemtoReg
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32

Mux
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc

ExtOp
361 control.3

The Big Picture: Where are We Now?

° The Five Classic Components of a Computer

Processor
Input
Control
Memory

Datapath Output

° Today’s Topic: Designing the Control for the Single Cycle Datapath

361 control.4

2
 Outline of Today’s Lecture

° Recap and Introduction

° Control for Register-Register & Or Immediate instructions

° Control signals for Load, Store, Branch, & Jump

° Building a local controller: ALU Control

° The main controller

° Summary

361 control.5

RTL: The ADD Instruction

31 26 21 16 11 6 0
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

° add rd, rs, rt

• mem[PC] Fetch the instruction from memory

• R[rd] <- R[rs] + R[rt] The actual operation

• PC <- PC + 4 Calculate the next instruction’s address

361 control.6

3
 Instruction Fetch Unit at the Beginning of Add / Subtract

° Fetch the instruction from Instruction memory: Instruction <- mem[PC]

• This is the same for all instructions

30
Addr<31:2>
PC<31:28> 30
Addr<1:0>
“00”
Target 4 1 Instruction
Instruction<25:0> 30

Mux
26 Memory
PC

0
30 0 32
Adder
30

Mux
“1”

Adder
1 Jump = previous Instruction<31:0>
Clk 30
SignExt

imm16 30
Instruction<15:0> 16

Branch = previous Zero = previous

361 control.7

The Single Cycle Datapath during Add and Subtract

31 26 21 16 11 6 0
op rs rt rd shamt funct

° R[rd] <- R[rs] + / - R[rt]

Branch = 0 Instruction<31:0>
Instruction
<21:25>

<16:20>

<11:15>

<0:15>

Jump = 0 Fetch Unit

Rd Rt
RegDst = 1 Clk
1 Mux 0
Rs Rt ALUctr = Add Rt Rs Rd Imm16
RegWr = 1 5 5 5 or Subtract
MemtoReg = 0
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU

32 0
Registers busB 0 32
Clk
Mux

32
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 0

ExtOp = x
361 control.8

4
 Instruction Fetch Unit at the End of Add and Subtract

° PC <- PC + 4
• This is the same for all instructions except: Branch and Jump

30
Addr<31:2>
PC<31:28> 30
Addr<1:0>
“00”
Target 4 1 Instruction
Instruction<25:0> 30

Mux
26 Memory
PC

0
30 0 32
Adder
30

Mux
“1”

Adder
1 Jump = 0 Instruction<31:0>
Clk 30
SignExt

imm16 30
Instruction<15:0> 16

Branch = 0 Zero = x

361 control.9

The Single Cycle Datapath during Or Immediate

31 26 21 16 0
op rs rt immediate

° R[rt] <- R[rs] or ZeroExt[Imm16]

Branch = 0 Instruction<31:0>
Instruction
<21:25>

<16:20>

<11:15>

<0:15>

Jump = 0 Fetch Unit

Rd Rt
RegDst = 0 Clk
1 Mux 0
Rs Rt ALUctr = Or Rt Rs Rd Imm16
RegWr = 1 5 5 5 MemtoReg = 0
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU

32 0
Registers busB 0 32
Clk
Mux

32
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 1

ExtOp = 0
361 control.10

5
 The Single Cycle Datapath during Or Immediate
31 26 21 16 0
op rs rt immediate

° R[rt] <- R[rs] or ZeroExt[Imm16]

Instruction<31:0>
nPC_sel= +4
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst = 0 Clk
1 Mux 0
Rs Rt ALUctr = Or Rt Rs Rd Imm16
RegWr = 1 5 5 5 MemtoReg = 0
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32

Mux
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 1

ExtOp = 0
361 control.11

The Single Cycle Datapath during Load

31 26 21 16 0
op rs rt immediate

° R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Branch = 0 Instruction<31:0>
Instruction
<21:25>

<16:20>

<11:15>

<0:15>

Jump = 0 Fetch Unit

Rd Rt
RegDst = 0 Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr = 1 5 5 5 = Add MemtoReg = 1
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU

32 0
Registers busB 0 32
Clk
Mux

32
Mux

WrEn Adr 1
Extender

1 Data In 32
imm16 Data 32
32
16 Memory
Clk
ALUSrc = 1

ExtOp = 1
361 control.12

6
 The Single Cycle Datapath during Load
31 26 21 16 0
op rs rt immediate

° R[rt] <- Data Memory {R[rs] + SignExt[imm16]}

Instruction<31:0>
nPC_sel= +4
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst = 0 Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr = 1 5 5 5 = Add MemtoReg = 1
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32

Mux WrEn Adr 1

Extender

1 Data In 32
imm16 Data 32
32
16 Memory
Clk
ALUSrc = 1

ExtOp = 1
361 control.13

The Single Cycle Datapath during Store

31 26 21 16 0
op rs rt immediate

° Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Branch = 0 Instruction<31:0>
Instruction
<21:25>

<16:20>

<11:15>

<0:15>

Jump = 0 Fetch Unit

Rd Rt
RegDst = x Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr = 0 5 5 5 = Add
MemtoReg = x
busA Zero MemWr = 1
Rw Ra Rb
busW 32
32 32-bit
ALU

32 0
Registers busB 0 32
Clk
Mux

32
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 1

ExtOp = 1
361 control.14

7
 The Single Cycle Datapath during Store
31 26 21 16 0
op rs rt immediate

° Data Memory {R[rs] + SignExt[imm16]} <- R[rt]

Instruction<31:0>
nPC_sel= +4
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Rd Rt Fetch Unit
RegDst = x Clk
1 Mux 0
Rs Rt ALUctr Rt Rs Rd Imm16
RegWr = 0 5 5 5 = Add
MemtoReg = x
busA Zero MemWr = 1
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32

Mux
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 1

ExtOp = 1
361 control.15

The Single Cycle Datapath during Branch

31 26 21 16 0
op rs rt immediate

° if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0

Branch = 1 Instruction<31:0>
Instruction
<21:25>

<16:20>

<11:15>

<0:15>

Jump = 0 Fetch Unit

Rd Rt
RegDst = x Clk
1 Mux 0
Rs Rt ALUctr = Rt Rs Rd Imm16
RegWr = 0 Subtract
5 5 5 MemtoReg = x
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit
ALU

32 0
Registers busB 0 32
Clk
Mux

32
Mux

32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = 0

ExtOp = x
361 control.16

8
 Instruction Fetch Unit at the End of Branch
31 26 21 16 0
op rs rt immediate

° if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

30
Addr<31:2>
PC<31:28> 30
Addr<1:0>
“00”
Target 4 1 Instruction
Instruction<25:0> 30

Mux
26 Memory
PC

0
30 0 32
Adder
30

Mux
“1”

Adder
1 Jump = 0 Instruction<31:0>
Clk 30
SignExt

imm16 30
Instruction<15:0> 16 Assume Zero = 1 to see
the interesting case.
Branch = 1 Zero = 1

361 control.17

Instruction Fetch Unit at the End of Branch

31 26 21 16 0
op rs rt immediate

° if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4

Inst
Memory Instruction<31:0>
Adr

nPC_sel

4
Adder

00
Mux

PC
Adder

Clk
imm16

361 control.18

9
 The Single Cycle Datapath during Jump
31 26 0
op target address

° Nothing to do! Make sure control signals are set correctly!

Branch = 0 Instruction<31:0>
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Jump = 1 Fetch Unit
Rd Rt
RegDst = x Clk
1 Mux 0
Rs Rt ALUctr = x Rt Rs Rd Imm16
RegWr = 0 5 5 5 MemtoReg = x
busA Zero MemWr = 0
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32

Mux
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
16 Memory
Clk
ALUSrc = x

ExtOp = x
361 control.19

Instruction Fetch Unit at the End of Jump

31 26 0
op target address

° PC <- PC<31:29> concat target<25:0> concat “00”

30
Addr<31:2>
PC<31:28> 30
Addr<1:0>
“00”
Target 4 1 Instruction
Instruction<25:0> 30
Mux

26 Memory
PC

0
30 0 32
Adder

30
Mux

“1”
Adder

1 Jump = 1 Instruction<31:0>
Clk 30
SignExt

imm16 30
Instruction<15:0> 16

Branch = 0 Zero = x

361 control.20

10
 Step 4: Given Datapath: RTL -> Control

Instruction<31:0>
Inst

<21:25>

<21:25>

<16:20>

<11:15>

<0:15>
Memory
Adr
Op Fun Rt Rs Rd Imm16

Control

nPC_selRegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg Equal

DATA PATH

361 control.21

A Summary of Control Signals

inst Register Transfer

ADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4
ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”
SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4
ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”
ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4
ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”
LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”,
MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”
STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4
ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”
BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4
nPC_sel = “Br”, ALUctr = “sub”

361 control.22

11
 A Summary of the Control Signals

See func 10 0000 10 0010 We Don’t Care :-)

Appendix A op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
add sub ori lw sw beq jump
RegDst 1 0 0 0 x x x
ALUSrc 0 0 1 1 1 0 x
MemtoReg 0 0 0 1 x x x
RegWrite 1 1 1 1 0 0 0
MemWrite 0 0 0 0 1 0 0
Branch 0 0 0 0 0 1 0
Jump 0 0 0 0 0 0 1
ExtOp x x 0 1 1 x x
ALUctr<2:0> Add Subtract Or Add Add Subtract xxx

31 26 21 16 11 6 0
R-type op rs rt rd shamt funct add, sub

I-type op rs rt immediate ori, lw, sw, beq

J-type op target address jump

361 control.23

The Concept of Local Decoding

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegDst 1 0 0 x x x
ALUSrc 0 1 1 1 0 x
MemtoReg 0 0 1 x x x
RegWrite 1 1 1 0 0 0
MemWrite 0 0 0 1 0 0
Branch 0 0 0 0 1 0
Jump 0 0 0 0 0 1
ExtOp x 0 1 1 x x
ALUop<N:0> “R-type” Or Add Add Subtract xxx

func
ALU ALUctr
op Main 6
ALUop Control 3
6 Control
(Local)
N
ALU

361 control.24

12
 The Encoding of ALUop
func
op 6 ALU ALUctr
Main
ALUop Control
6 Control 3
(Local)
N

° In this exercise, ALUop has to be 2 bits wide to represent:

• (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, and (4) Subtract

° To implement the full MIPS ISA, ALUop hat to be 3 bits to represent:

• (1) “R-type” instructions
• “I-type” instructions that require the ALU to perform:
- (2) Or, (3) Add, (4) Subtract, and (5) And (Example: andi)

R-type ori lw sw beq jump

ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx
361 control.25

The Decoding of the “func” Field

func
op 6 ALU ALUctr
Main
ALUop Control
6 Control 3
(Local)
N

R-type ori lw sw beq jump

ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 xxx

31 26 21 16 11 6 0
R-type op rs rt rd shamt funct

( P. 286 text)
funct<5:0> Instruction Operation ALUctr ALUctr<2:0> ALU Operation
10 0000 add 000 Add
10 0010 subtract 001 Subtract
ALU

10 0100 and 010 And

10 0101 or 110 Or
10 1010 set-on-less-than 111 Set-on-less-than
361 control.26

13
 The Truth Table for ALUctr funct<3:0> Instruction Op.
0000 add
ALUop R-type ori lw sw beq 0010 subtract
(Symbolic) “R-type” Or Add Add Subtract 0100 and
ALUop<2:0> 1 00 0 10 0 00 0 00 0 01 0101 or
1010 set-on-less-than

ALUop func ALU ALUctr

bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> Operation bit<2> bit<1> bit<0>
0 0 0 x x x x Add 0 1 0
0 x 1 x x x x Subtract 1 1 0
0 1 x x x x x Or 0 0 1
1 x x 0 0 0 0 Add 0 1 0
1 x x 0 0 1 0 Subtract 1 1 0
1 x x 0 1 0 0 And 0 0 0
1 x x 0 1 0 1 Or 0 0 1
1 x x 1 0 1 0 Set on < 1 1 1

361 control.27

The Logic Equation for ALUctr<2>

ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<2>
0 x 1 x x x x 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1
X Y Z A B C D
This makes func<3> a don’t care

° ALUctr<2> = !ALUop<2> & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>

= !X&Y + X&!A&!B&C&!D + X&A&!B&C&!D

= !X&Y + X&!B&C&!D

361 control.28

14
 The Logic Equation for ALUctr<1>

ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<1>
0 0 0 x x x x 1
0 x 1 x x x x 1
1 x x 0 0 0 0 1
1 x x 0 0 1 0 1
1 x x 1 0 1 0 1

° ALUctr<1> = !ALUop<2> & !ALUop<0> +

ALUop<2> & !func<2> & !func<0>

361 control.29

The Logic Equation for ALUctr<0>

ALUop func
bit<2> bit<1> bit<0> bit<3> bit<2> bit<1> bit<0> ALUctr<0>
0 1 x x x x x 1
1 x x 0 1 0 1 1
1 x x 1 0 1 0 1

° ALUctr<0> = !ALUop<2> & ALUop<0>

+ ALUop<2> & !func<3> & func<2> & !func<1> & func<0>
+ ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

361 control.30

15
 The ALU Control Block

func
6 ALU ALUctr
ALUop Control
3
(Local)
3

° ALUctr<2> = !ALUop<2> & ALUop<0> +

ALUop<2> & !func<2> & func<1> & !func<0>

° ALUctr<1> = !ALUop<2> & !ALUop<0> +

ALUop<2> & !func<2> & !func<0>

° ALUctr<0> = !ALUop<2> & ALUop<0>

+ ALUop<2> & !func<3> & func<2> & !func<1> & func<0>
+ ALUop<2> & func<3> & !func<2> & func<1> & !func<0>

361 control.31

Step 5: Logic for each control signal

° nPC_sel <= if (OP == BEQ) then EQUAL else 0

° ALUsrc <= if (OP == “Rtype”) then “regB” else “immed”

° ALUctr <= if (OP == “Rtype”) then funct

elseif (OP == ORi) then “OR”
elseif (OP == BEQ) then “sub”
else “add”

° ExtOp <= _____________

° MemWr <= _____________

° MemtoReg <= _____________

° RegWr: <=_____________

° RegDst: <= _____________

361 control.32

16
 Step 5: Logic for each control signal

° nPC_sel <= if (OP == BEQ) then EQUAL else 0

° ALUsrc <= if (OP == “Rtype”) then “regB” else “immed”

° ALUctr <= if (OP == “Rtype”) then funct

elseif (OP == ORi) then “OR”
elseif (OP == BEQ) then “sub”
else “add”

° ExtOp <= if (OP == ORi) then “zero” else “sign”

° MemWr <= (OP == Store)

° MemtoReg <= (OP == Load)

° RegWr: <= if ((OP == Store) || (OP == BEQ)) then 0 else 1

° RegDst: <= if ((OP == Load) || (OP == ORi)) then 0 else 1

361 control.33

The “Truth Table” for the Main Control

RegDst
func
ALUSrc ALU ALUctr
op Main 6
6 Control
: Control 3
ALUop (Local)
3
op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010
R-type ori lw sw beq jump
RegDst 1 0 0 x x x
ALUSrc 0 1 1 1 0 x
MemtoReg 0 0 1 x x x
RegWrite 1 1 1 0 0 0
MemWrite 0 0 0 1 0 0
Branch 0 0 0 0 1 0
Jump 0 0 0 0 0 1
ExtOp x 0 1 1 x x
ALUop (Symbolic) “R-type” Or Add Add Subtract xxx
ALUop <2> 1 0 0 0 0 x
ALUop <1> 0 1 0 0 0 x
ALUop <0> 0 0 0 0 1 x
361 control.34

17
 The “Truth Table” for RegWrite

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

R-type ori lw sw beq jump
RegWrite 1 1 1 x x x

° RegWrite = R-type + ori + lw

= !op<5> & !op<4> & !op<3> & !op<2> & !op<1> & !op<0> (R-type)
+ !op<5> & !op<4> & op<3> & op<2> & !op<1> & op<0> (ori)
+ op<5> & !op<4> & !op<3> & !op<2> & op<1> & op<0> (lw)
op<5> .. op<5> .. op<5> .. op<5> .. op<5> .. op<5> ..
<0> <0> <0> <0> <0> op<0>

R-type ori lw sw beq jump

RegWrite

361 control.35

PLA Implementation of the Main Control

op<5> .. op<5> .. op<5> .. op<5> .. op<5> .. op<5>..
<0> <0> <0> <0> <0> op<0>

R-type ori lw sw beq jump

RegWrite

ALUSrc
RegDst
MemtoReg
MemWrite
Branch
Jump
ExtOp
ALUop<2>
ALUop<1>
ALUop<0>
361 control.36

18
 Putting it All Together: A Single Cycle Processor
ALUop
ALU ALUctr
RegDst 3 func Control
op Main 3
ALUSrc Instr<5:0> 6
6 Control
Instr<31:26> : Branch Instruction<31:0>
Instruction

<21:25>

<16:20>

<11:15>

<0:15>
Jump Fetch Unit
Rd Rt
RegDst Clk
1 Mux 0
Rs Rt Rt Rs Rd Imm16
RegWr 5 5 5 ALUctr
busA Zero MemWr MemtoReg
Rw Ra Rb
busW 32
32 32-bit

ALU
32 0
Registers busB 0 32
Clk

Mux
32

Mux
32
WrEn Adr 1
Extender

1 Data In 32
imm16 Data
32
Instr<15:0> 16 Memory
Clk
ALUSrc

ExtOp
361 control.37

Clocking Methodology
Clk
Setup Hold Setup Hold
Don’t Care

. . . .
. . . .
. . . .

° All storage elements are clocked by the same clock edge

° Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew

° (CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time

361 control.38

19
 Worst Case Timing (Load)
Clk
Clk-to-Q
PC Old Value New Value
Instruction Memoey Access Time
Rs, Rt, Rd, Old Value New Value
Op, Func
Delay through Control Logic
ALUctr Old Value New Value

ExtOp Old Value New Value

ALUSrc Old Value New Value

MemtoReg Old Value New Value Register

Write Occurs
RegWr Old Value New Value
Register File Access Time
busA Old Value New Value
Delay through Extender & Mux
busB Old Value New Value
ALU Delay
Address Old Value New Value
Data Memory Access Time
busW Old Value New
361 control.39

Drawback of this Single Cycle Processor

° Long cycle time:

• Cycle time must be long enough for the load instruction:
PC’s Clock -to-Q +
Instruction Memory Access Time +
Register File Access Time +
ALU Delay (address calculation) +
Data Memory Access Time +
Register File Setup Time +
Clock Skew

° Cycle time is much longer than needed for all other instructions

361 control.40

20
 Summary
° Single cycle datapath => CPI=1, CCT => long

° 5 steps to design a processor

• 1. Analyze instruction set => datapath requirements
• 2. Select set of datapath components & establish clock methodology
• 3. Assemble datapath meeting the requirements
• 4. Analyze implementation of each instruction to determine setting of
control points that effects the register transfer.
• 5. Assemble the control logic
Processor
Input
° Control is the hard part Control
Memory
° MIPS makes control easier
Datapath Output
• Instructions same size
• Source registers always in same place
• Immediates same size, location
• Operations always on registers/immediates
361 control.41

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