Programmable Logic Devices

BY
Mahesh K. Yadav
Director- RPSCET
Programmable Logic Devices
• Introduction
• Comparison of Combinational & Sequential
with ASICs
• PLDs
• ROM as a PLD
• Programmable Logic Array (PAL)
• Programmable Array Logic (PAL)
• Complex Programmable Logic Devices (CPLD)
• Field Programmable Gate Array (FPGA)
• Summary
 Introduction
Comparison of Combinational & Sequential
Advantages
• Low development cost
• Fast turn around of designs and
• Relatively easy to test circuits
Disadvantages
• Large board space requirements
• Large power requirements
• Lack of security- circuits can be copied by others
• Additional cost, space, power requirements
required to modify the design or to introduce
more features
Application Specific ICs (ASICs)
Advantages
• Reduced space requirements
• Reduced power requirements
• Designs implemented in ASIC form is almost
impossible to copy
• If produced in bulk, the cost is reduced
• Large reduction in size due to high level of
integration
Disadvantages
• Initial development cost is enormous
• Testing methods have to be developed which may
increase the cost and effort
Programmable Logic Devices (PLDs)
A PLD is an IC that is user Configurable and is capable
of implementing logic functions. It is a VLSI Chip that
Contains a regular structure and allows the designer to
customize it for any specific application i.e. it is
programmed by the user to perform a function required
for his application.

Advantages of PLDs over fixed function ICs

• Short design cycle.
• Low cost of development
• Low power consumption
• Reduction in board space requirements
• Compact circuitry
• Security of Design
• High switching speed
 Types of PLDs
• ROM used as PLD
• Programmable logic Arrays (PLAs)
• Programmable Array logic (PAL)
• Simple programmable logic devices (SPLDs)
• Complex programmable logic devices (CPLDs)
• Field programmable Gate Arrays(FPGAs)

PLDs allows designers more flexibilities to

experiment with design because these can be
reprogrammed in seconds. The design deficiencies
and modifications can be carried out in short time
thereby reducing the possibility of huge cost over-runs.
PLDs are useful for prototyping ASIC
(Application Specific IC) designs since foundry
produced ASIC may require months or costly
development.
 ROM as a PLD
Read only memory (ROM) is a basically combinational circuit and can be
used to implement a logic function. A ROM of size MXN has M number of
location and N number of bits can be stored at each location. The
number of address inputs is P, where 2P=M and number of data output
lines in N. it can be considered as a logic device with P inputs and N
outputs as shown in below figure.

In general, a ‘P’ variable, N outputs logic function can be implemented

using ROM of size 2PXN, Since all the possible minterms (2P) are
effectively generated. In case of PROM, EPROM user can program them
as per the requirements of the logic function .
 ROM as a PLD
Advantages
• Ease of design since no simplification of minimization of
logic functions is required.
• Cost is reduced.
• It is faster than discrete SSI/MSI Circuits
• Design can be changed/modified rapidly.

Disadvantages of ROM as PLD

• Non-utilisation of all minterms (complete Circuit)
• Increased Power requirement.
• Enormous increase in Size with increase in number of
input variables making it impracticable.
 ROM as a PLD
Example :- Implement Y = m(0,6,9,12,13,15) using ROM
Solution :- A 16-bit ROM array has
Address Bit
A3 A2 A1 A0 Stored four inputs and one output i.e.
0 0 0 0 1 M=16, N=1 and P=4. The bit
0 0 0 1 0
0 0 1 0 0 pattern as shown below can be
0 0 1 1 0 stored (Programmed) in the ROM.
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
 Programmable Logic Arrays (PLA)
A PLA consists of two level AND-OR Circuits on a single
chip. The number of AND & OR gates (both
programmable) and their inputs are fixed for a given chip.
The AND gates Provide product terms. The OR gates
logically sum these product terms and thereby generate a
SOP expression. It has M inputs, n product terms, and N
outputs with N<2M, and can be used to generate
(implement) a logic function of M variables with N outputs.
Since all of the Possible 2M min-terms are not available,
Therefore, logic minimization is needed to the implement a
given logic function.
 Internal Architecture of PLA
A PLA consists of two level AND-OR Circuits on a single chip. The
number of AND & OR gates (both programmable) and their inputs are
fixed for a given chip. The AND gates Provide product terms. The OR
gates logically sum these product terms and thereby generate a SOP
expression. It has M inputs, n product terms, and N outputs with
N<2M, and can be used to generate (implement) a logic function of M
variables with N outputs. Since all of the Possible 2M min-terms are
not available, Therefore, logic minimization is needed to the implement
a given logic function.
 Input Buffers
The input circuits at the input are required to limit loading of Sources
that drive the inputs. It produces inverted as well as non inverted
inputs at the output. Below given is a buffer for one input. Similar
buffers are used for each of the M inputs.
 AND Matrix
The AND matrix is used to
form product terms. It has
‘n’ AND gates with P0
through Pn-1 and 2M inputs
(I0 to IM-1 to I0 to IM-1) for
each AND Gate. A nichrome
fuse link in series with each
diode is used to programme
the AND matrix. All the links
are intact in an
unprogrammed PLA device.
Each AND Gate Generates
one Product term which is
given by
• P= I0.I0. I1.I1. …….…… IM-1. IM-1
 AND Matrix
For generating a required product
term, the unwanted links are opened
through method of programming by
programmer device
 Or Matrix
The OR matrix is also Programmable and is used to produce the logical
sum of the product term (SOP) outputs of the AND matrix. An OR gate
matrix Consists of Parallel connected transistors with common emitter
load. considering all fuse links intact, the output of OR matrix is given by
so = P0+P1------ Pn-1. From this, the required sum can be generated by
opening the unwanted links.
 Applications of PLA
The PLAs are used to implement combinational & sequential logic
circuits using following steps:-

•Prepare the truth table

•Write Boolean equation in SOP from
•Simplify the Boolean equation to reduce product terms
•Determine the input connections of AND matrix to generate
required product terms.
•Determine the imput connection of OR matrix to generate
required Sum terms.
•Determine the connections requited for invert/non invert matrix to
set the active logic levels of the outputs.
•Program the PLA.

PLAs are available as IC chips named 82S200, 828201 etc.

 Understanding PLA through an example
Implement following truth table using PLA.
Step- 1: Prepare truth table Step- 2 & 3 : Boolean equations
Inputs Outputs
A B C Y1 Y2 Y1= AB’C’ + AB’C + ABC
0 0 0 0 0 Y1 = AB’ + AC
0 0 1 0 0 Y2 = AC + BC
0 1 0 0 0
Step-4: Determine input connections
0 1 1 0 1
of AND Gate
1 0 0 1 0
No. of product terms = 03
1 0 1 1 1
No. of Programming AND gate= 03
1 1 0 0 0
Programming OR Gates = 02
1 1 1 1 1
 Programmable Array Logic (PAL)
It has Programmable AND matrix and Fixed OR matrix
Complex Programmable Logic Device (CPLD)
A CPLD is a programmable logic device with complexity between that
of PALs and FPGAs, and architectural features of both. The main
building block of the CPLD is a macrocell, which contains logic
implementing disjunctive normal form expressions and more
specialized logic operations.
CPLDs are well-suited for relatively simple designs with low logic
complexity. They offer a cost-effective solution for small-scale
projects.
CPLDs offer a high degree of flexibility, allowing designers to
implement a wide range of custom logic functions. Unlike fixed
function logic gates or ASICs (Application-Specific Integrated
Circuits), CPLDs can be programmed and reprogrammed to suit
changing design requirements.
•CPLD is frequently used in product prototyping and product
manufacturing (typically below 10,000 pieces) because it can realize
bigger scale circuit design.
Complex Programmable Logic Device (CPLD)
CPLD is made up of three parts: an I/O block, a programmable
interconnect channel, and a logic block.A programmable interconnect
matrix cell (PIMC) at the center of the CPLD is encircled by
programmable logic macro cells (MC, Macro Cell). The most complex
of them all, the MC structure stands out as having a complex I/O cell
interconnection structure that can be customized by the user to meet
the needs of a particular circuit structure to carry out particular tasks.
The timing of the suggested logic circuits may be reliably anticipated
since each internal logic block in the CPLD is connected using fixed-
length metal wires, avoiding the disadvantage of segmented
connectivity topologies
 Field Programmable Gate Array (FPGA)
FPGAs are integrated circuits that that can be reconfigured to meet
designers' needs. FPGAs contain an array of programmable logic
blocks, and chip adoption is driven by their flexibility, hardware-timed
speed and reliability, and parallelism.
 Comparison between FPGA and CPLD
•A CPLD is an integrated circuit that assists in the execution of digital systems. In
contrast, an FPGA is an integrated circuit that is mainly created to be customized after
manufacturing by a customer or a developer.
•FPGAs may include up to 100,000 small logic blocks. In contrast, CPLDs may only
store a few thousand logic blocks.
•FPGA is appropriate for complicated apps. In contrast, CPLD is better suited for
simpler apps.
•FPGA has a larger power usage. In contrast, CPLD has lower power consumption.
•In terms of performance, FPGA provides stable performance that is independent of
internal routing. In contrast, CPLD has unpredictable performance that is based on
routing.
•The CPLD is equivalent to the PAL. On the other hand, FPGA is similar to a Gate
array.
•FPGA is a digital logic chip that is based on RAM. In contrast, CPLDs are EEPROM-
based.
•FPGA is classified as fine grain. In contrast, CPLD is coarse grain.
•CPLD is provided more protection than FPGA because it has nonvolatile memory.
•Delays in CPLDs are significantly more predictable than in FPGAs.
•Head-to-head comparison between CPLD and FPGA
 References
Modern Digital Electronics – By RP Jain pages 522 to 565
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