Architecture, Programming, and Interfacing (8086 to Pentium)

THE HARDWARE STRUCTURE

OF 8086

PROF. DR. SHAMIM AKHTER

Professor, Computer Science and Engineering (CSE)
 8086/8088 Pin-Out
40-pin dual in-line package(DIP40)
- 16-bit microprocessor (registers) with 20 bits address bus (1 MB memory)
-8086 has 16 bits data bus
-8088 has 8 bits data bus

..
MIN/MAX MODE Operations

8086 Min Mode BASIC Operation

20-bit Address
16-bit Data
20 Bit Control & Status
3 power

59 bit total
Has 40 Pins

Solution:??

Multiplexing
 Why are there MIN and MAX modes?
• In brief minimum mode is designed for a single processor environment
while maximum mode is designed for a multiprocessor environment.

• In minimum mode, the processing unit issues control signals that memory
and i/o devices require. In a multiprocessor system, an external bus
controller issues control signals.

• A multiprocessor environment is necessary to implement cumbersome

mathematical operations that can be solved using a dedicated math
coprocessor such as 8087 which works hand in hand with 8086.
 Power supply requirements
Microprocessor Voltage Current Ambient Temp
8086/8088 +5.0V 360mA/340mA 32degF-180degF
80C86/80C86 +5.0V 19mA -40degF +255degF

DC Input Characteristics
Logic Level Voltage
0 +0.8V max
1 2.0V min

DC Output Characteristics
Logic Level Voltage
0 +0.45V max
1 2.4V min
 Pin Connections
Pin Numbers Activities
AD7-AD0 Lines are multiplexed and represents the rightmost 8 bit memory address
(8086,8088) or I/O port number whenever ALE is active (1) or data whenever ALE is
inactive (0).
AD15-AD8 Upper multiplexed/data bus. These lines represent A15-A8 whenever
(8086 only) Address Latch Enable(ALE). ALE=1 or D15-D8 whenever ALE=0
A15-A8 Provides the upper-half memory address bits.
(8088 only)
A19/S6-A16/S3 Works as multiplexed address signals and also status bits.
S6- always a logic 0.
S5-indicates the condition of the IF (Interrupt) flag bit
S3,S4- shows which segment is accessed during current bus cycle.
S4 S3 Function
0 0 Extra Segment
0 1 Stack Segment
1 0 Code or No segment
1 1 Data Segment
 RD Represents as Read Signal and activated at logic 0.
READY If READY bit is placed at a logic 1 , it has no effect
If READY bit is placed at a logic 0, microprocessor enters into wait states
and remains idle.
INTR When 1 and IF=1, microprocessor prepares to service
interrupt. INTA becomes active after current instruction completes.
TEST Test pin is an input that is tested by WAIT instruction
If TEST=1 ,WAIT instruction waits till becomes 0
Commonly connected to the 8087 coprocessor.
NMI Similar to INTR except that the NMI interrupt does not check to see
whether IF flag bit is a logic 1
RESET The microprocessor resets if this pin is held high for 4 clock periods.
Instruction execution begins at FFFF0H and clears the IF flag bit.
CLK Provides basic timing signal to the microprocessor. The Clock input must
have a duty cycle of 33% (high for 1/3 and low for 2/3s)
VCC Provides + 5.0 V
GND (2) Provides 0V
MN/MX Selects the minimum mode or maximum mode operation. During
minimum mode selection the pin connected to +5.V.
BHE/S7 Bus High Enable. Enables the most significant data bus bits (D15-D8) during
a read or write operation. S7 is always logic 1.
 Data Access from Memory
• Data can be accessed from memory in four
different ways:
– 8 bits data from Lower (Even) address bank.
– 8 bits data from Upper (Odd) address bank.
– 16 bits data from Even address.
– 16 bits data from Odd address.
Even and Odd Address
0/1
0=Bus high
enable 0/1
1=Bus high 0=Even add
disable 1=odd add

8bits(higher) 8bits (lower)

2 Bytes Data
0 00………….00 0 8
1 00…………..00 1 9
2 00…………..01 0 A
3 00…………..01 1 B
4 00…………..10 0 C

512KB=2^19 512KB=2^19
19 bits 19 bits
A19….A1 A19….A1
5 5
4 4
3 3
2 2 C
A0=0
1 B 1 A Even
0 9 0 8 Bank
ODD Bank
A19-A1
Accessing Even Address Only
8 bits data from Lower (Even) address bank.
 Accessing Odd Address Only
8 bits data from Upper (Odd) address bank.

A19-A1
 Accessing 16 bit Data, Start Even Address

A19-A1
 Accessing 16 bit Data, Start Odd Address
BHE=0, A0=1 BHE=1, A0=0
1 2

A19-A1 A19-A1

A19-A1 A19-A0
 Minimum Mode Pins
Pin Numbers Activities
IO/M (8086)or Indicates the address bus contains memory address or I/O port address.
M/IO (8088)
WR Is a strobe that indicates processor outputting data to a memory or I/O
device. The pin activates at logic 0. A strobe line is employed to signal the
receiving circuit when the input data is valid.
INTA Interrupt acknowledgement signal is a response to INTR input pin. Input
interrupt devices use to put the interrupt vector number on the data bus.
Microprocessor read the number and identify the ISR.
ALE Address Latch Enable. When 1, address data bus contains a memory or I/O
address.
DT/R Data Transmit/Receive. Data bus is transmitting/receiving data.
DEN Data bus Enable. Activates external data bus buffers.
HOLD Get request from DMA. Input Pin.
HOLD=1, CPU stops executing software and places address, data and
control BUS at the high-impedance state. High impedance or High-Z or Hi-Z
is a state when the output is not driven by the input(s), that means output
is neither high (1) nor low (0). The output is electrically disconnected from
the circuit.
HOLD = 0, CPU starts executing normal software.
 HLDA Output Signal.
Hold Acknowledge indicates processor has entered the hold state.
SS0 (8088) With IO/M an DT/R signal decode the function of current BUS cycle.

Bus cycle status (8088) using SS0

IO/M DT/R SSO Function
0 0 0 Interrupt Acknowledge
0 0 1 Memory Read
0 1 0 Memory Write In the x86 computer
0 1 1 Halt architecture, HLT (halt) is an
1 0 0 Opcode Fetch instruction that halts the central
processing unit (CPU) until the
1 0 1 I/O Read next external interrupt is fired.
1 1 0 I/O Write
1 1 1 Passive
 8086 Minimum Mode

Only one processor

MN/MX = Logical 1
Simple Circuit
Performance is lower Transceiver
8086
 Bus Latching and Buffering
• Buffers pass an input through to output after some propagation time, possibly
increasing drive strength.
• Latches additionally add memory, to capture and persist the input value at some point
in time (memory). This latching behavior is triggered by a third signal, control.
• Latches and Buffers are used to de-multiplex the address/data and address/status
lines and commonly have output buffers for driving external loads.
• That is, it's not RAM. It differs from a register in that the storage takes place while a
control input is at a particular level (0 or 1), while a register stores the input data upon
receipt of an edge (rising or falling).
 Three-state Buffer (Tri-state buffer)
0, 1, Z

• When enabled by the control line, output follows input

(buffered, pass-through).
• When disabled, output is a very high impedance which
prevents the output from driving or loading connected circuits.
• In effect, it is like a switch.
Bidirectional buffers (transceivers)
 Latches (D-type flip-flops)
• When enable(G) is high, Q follows D.
• When enable(G) goes low, Q maintains
(latches) the state of D.
• Eg: 74LS373 (latched on falling edge).
74LS374 (latched on rising edge)
 Maximum Mode Pins
Pin Numbers Activities
S2, S1, S0 Status bit indicates the function of the current bus cycle. Decoded by 8288
BUS controller and their activities are shown in the next slide.
RQ/GT1 and The request/grant pins work with DMA. These lines are bidirectional and
RQ/GT0 are used to both request and grant a DMA operation.
Lock It indicates that other system bus masters[DMA, Peripherals] have not been
allowed to gain control of the system bus while LOCK’ is active low(0). The
LOCK signal will be active until the completion of the next
instruction. BTS=>Bit Test and Set instruction. Read-Modify-Write@a
memory location
QS1 and QS0 The Queue Status bits show the status of the instruction queue.
Provided for access by the numeric coprocessor (8087).

QS1 QS0 Function

0 0 Queue is idle/No operation
0 1 First Byte of opcode
1 0 Queue is empty
1 1 Subsequent byte of opcode
 Bus control function generated by
8288 bus controller

S2, S1, S0 : Status pins. These pins are active during

T4, T1, and T2 states and are returned to the End of
the BUS Cycle or passive state (1,1,1 during T3 or Tw
(when ready is inactive)). These are used by the 8288
bus controller for generating all the memory and I/O
operation) access control signals. Any change in S2,
S1, S0 during T4 indicates the beginning of a bus
cycle. The 8288 bus controller uses these
 8086 Maximum Mode

Multiple co-processors
-8087 (numeric calculation), -
- 8089 (I/O coprocessor)

MN/MX is logical 0
Circuit is more complex
Performance is very high
 8288 Bus Controller

BUS
Command
Signals

Enable by CEN

Address
Latch, Data
Transceiver,
and Interrupt
Control
Block Diagram Pin-Out Signal
AEN enables memory control signal,
CEN enables command output pins
I/O bus mode or system bus mode
 8288 Pin Functions
Pin Numbers Activities

AEN Address Enable Input Pin causes 8288 to enable the memory control
signal
CEN Control Enable Input Pin enables the command output pins on the 8288
IOB Selects the I/O bus mode or system BUS mode.
MCE/PDEN The master cascade/peripheral data output selects cascade operation for
an interrupt controller if IOB is grounded,
and enables the I/O bus transceivers if IOB is tied high.
AMWT Advanced memory write control signal
AIOWC Advanced IO write control signal
These two output signals are enabled one clock cycle earlier than normal
write commands.
Some memory and I/O devices require this wider pulse width.
 Interfacing 8284 with 8086
• 8284 provides synchronization in generating Clock, Reset, and
Ready signals.
• Clock:

Micro Processor Unit

Clock div 3
Frequency

Internal External

Requires CSYNC HIGH will reset the internal counters, when CSYNC
Synchronization goes LOW the counters will resume counting.

CSYNC goes LOW

 Clock Generator (8284A) Negative edge FF (1-0)

Provides MP reset at
power on
resetting
positive
Square wave
edge (0-1)
signal

Frequency / Crystal

Peripheral
Clock -1/6 of
crystal/EFI
Bus ready 1- EFI (external) freq
0 (Ground)- Internal
5MHz Clock
Signal

Negative
edge FF (1-0)

1st Stage Synchronization ASYNC =1 2nd Stage Synchronization

 RESET Operation
• RESET: The reset input causes the microprocessor to reset itself if this pin is held high
for at least four clocking periods.
• Whenever the 8086 or 8088 is reset,
– it begins executing instructions at memory location FFFFOH and disables future interrupts by
clearing the IF flag bit.
– All registers become 0
– PC and SP become the initial origin address.
Condition to perfect
RESET Operation
Power applied

Within 4 Clock Cycles

Resistor-Capacitor-
Diode Filter Circuit RESET high-held 50 micro sec

Reset timing requirements: RESET=1 no later than 4 CC after system power is applied and to be high for
atleast 50 microseconds. FF ensures RESET=1 after 4 CC and RC ensures high for 50 microseconds.
https://www.youtube.com/watch?v=fs9qm_5re0Y
 Resistor-Capacitor-Diode Filter Circuit

Two methods to RESET

1. Power on RESET(Initial RESET)
2. Manual RESET

All registers become 0

Active on 0v PC and SP becomes
initial origin address.

10 micro Faraday

Condition to perfect RESET Operation

Power applied RESET high-held 50 micro sec
With in 4 clock cycles

https://www.youtube.com/watch?v=fs9qm_5re0Y
 RESET

CLK 5MHz

0 1
1 0

A special trigger called the Schmitt • It is an active circuit that converts

trigger is used an analog input signal to a digital output signal.
Upper threshold voltage (VUT) • The circuit is named “trigger”
– Output retains its value until the input changes
sufficiently to trigger a change.
Lower threshold voltage (VLT).
– When the input is higher than the threshold
(chosen),
• Output is high.
– When the input is below the threshold (different
(lower) chosen )
• Output is low,
– When the input is between the two levels
• the output retains its value.
Ready Synchronization circuitry
No changes in RDY

Changes in RDY need to setup and hold times

•
BUS CYCLES
There are at least four clock periods in a bus cycle of 8086 microprocessor. These four clock
periods are called T1, T2, T3 and T4 states.
• These four clock states gives bus cycle duration T of 200 ns *4 = 800 ns in 5-MHz 8086
system.
• Read Cycle :
– T1 microprocessor puts an address on address and address/data bus. The ALE,
DT/R’, IO/M’ or M/IO’ signals are also output.
– T2 state RD’ and DEN’ are activated and the bus is put in high impedance state.
– Data to be read must be out on bus during T3 and T4.
– During T3 bus is made “reserved for data in” and finally data is read during T4.
– RD’ signal is deactivated.
• Write Cycle :
– T1 state microprocessor puts an address on address bus.
The ALE, DT/R’, IO/M’ or M/IO’ signals are also output.
– T2 state W’ and DEN’ are activated. Data is put on data bus
by CPU and appear on the address/data bus.
– T3 and T4 states, Data is written out to memory or I/O, In
T4 all bus signals are deactivated in the preparation for
next bus cycle and make W’ to logic 1.
 READY and WAIT State
• READY input causes
– Wait states are required for slower memory and I/O
components

• A wait state (Tw) is an extra clock period

– Inserted between T2 and T3 to lengthen the BUS cycle
– If the normal effective memory access time is 460 ns with
a 5 MHz clock, by lengthening one clock period (200ns), it is
660ns.
 Wait State Circuit CS=logic 0 enable
Initial Logic 1 memory device
Usually FOUR (4) clock
signals are required to
complete a memory read or Logic 0
a memory write operation.

8 bits serial
shift register

READY
Parallel out serial shift register
 Clock Generator (8284A) Negative edge FF (1-0)

Provides MP reset at
power on
resetting
positive
Square wave
edge (0-1)
signal

Frequency / Crystal

Peripheral
Clock -1/6 of
crystal/EFI
Bus ready 1- EFI (external) freq
0 (Ground)- Internal
5MHz Clock
Signal

Negative
edge FF (1-0)

1st Stage Synchronization ASYNC =1 2nd Stage Synchronization

• EQ. Explain three major functionalities of the 8284 Clock generator circuit.
• EQ. Draw the reset (R-C) circuit and explain the activities of the manual reset procedure.
• EQ. Explain the procedure to generate the wait state.