Multiplexers, Demultiplexers, Encoders, Priority Encoders,

and Decoders
1. Introduction to Digital Logic Devices
Digital logic devices are essential in designing and implementing combinational circuits. They
help manage the flow of data and signals in systems. This lecture will cover five essential devices:
Multiplexers, Demultiplexers, Encoders, Priority Encoders, and Decoders. Each device is
described in detail, along with example and truth tables.

2. Multiplexers (MUX)
2.1 What is a Multiplexer?

A multiplexer (MUX) is a combinational circuit that selects one of many input signals and
forwards it to a single output line. The selection of the input is controlled by select lines.

Example: A 4:1 multiplexer has four input lines (I0, I1, I2, I3) and two select lines (S0, S1) that
control which input is passed to the output.

2.2 Truth Table for 4:1 MUX

S1 S0 Output (Y)
0 0 I0
0 1 I1
1 0 I2
1 1 I3

e.g. when select lines are S1 = 0, S0 = 1, input I1 is passed to the output.

2.3 Circuit Diagram for 4:1 MUX

A 4:1 multiplexer can be designed using AND, OR, and NOT gates. Each input is ANDed with
the respective select line combination, and the results are ORed to produce the final output.
3. Demultiplexers (DEMUX)
3.1 What is a Demultiplexer?

A demultiplexer (DEMUX) is the reverse of a multiplexer. It takes a single input and routes it
to one of several outputs, based on the select lines.
  Example: A 1:4 demultiplexer takes one input and distributes it to one of four output
lines.

3.2 Truth Table for 1:4 DEMUX

Output Output Output Output

S1 S0
Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

3.3 Circuit Diagram for 1:4 DEMUX

The input is ANDed with the appropriate select line configuration to determine which output line
receives the input signal.
4. Encoders
4.1 What is an Encoder?

An encoder is a combinational circuit that takes multiple input signals and converts them into a
binary code. For example, an 8:3 encoder takes eight inputs and encodes them into three output
bits.

4.2 Truth Table for 8:3 Encoder

4.3 Circuit Diagram for 8:3 Encoder

The output lines are determined by the combination of the inputs using OR gates.

5. Priority Encoder
5.1 What is a Priority Encoder?

A priority encoder is a type of encoder where priority is given to the highest-order input. If
multiple inputs are active, the input with the highest priority is encoded.

5.2 Truth Table for 4:2 Priority Encoder

I3 I2 I1 I0 Output Y1 Output Y0 Valid

1 X X X 1 1 1
0 1 X X 1 0 1
0 0 1 X 0 1 1
0 0 0 1 0 0 1
0 0 0 0 - - 0

 Valid indicates whether an input is active.

6. Decoders

6.1 What is a Decoder?

A decoder is the inverse of an encoder. It takes a binary input and activates one output line
corresponding to that binary value. A 2:4 decoder takes a 2-bit input and activates one of four
output lines.
6.2 Truth Table for 2:4 Decoder

Input Input Output Output Output Output

S1 S0 Y0 Y1 Y2 Y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

6.3 Circuit Diagram for 2:4 Decoder

The inputs are ANDed with the appropriate combination of the input lines.

7. Constructing an 8:1 Multiplexer Using Two 4:1 Multiplexers

7.1 How to Build an 8:1 Multiplexer Using Two 4:1 Multiplexers

To build an 8:1 MUX, we can use two 4:1 MUXes and one 2:1 MUX.

1. The two 4:1 MUXes will handle inputs I0-I3 and I4-I7, based on the select lines S1 and
S0.
2. The outputs of these 4:1 MUXes are fed into a 2:1 MUX controlled by S2 (the third select
Priority Encoder: Explanation and Example Cases

A priority encoder is a type of encoder that assigns priority to the inputs, meaning if multiple
inputs are active (set to high), the one with the highest priority (usually the input with the highest
index) will be encoded as the output. This ensures that when more than one input is active, the
system knows which one to prioritize.

Priority Encoder Operation

In a 4:2 priority encoder, the four inputs are I3, I2, I1, and I0, and the two outputs are Y1 and
Y0. In addition, a valid output is used to indicate that at least one input is active. The highest
priority input is I3, followed by I2, I1, and finally I0.

4:2 Priority Encoder Truth Table

Input I3 Input I2 Input I1 Input I0 Output Y1 Output Y0 Valid

0 0 0 0 - - 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1

Explanation of Priority Encoder Operation:

 Highest Priority Input (I3): If I3 is active (1), no matter the values of I2, I1, and I0,
the output will be determined by I3. The output will be Y1 = 1 and Y0 = 1, representing
the binary code for 3 (the index of I3).
  Lower Priority Inputs: If I3 is 0, the encoder will then check I2. If I2 is active, the
output will be Y1 = 1 and Y0 = 0, representing the binary code for 2 (the index of I2).
 Valid Output: This indicates whether any input is active. If no inputs are active, Valid
= 0, meaning the encoder has no valid data.

Example Cases of a Priority Encoder

Case 1: Only One Input is Active

 Inputs: I3 = 0, I2 = 0, I1 = 1, I0 = 0
 Explanation: Since only I1 is active, the encoder will output Y1 = 0 and Y0 = 1, which
is the binary code for 1 (the index of I1).
 Output: Y1 = 0, Y0 = 1, Valid = 1

Case 2: Two Inputs Are Active

 Inputs: I3 = 0, I2 = 1, I1 = 1, I0 = 0
 Explanation: Even though both I2 and I1 are active, I2 has a higher priority. The
encoder will output Y1 = 1 and Y0 = 0, which is the binary code for 2 (the index of I2).
 Output: Y1 = 1, Y0 = 0, Valid = 1

Case 3: Highest Priority Input is Active

 Inputs: I3 = 1, I2 = 0, I1 = 1, I0 = 1
 Explanation: Since I3 is the highest priority input, it will be encoded even though I1
and I0 are also active. The output will be Y1 = 1 and Y0 = 1, representing the binary
code for 3 (the index of I3).
 Output: Y1 = 1, Y0 = 1, Valid = 1

Case 4: No Input is Active

 Inputs: I3 = 0, I2 = 0, I1 = 0, I0 = 0
 Explanation: Since no inputs are active, the output will be invalid, and the Valid signal
will be 0.
 Output: Y1 = -, Y0 = -, Valid = 0

Application Example: Priority encoders are used in processors to manage hardware

interrupts. When multiple devices request an interrupt at the same time, a priority encoder ensures
that the processor services the interrupt with the highest priority. For example, if a disk drive
(higher priority) and a keyboard (lower priority) both request an interrupt, the encoder will service
the disk drive first.
 DLD ASSIGNMENT 2- CLO2
Submission due date: 16th May 2025
Total marks: 5
Instructions:
 The assignment must be handwritten on A4-sized papers.
 Submission is mandatory for all students.

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1. Implement a logic circuit for the truth table in Figure 1

Figure 1

2.

Figure 5-61

3. For a 4-bit comparator:

4.

5. (a) State the difference(s) between an encoder and a priority encoder.

(b) With reference to Encoders,

6.
 Figure 6-44

Figure 6-45

7. Assuming your class roll number is a decimal number,

i) Convert it to its BCD equivalent (e.g. 0220000 0010 0010)
ii) AND the BCD equivalent in (i) with 000000000001
iii) Pass the ANDed output in (ii) through an inverter
iv) Represent steps (i)-(iii) in the form of timing diagrams.

8. As part of an aircraft’s functional monitoring system, a circuit is required to indicate the status of the landing gears
prior to landing. A green LED display turns on if all three gears are properly extended when the “gear down” switch
has been activated in preparation for landing. A red LED display turns on if any of the gears fail to extend properly
prior to landing. When a landing gear is extended, its sensor produces a LOW voltage. When a landing gear is
retracted, its sensor produces a HIGH voltage. Implement a circuit to meet this requirement.