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UVM Snippets

The document outlines the structure and functionality of various components in a UVM (Universal Verification Methodology) environment, including transaction classes, sequences, drivers, monitors, environments, tests, scoreboards, and agents. Each component is defined with its purpose, such as creating and sending transactions, monitoring DUT behavior, and checking results against expected outcomes. The document provides code snippets and explanations for each component, illustrating how they interact within the verification framework.

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Anand N
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0% found this document useful (0 votes)
34 views5 pages

UVM Snippets

The document outlines the structure and functionality of various components in a UVM (Universal Verification Methodology) environment, including transaction classes, sequences, drivers, monitors, environments, tests, scoreboards, and agents. Each component is defined with its purpose, such as creating and sending transactions, monitoring DUT behavior, and checking results against expected outcomes. The document provides code snippets and explanations for each component, illustrating how they interact within the verification framework.

Uploaded by

Anand N
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UVM Snippets

1) UVM Sequence Item (Transaction Class):


class my_transaction extends uvm_sequence_item;
rand bit [7:0] data;
`uvm_object_utils(my_transaction)

function new(string name = "my_transaction");


super.new(name);
endfunction
endclass
Explanation:
Defines a transaction (or sequence item).
Registered with factory using uvm_object_utils for reuse and randomization.

2) UVM Sequence:
class my_sequence extends uvm_sequence #(my_transaction);

`uvm_object_utils(my_sequence)

function new(string name = "my_sequence");


super.new(name);
endfunction

task body();
my_transaction tx = my_transaction::type_id::create("tx");
start_item(tx);
assert(tx.randomize());
finish_item(tx);
endtask
endclass

Explanation:
Controls how transactions are created and sent to the driver.
The body task defines the sequence flow.

3) UVM Driver:
class my_driver extends uvm_driver #(my_transaction);

`uvm_component_utils(my_driver)
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
task run_phase(uvm_phase phase);
forever begin
my_transaction tx;
seq_item_port.get_next_item(tx);
$display("DRIVER: Received tx with data = %0d", tx.data);
seq_item_port.item_done();
end
endtask
endclass
Explanation:
Controls how transactions are created and sent to the driver.
The body task defines the sequence flow.

4) UVM Monitor:
class my_monitor extends uvm_monitor;

`uvm_component_utils(my_monitor)

function new(string name, uvm_component parent);


super.new(name, parent);
endfunction

task run_phase(uvm_phase phase);


forever begin
$display("MONITOR: Observing behavior...");
#10;
end
endtask
endclass

Explanation:
- Passively samples DUT signals for coverage or checking.
Used for scoreboard or functional coverage.

5) UVM Environment:
class my_env extends uvm_env;

my_driver drv;
my_monitor mon;

`uvm_component_utils(my_env)

function new(string name, uvm_component parent);


super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);


super.build_phase(phase);
drv = my_driver::type_id::create("drv", this);
mon = my_monitor::type_id::create("mon", this);
endfunction
endclass

Explanation:
Instantiates components like driver and monitor.
Acts as a container in the verification environment.
6) UVM Test:
class my_test extends uvm_test;

`uvm_component_utils(my_test)

my_env env;
my_sequence seq;

function new(string name, uvm_component parent);


super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);


super.build_phase(phase);
env = my_env::type_id::create("env", this);
endfunction

task run_phase(uvm_phase phase);


phase.raise_objection(this);
seq = my_sequence::type_id::create("seq");
seq.start(env.drv.seq_item_port);
phase.drop_objection(this);
endtask
endclass
Explanation:
Top-level block that connects everything.
It starts the sequence and manages simulation flow.

7) UVM Scoreboard:
class my_scoreboard extends uvm_scoreboard;

`uvm_component_utils(my_scoreboard)

function new(string name, uvm_component parent);


super.new(name, parent);
endfunction

task run_phase(uvm_phase phase);


forever begin
$display("SCOREBOARD: Checking results...");
#20;
end
endtask
endclass

Explanation:
Performs output checking or result comparison.
Used for checking DUT behavior against golden models.
8) UVM Agent:
class my_agent extends uvm_agent;

`uvm_component_utils(my_agent)

my_driver drv;
my_monitor mon;

function new(string name, uvm_component parent);


super.new(name, parent);
endfunction

function void build_phase(uvm_phase phase);


super.build_phase(phase);
drv = my_driver::type_id::create("drv", this);
mon = my_monitor::type_id::create("mon", this);
endfunction
endclass

Explanation:
Wraps sequencer, driver, and monitor into one unit.
Can be active (drives DUT) or passive (just monitors).

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