ANALOG CIRCUITS

UNIT I
BJT Biasing: Transistor Biasing and Stabilization - Operating point, DC & AC load lines,
Biasing –Fixed Bias, Self Bias, Bias Stability, Bias Compensation using Diode

BJT Small Signal Model: Transistor Hybrid model, Determination of h-parameters from
transistor characteristics, Typical values of h- parameters in CE, CB and CC configurations,
Transistor at High Frequency: Hybrid –𝜋 model of Common Emitter transistor model, fα, fβ
and unity gain bandwidth, Gain-bandwidth product.

1.1 Biasing
 In order to operate transistor in the desired region we have to apply external d.c
voltages of correct polarity and magnitude to the two junctions of the transistor. This
is known as biasing of the transistor.
 The d.c voltages are used to bias the transistor.

1.1.1 Need for Biasing

 To operate the transistor in the desired region.
 To get the output signal power always greater than input signal power.

1.2 Operating point or Quiescent point

 A point which establishes a certain current and voltage conditions, while biasing a
transistor.
 The operating point must be stable for proper operation of the transistor.
 However, the operating point shifts with changes in transistor parameters such as
β, ICO
and VBE.
 As transistor parameters are temperature dependent, the operating point also
varies with changes in temperature.

1.2.1 Selection of Operating Point

 The operating point can be selected at three different positions on the dc load line:
near saturation region, near cut-off region or at the center, i.e. in the active region.
 The selection of operating point will depend on its application.
 When transistor is used as an amplifier, the Q point should be selected at the
center of the dc load line to prevent any possible distortion in the amplified output
Signal.
 This is well understood by going through following cases.

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1.2.1.1 Case 1: Operating point near saturation region
 Biasing circuit is designed to fix a Q-point at point P which is very near to the
saturation region is shown in Fig. 1.1.

Fig. 1.1 Operating point near saturation region gives clipping at the positive peaks
 Collector current is clipped at the positive half cycle.
 Therefore, point P is not a suitable operating point.

1.2.1.2 Case 2: Operating point near cut-off region

Fig. 1.2 Operating point near cut-off region gives clipping at the negative peaks
 Biasing circuit is designed to fix a Q-point at point R which is very near to the cut-
off region is shown in Fig. 1.2.
 The collector current is clipped at the negative half cycle.
 So, point R is also not a suitable operating point.

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1.2.1.3 Case 3: Operating point at the centre of the active region
 Biasing circuit is designed to fix a Q-point at point Q as shown in Fig. 1.3.
 The output signal is sinusoidal waveform without any distortion.
 Thus point Q is the best operating point.

Fig. 1.3 Operating point at the centre of the active region is most suitable
1.3 DC Load line
 The line drawn between two points IC and VCE is called as DC load line.
 Consider a common emitter circuit shown in the Fig. 1.4.
 The transistor in the Fig.1.4 is biased with a common supply such that the base
emitter junction is forward biased and the collector base junction is reverse biased.

Fig. 1.4 Common emitter amplifier

 Coupling capacitor CC act as a DC blocking element.

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  Input side coupling capacitor CC couples AC input signal to the base of the
transistor.
 Output side coupling capacitor CC couples AC output signal of the transistor to the
load.
1.3.1 DC analysis
 To find dc analysis ac signal is equal to zero and the capacitors are open circuited.
 Therefore, DC equivalent circuit for common emitter amplifier is shown in the Fig.
1.5.

Fig. 1.5 DC equivalent circuit of figure 1.4

 Applying Kirchhoff’s voltage law to the base circuit of Fig. 1.5, we get

Where
IB is the base current
 Applying Kirchhoff’s voltage law to the collector circuit shown in the Fig. 1.5, we get

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 Where
IC RC is the voltage drop across RC
VCE is the collector to emitter voltage.

 From the above collector current equation, we get

 From the equation number 4, we can draw a straight line on the graph of I C versus
VCE which is having slope - 1/RC and Y-intercept VCC/RC.
 Apply IC=0 (transistor is in cut off region) in the equation number 4, we get

 Apply VCE=0 (transistor is in saturation region) in the equation number 4, we get

 The Fig. 1.6 shows the output characteristics of a common emitter configuration
with DC load line drawn between points A and B.

Fig. 1.6 Common emitter output characteristics with dc load line

1.4 A.C. Load Line

 The AC load line is a straight line with a slope equal to the AC impedance facing
the nonlinear device.
 Consider a common emitter amplifier circuit as shown III Figure 1.7.

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 Fig. 1.7 Common emitter amplifier circuit

1.4.1 AC analysis
 To find ac analysis d.c signal is equal to zero and the capacitors are short circuited.
 Figure 1.8 shows the ac equivalent circuit of the common emitter amplifier.

Fig. 1.8 A.C. equivalent of Common emitter amplifier circuit

 From the above figure, the resistance driving the base,

 a.c. load resistance seen by the collector

 Now summing up the voltages around the collector loop of the a.c. equivalent
circuit,

 Now let

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 Then the a.c collector current,

 The a.c collector-to-emitter voltage

 Substituting the values of ic and vce in equation (i),

 The above equation is an equation of a straight line called ac load line.

 We know that when the transistor goes into saturation, the collector-to-emitter
voltage (VCE) becomes zero.
 In that case, the equation (ii) may be written as

 The above expression gives the upper end of the ac load line.
 Similarly, when the transistor goes into cut-off, the collector current (IC) becomes
zero.
 In that case, the equation (ii) may be written as

 The above equation gives us the lower end of ac load line.

 By joining the upper and lower ends, we get a complete ac load line as shown in
Figure 1.9.

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 Fig. 1.9 A.C. load line

1.5 Introduction to Bias Stability

 The biasing circuit should be designed to fix the operating point or Q point at the
center of the active region.
 While designing the biasing circuit, care should be taken so that the operating point
will not shift into an undesirable region (i.e. into cut-off or saturation region).
 Designing the biasing circuit to stabilize the Q point is known as bias stability.
 Two important factors are to be considered while designing the biasing circuit
which is responsible for shifting the operating point
 Temperature dependent factors (Ico, VBE)
 Transistor current gain β / hfe
 To maintain the operating point stable by keeping I C and VCE constant, so that the
transistor will always work in active region.
 The following techniques are used to stabilize the operating point
 Stabilization techniques
 Compensation techniques.

1.5.1 Stabilization techniques

 Stabilization techniques refer to the use of resistive biasing circuits which allow IB
to vary so as to keep IC relatively constant with variations in lCO, β and VBE.

1.5.2 Compensation techniques

 Compensation techniques refer to the use of temperature sensitive devices such
as diode, transistors, thermistors etc., which provide compensating voltages and
currents to maintain the operating point stable.

1.6 Stability Factor

 The stability factor may be defined as the rate of change of collector current with
respect to the reverse saturation current keeping the common-emitter current gain
(β) and base emitter voltage (VBE) as constant.
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  The stability factor is a measure of bias stability of a transistor circuit.
 Stability factor indicates the degree of change in operating point due to variation in
temperature.
 Ideally stability factor should be perfectly zero to keep the operating point stable.
 Practically stability factor have the value as minimum as possible.
 Other stability factors are

1.6.1 Derivation of stability factor

 For a common emitter configuration collector current is given as

 Differentiate the above equation with respect to IC

 The above equation can be considered as a standard equation for derivation of

stability factors of other biasing circuits.

1.7 Methods of Transistor Biasing

 Following are the most commonly used methods for biasing the transistors.
 Fixed bias (Base bias)
 Emitter feedback bias (Emitter to Base bias)
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  Collector feedback bias (Collector to Base bias)
 Collector - Emitter Feedback Bias (Collector - Emitter to Base
bias)
 Voltage divider bias (self bias)
1.8 Fixed bias (Base bias)
 The Fig. 1.10 shows the common emitter amplifier using fixed bias circuit.
 The Base Resistor RB is connected between VCC and Base (B) terminal.

Fig. 1.10 Common emitter amplifier using fixed bias

 Find the d.c analysis (a.c Input is equal to zero & all capacitors are open circuited)
for the figure 1.10.
 The d.c equivalent circuit of fixed bias is shown in Fig. 1.11.

Fig. 1.11 D.C equivalent circuit of fixed bias

1.8.1 Base-Emitter Circuit Analysis

 Applying Kirchhoff's voltage law to the base to emitter circuit of figure 1.11, we get
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  Solving for the current IB

1.8.2 Collector-Emitter Circuit Analysis

 Applying Kirchhoff's voltage law to the collector to emitter circuit of figure 1.11, we
get

 From the above equation, the Collector to emitter voltage (VCE) is given by

 The magnitude of collector current (IC)is given by

 The collector current (IC)can also give from equation (2)

 The Collector to emitter voltage (VCE) also given in terms of VC and VE

 Similarly, the Base to emitter voltage (VBE) also given in terms of VB and VE

 From the figure 1.11, the Emitter voltage VE=0.So we can write VBE and VCE as

1.8.3 Stability factor for fixed bias

 From the base-emitter circuit analysis of figure 1.11, we have base current

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  Differentiate the above equation with respect to Collector current I C

--- (i)
 We have general formula for stability factor

--- (ii)
 Substitute the value of equation (i) into equation (ii), we get

1.8.4 Advantages and Disadvantages of Fixed bias circuit

Advantages
 Simple circuit which uses very few components.
 It provides maximum flexibility in the design.
Disadvantages
 Operating point is not maintained.
 Stabilization of operating point is very poor.

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1.9 Voltage Divider Bias (or) Self bias
 The d.c biasing methods discussed earlier, we have found that the values of Base
current and Collector to emitter voltage depends upon the current gain (β) of the
transistor.
 The value of current gain (β) is temperature sensitive especially for silicon
transistors.
 It would be desirable to provide a d.c bias circuit which is independent of the
transistor current gain (β)
 Fig. 1.12 Common Emitter amplifier using Voltage divider bias circuit.

Fig. 1.12 Common Emitter amplifier using Voltage divider bias circuit
 In this circuit, the biasing is provided by three resistors: R1, R2 and RC.
 The emitter resistor (RE) provides the d.c stability.
 The resistors R1 and R2 act as a potential divider giving a fixed voltage to the base
terminal.

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  Find the d.c analysis (a.c Input is equal to zero & all capacitors are open circuited)
for the figure 1.12.
 The d.c equivalent circuit of voltage divider Bias is shown in Fig. 1.13.

Fig. 1.13 DC Equivalent circuit of Voltage divider bias circuit

1.9.1 Base-Emitter circuit analysis

 From the figure 1.13, Voltage across R2 is the base voltage VB.
 Apply the voltage divider theorem to find VB, we get,

1.9.2 Collector-Emitter circuit analysis

 Now Apply Kirchoff's Voltage Law to collector to emitter circuit loop of figure 1.13,
we get

 Substituting IE ≈ IC in the above equation

 Voltage across RE is VE and can be written as

 From the above equation find the value of Emitter current IE

 We know that IE ≈ IC

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1.9.3 Simplified Circuit of Voltage Divider Bias
 Fig. 1.14 shows simplified circuit of voltage divider bias which is shown in figure
1.13.
 Here, R1 and R2 are replaced by RB and VB is replaced by Thevenin's voltage VT

Fig. 1.14 Thevenin's equivalent circuit for voltage divider bias

 RB and VT can be given as

1.9.4 Stability factor for Voltage Divider Bias

 From the base-emitter circuit analysis of figure 1.14, we have base current

 Differentiate above equation with respect to IC

--- (i)
 We have general formula for stability factor

--- (ii)
 Substitute the value of equation (i) into equation (ii), we get

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  Let RE >> RB

1.9.5 Advantages of Self Bias or Voltage Divider Bias Circuit

 Stability factor S for voltage divider bias or self bias is less as compare to other
biasing circuits.
 So this circuit is more stable and hence it is most commonly used.

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1.10 Bias Compensation using Diodes
 The collector to base bias and the voltage follower bias use the negative feedback
to do the stabilization action.
 This negative feedback reduces the amplification of the signal.
 If this loss in signal amplification is intolerable and extremely stable biasing
conditions are required, then it is necessary to use compensation techniques.
o Compensation for VBE
o Compensation for lCO
1.10.1 Compensation for VBE
1.10.1.1 Diode in Emitter Circuit
 Fig. 1.15 shows the voltage divider bias with bias compensation technique.
 Here, separate supply VDD is used to keep diode in forward biased condition.
 If the diode and the transistor are made up of the same type material, then the
voltage across the diode will have the same temperature coefficient (-2.5 mV/0C)
as the base to emitter voltage VBE.
 So when VBE changes by әVBE with change in temperature, VD also changes by
әVD then the changes tend to cancel with each other.
 Apply KVL to the base circuit of Fig. 1.15 we have

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 Fig. 1.15 Stabilization by means of voltage divider bias and diode compensation technique

 The total output current in common emitter configuration is given by

 Find the value of base current IB in above equation

 Substitute the value of Base current IB in equation (1)

 Since VD tracks VBE with respect to temperature, it is clear from equation (2) that, IC
will be insensitive to variations in VBE.
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1.10.1.2 Diode in voltage divider circuit
 Fig. 1.16 shows diode compensation technique used in voltage divider bias.

Fig. 1.16 Diode compensation in voltage divider bias circuit

 Here, diode is connected in series with resistance R2 and it is in forward biased
condition.
 From the voltage divider bias circuit, we have

 When VBE changes with temperature, IC also changes.

 To cancel the change in IC, one diode is used in this circuit for compensation as
shown in Fig. 1.16.
 From figure 1.16,the voltage at the base is VB and is given by

 Substitute the value of VB in equation (3)

 If the diode and the transistor are made up of the same type material, then the
voltage across the diode will have the same temperature coefficient (-2.5 mV/0C)
as the base to emitter voltage VBE.
 So when VBE changes by әVBE with change in temperature, VD also changes by
әVD then the changes tend to cancel with each other.

 From the above equation, we can see collector current I C is unaffected by change
in VBE.
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1.10.2 Compensation for lCO
 In case of germanium transistors, changes in lCO with temperature are
comparatively larger than silicon transistor.
 Thus, in germanium transistor changes in lCO with temperature play more important
role in collector current stability than the changes in the VBE.

Fig. 1.17 Diode compensation for a germanium transistor

 The Fig. 1.17 shows diode compensation technique commonly used for stabilizing
germanium transistors.
 It offers stabilization against variation in lCO.
 In this circuit diode is kept in reverse biased condition.
 In reverse biased condition the current flowing through diode is only the leakage
current.
 If the diode and the transistor are of the same type and material, the leakage
current IO of the diode will increase with temperature at the same rate as the
collector leakage current lCO.
 From Fig. 1.17, the current through resistor R1 is given by

 Let VCC >> VBE, so the above equation becomes

 The total output current in common emitter configuration is given by

--- (i)
 From Fig. 1.17, we have

--- (ii)
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  Substitute the IB value in equation (ii) into equation (i), we get

 If β >> 1, the above equation becomes

 If the diode and the transistor are made up of the same type material, then IO = ICO

 From the above equation as I is constant, IC remains fairly constant.

1.11 BJT Small Signal Model

 A transistor model is a combination of circuit elements, which deals the actual
behavior of a transistor under specific operating condition.
 The transistor behavior is different at low frequencies and high frequencies.
 At low frequencies the reactance’s of junction capacitances of the transistor are
very high and can be ignored.
 But this is not the case at high frequencies.
 Therefore, we use different transistor models to analyze the transistor at low and
high frequencies. At low frequencies we use hybrid equivalent model and at high
frequencies we use hybrid π model.

1.12 BJT Hybrid model (or) h parameter model

 The equivalent circuit of a transistor can be drawn using hybrid model.
 The parameters which are used in hybrid model called as hybrid parameters (or) h-
parameters.
 These are generally used to determine amplifier characteristic parameters such as
voltage gain, input and output resistances.
 The hybrid parameters give very accurate results in transistor amplifier circuit
analysis.

1.12.1 Benefits of h-parameters

 Real numbers at audio frequencies.
 Easy to measure.
 Can be obtained from the transistor static characteristic curves.
 Convenient to use in circuit analysis and design.
 Most of the transistor manufacturers specify the h-parameters.

1.12.2 The h-parameters of a Linear Circuit

 Figure 1.18 (a) shows a model of any linear device or a circuit.

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  This device or a circuit is represented by a box and has four terminals i.e., two-
terminals 1- 1' for input and two-terminals 2-2' for output.
 The behavior of this circuit is specified by two voltages and two currents.

Fig. 1.18 Linear Circuit and its Hybrid model

 Two voltages are the input voltage (V1) and the output voltage (V2).
 The two currents are the input current (i1) and output current (i2).
 The linear circuit may be replaced by an equivalent circuit as shown in Figure 1.18
(b).
 The equivalent circuit is called hybrid model of a linear circuit.
 In such a circuit, the input voltage and the output current may be related in terms of
the input current and output voltage by the following two equations.

 The equations (i) and (ii) have been obtained by applying Kirchoff's Voltage Law to
the input and output circuits of the hybrid model shown in figure 1.18 (b).
 Thus a linear circuit has a set of four h-parameters namely h11, h12, h21 and h22.

1.12.3 Determination and Meaning of h-parameters

Fig. 1.19 Determination of h parameters

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1.12.3.1 Determination of h11 and h21
 These are determined by short-circuiting the output terminals of a given circuit as
shown in Figure 1.19 (a).
 A short-circuit at the output terminals makes the voltage V2 equal to zero.
 We know that the input voltage is given by the relation,

 Substituting the value of v2 (equal to zero) in the above equation, the input voltage,

 Similarly, we know that the output current is given by the relation,

 Again substituting the value of v2 (equal to zero) in the above equation, the output
current,

1.12.3.2 Determination of h21 and h22

 These are determined by open circuiting the input terminals of a given circuit as
shown in Fig. 1.19 (b).
 An open circuit, at the input terminals makes the input current (i1) equal to zero.
 We also know that the input voltage is given by the relation

 Substituting the value of i1 (equal to zero) in the above equation, the input voltage,

 Similarly, we know that the output current is given by the relation,

 Again substituting the value of i1 (equal to zero) in the above equation, the output
current,

1.12.4 Another Representation for h-parameters

 Sometimes, it is more convenient to represent the parameters h 11, h12, h21 and h22
as hi hr, hf and ho respectively.
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  In other words

1.12.5 Transistor configurations and their hybrid models

 The basic circuit of hybrid model is same for all the three configurations, only
parameters are different.
 The Fig. 1.20 shows the transistor configurations and their hybrid models.

Fig. 1.20 Transistor configurations and their hybrid models

 The circuits and equations in Fig. 1.20 are valid for either an n-p-n or p-n-p
transistor and are independent of the type of load or method of biasing.

1.13 Determination of h-parameters from Transistor Characteristics

 Let us consider common emitter configuration. Its functional relationship can be
defined from the below equations.

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1.13.1 Determination of hie and hre from Input Characteristic Curves

Fig. 1.21 Input characteristics curve for the common emitter transistor configuration

 The input characteristic curves give the relationship between input voltage VBE and
the input current IB for different values of output voltage VCE.
 Fig. 1.21 shows typical input characteristic curves for the common emitter
transistor configuration.
 The parameter hie can be obtained as the change in the base voltage, V BE2 - VBE1,
divided by the change in the base current, IB2 - IB1, for a constant collector voltage
at the quiescent point, Q.
 The slope of the line EF, drawn tangent to the input characteristic curve at the point
Q gives hie.

 The parameter hre can be obtained as the change in base voltage, V BE2 – VBE1,
divided by the change in collector voltage, VCE2 – VCE1, for a constant base current
lB, at the quiescent point Q.

1.13.2 Determination of hfe and hoe from output Characteristic Curves

 The output characteristic curves give the relationship between output current l C and
output voltage VCE for different values of input current lB.
 Fig. 1.22 shows typical output characteristic curves for the common emitter
transistor configuration.

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 Fig. 1.22 Output characteristics curve for the common emitter transistor configuration

 It is the ratio of change in collector current IC taken around the quiescent point Q to
the corresponding change in the base current IB, for constant value of output
voltage VCE at the Q-point.

 The parameter hoe can be obtained as the change in the collector current, I C2 – IC1
divided by the change in the collector voltage, V CE2 – VCE1 for a constant base
current at the quiescent point Q.

1.14 Typical values of h- parameters in CE, CB and CC configurations

 Below Table gives the value of h-parameters of a typical transistor for CE, CB and
CC configurations.

S. No. Parameter CE CB CC

1. hi 1100Ω 22Ω 1100Ω

2. hr 2.5×10-4 3×10-4 1

3. hf 50 -0.98 -51

4. h0

5. 1/h0 40 kΩ 2 MΩ 40 kΩ

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1.15 Transistor at High Frequency
 To study and analyze the behavior of the transistor at high frequency signals by
Hybrid-pi or Hybrid-π model.

1.16 The Hybrid- pi () – Common Emitter transistor model

 Hybrid π model is used for high frequency analysis of the transistor.
 Fig. 1.23 shows the hybrid-π model for a transistor in the CE configuration.
 For this model, all parameters (resistances and capacitances) in the model are
assumed to be independent of frequency.
 But they may vary with the quiescent operating point.
 The various elements present in hybrid π model are Cb’e, Cb’c, rbb’, rb’e, rb’c, gm,
and rce.

Fig. 1.23 Hybrid π model for a transistors in the CE configuration

1.16.1 Hybrid π model Parameter Values

 The below Table shows the typical values for hybrid-π parameters at room
temperature and for IC =1.3 mA.

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1.16.2 Relation between hybrid - π model and h parameters
 The below Table summarizes the relation between hybrid - π model and h
parameters

1.17 Hybrid-π model parameters and its derivation

1.17.1 Transconductance (gm)
 Let us consider a n-p-n transistor in the CE configuration with V CC bias in the
collector circuit as shown Fig. 1. 24

Fig. 1.24 CE Configuration

 The transconductance is the ratio of change in the collector current due to small
changes in the voltage VB' E across the emitter junction.
 It is given as,

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  We know that, the collector current in active region is given as,

 Differentiate above equation w.r.t IC

 Substituting value of Ic in equation (1) we get,

 The emitter diode resistance, re is given as,

 Substituting the above value in equation (2) we get,

 The emitter diode is a forward biased diode and its dynamic resistance is given as,

Where VT is the "volt equivalent of temperature" and its value at room

temperature is 26mV

 Substituting the value of rein equation (4) into equation (3)

1.17.2 Input Conductance (gb'e)

 Fig. 1 . 25 and Fig. 1.26 show the h-parameter model and hybrid - π model for
CE configuration at low frequency respectively.
 At low frequency, all capacitors are negligible and hence not drawn in Fig. 1.26

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 Fig. 1.25 h-parameter model for CE configuration at low frequency

Fig. 1.26 Hybrid – π model for CE configuration at low frequency

 Apply KCL to the output circuit of figure 1.25, we get

 To find the short circuit current gain h fe , output is short circuited (i.e V ce=0) and the
above equation becomes

 From the figure, we have rb'c >> rb’e. Hence Ib flows into rb'e and Vb'e = Ib rb'e.

 Similarly as rb'e is very large, output current is given by

 Substituting value of IC/lb in equation (6) we get

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1.17.3 Feedback Conductance ( gb'e)
 Consider figure 1.25, when input is open circuited (Ib = 0) Vi is given as,

 Now consider the hybrid - π model for CE configuration as shown in Fig.1. 27.

Fig. 1.27 hybrid - π model for CE configuration

 With Ib = 0, Vce can be given as,

 The voltage between B' and E, Vb'e can be given as,

 From the figure 1.27, assume Ib = 0

 Substituting value of Vi in equation (9), we get

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1.17.4 Base Spreading Resistance (rbb')
 With h-parameter model (figure 1.25) for CE configuration, the input resistance with
output shorted (Vce = 0) is hie.
 With hybrid - π model (figure 1.26) input resistance with output shorted is rbb' + rb'e.

1.17.5 Output Resistance (gce)

 Using h-parameters (figure 1.25) the output conductance is given as,

 Consider hybrid - π model for CE configuration, shown in Fig. 1.27.

 Applying KCL to the output circuit we get,

 Substituting value of I1 from equation (10) we get,

 Substituting value of Vb'e from equation (11) we get,

 Dividing both sides by Vce we get,

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  Substituting value of IC/Vce in equation (14) we get,

1.18 CE short circuit current gain

 Consider a single stage CE transistor amplifier with load resistor RL, as shown in the Fig.
1.28.

Fig. 1.28 The hybrid - π model circuit for a single transistor with a resistive load R L

 For the analysis of short circuit current gain we have to assume RL = 0.

 With RL = 0, output short circuited rce=0, Cb’e (Ce), Cb’c (Cc) and rb’c appear in parallel.
 When Cc (Cb'c) appears between base and emitter, it is known as Miller capacitance (CM).
 Hence, the Miller capacitance (CM) is given by

 Apply RL=0 in the above equation, we will get

 As rb’c >> rb’e, rb’c is neglected.

 With this approximation we get simplified hybrid - π model for short circuit CE transistor, as
shown in the Fig. 1.29.
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 Fig. 1.29 simplified hybrid - π model for short circuit CE transistor
 Parallel combination of rb’e and (Ce + Cc) is given as

 The further simplified hybrid - π model as shown in the Fig. 1.30.

Fig. 1.30 Further simplified hybrid - π model

 Look at Fig. 1.30 we can write

 The current gain for the circuit shown in Fig. 1.30 can be given as,

 Substitute the value of Vb’e / Ib from equation (2) into above equation

 We have hfe= gm rb’e

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  Looking at equation (4) we can say that current is not constant. It depends on frequency.
 When frequency is small, the term containing f is very small compared to 1 and hence at low
frequency, Ai = - hfe.
 But as frequency increases Ai reduces as shown in Fig. 1.31.

Fig. 1.31 Frequency verses current gain curve

1.18.1 fβ (cut-off frequency)
 It is the frequency at which the transistor's short circuit CE current gain drops by 3 dB or
1 times from its value at low frequency.
2
 It is given as

Where

 At f=fβ

 We can also write fβ as

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1.18.2 fα (cut-off frequency)
 It is the frequency at which the transistor's short circuit CB current gain drops by 3 dB or
1 times from its value at low frequency.
2
 It is given as

Where

 At f=fα

 We can also write fα as

1.18.3 fT (Unity Gain Bandwidth)

 It is the frequency at which short circuit CE current gain becomes unity.
 At f = fT equation (6) becomes

 Let us assume fT/ fβ >> 1

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 Substituting the value of fβ from equation (7) into above equation

 Since Ce > Cc so the above equation becomes

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1.19 Gain bandwidth product
 The product of voltage gain and bandwidth of an amplifier is always constant when the roll
off is -20 dB/decade. Such a product is called gain bandwidth product.

1.19.1 Gain bandwidth product for Voltage

 We have, voltage gain including source resistance at low frequency is

 The gain bandwidth product for voltage gain is given as,

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  This equation can be further simplified as follows,

1.19.2 Gain-bandwidth product for Current

 We have, current gain including source resistance at low frequency is

 The gain bandwidth product for current gain is given as,

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 By similar analysis with replacement of - hfe RL by - hfe RS we get,

 The quantities fH, Aiso and Avso which characterize the transistor stage, depend on both RL
and RS.

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