1x3 Router – RTL Design & Verification Project Explanation & Interview
Q&A
Direct Spoken Explanation for Interview
My project was to design and verify a 1x3 router using Verilog HDL and UVM. The router
has one 8-bit input port and three output ports. It receives packets on the input port and
routes them to the correct output port based on the destination address in the packet
header.
The packet comes in three parts — the header byte, payload bytes, and a parity byte. In the
header, the top two bits are the destination address: 00 means send to output 0, 01 to
output 1, 10 to output 2, and 11 is invalid. The remaining bits carry part of the data. The
parity byte at the end is used to detect errors.
In the RTL, I implemented logic to decode the destination address, enable the right output
port, store the data in FIFO buffers, and perform parity checking. A state machine controls
the packet reception and routing.
For verification, I created a UVM-based testbench with a driver to send packets, a monitor
to observe DUT activity, a scoreboard to compare outputs with expected results, and
sequences to generate different traffic patterns — including valid packets, invalid
addresses, parity errors, and back-to-back packets. I also collected both code coverage and
functional coverage to ensure complete verification.
I used QuestaSim for simulation and Synopsys Design Compiler for synthesis. One challenge
I faced was generating random error packets while keeping the UVM environment reusable,
which I solved by writing dedicated sequence classes.
If I were to improve the design, I’d add more output ports, implement error correction, and
use advanced arbitration for multiple inputs.
Short Explanation (30–40 sec)
My project was a 1x3 router with an 8-bit input, designed in Verilog HDL. I developed a
UVM-based testbench with driver, monitor, scoreboard, and sequences to verify its
functionality. We collected both code and functional coverage using QuestaSim and
synthesized the design using industry tools.
Detailed Explanation (2–3 min)
In my project, I designed and verified a 1x3 router with an 8-bit input using Verilog HDL.
The router receives a packet on a single input port and directs it to one of three output ports
based on the address in the packet header.
For verification, I created a UVM-based testbench that included:
- Driver – Sends packets from the testbench to the DUT
- Monitor – Observes DUT inputs and outputs
- Scoreboard – Compares expected vs. actual results
- Sequence – Generates different packet patterns
I verified both functional correctness and collected coverage metrics — including code
coverage (to ensure all RTL lines are exercised) and functional coverage (to ensure all
scenarios are tested). Finally, I synthesized the RTL using industry-standard tools to check
for synthesis errors and confirm the design met timing requirements.
Understanding the 8-bit Input
The 8-bit input is the main data bus for receiving packets. The first byte is the header — its
top 2 bits indicate the destination output port, and the remaining bits carry part of the data.
The following bytes are payload, and the last byte is a parity byte for error checking.
Typical bit breakdown for the header:
[7:6] → Destination Address (2 bits)
[5:0] → Payload/Data bits (6 bits)
If DA = 00 → Output Port 0
If DA = 01 → Output Port 1
If DA = 10 → Output Port 2
If DA = 11 → Invalid/default handling.
Core Project Q&A
Q1. Why did you choose a 1x3 router instead of 1x4 or more?
It’s small enough to implement and verify within limited time, but still complex enough to
show routing, packet handling, and verification skills. Same principles scale to larger
routers.
Q2. How does your router decide the output port?
It reads the destination address bits in the header and enables the corresponding output
port using control logic.
Q3. How do you handle invalid destination addresses?
If address = 11 (invalid for 1x3), the router either drops the packet or sends it to a default
error port.
Q4. How does parity checking work?
During transmission, parity is calculated and compared with the parity byte at the end. If
mismatched, packet is marked corrupted.
Q5. What is the role of pkt_valid signal?
Indicates when a valid packet is being sent. If pkt_valid = 0 → No valid packet is present.
Q6. What kind of verification tests did you write?
Valid packet routing to each output, invalid address handling, parity error detection,
random packet sequences, and back-to-back packet transfers.
Q7. How does the router handle multiple packets back-to-back?
Each output port has a buffer, allowing sequential packet processing without overlap.
Q8. What was the main challenge in verification?
Testing corner cases like invalid addresses and parity errors required writing special UVM
sequences.
Q9. How does your scoreboard work?
It compares DUT output to a reference model output. Matches = pass; mismatches = error
logged.
Q10. What tools did you use and why?
QuestaSim – Simulation & debugging; Synopsys DC – Synthesis; SystemVerilog + UVM –
Advanced, reusable verification
Q11. How do you handle invalid or corrupted packets?
Detected using parity check or invalid address logic → sent to default port or dropped.
Q12. Did you face any synthesis issues?
Yes, unused signals created warnings. Solved by cleaning RTL and driving all outputs.
Q13. How would you improve the project?
Add more ports, include error correction, and use advanced arbitration for multiple inputs.
