Timing Closure

Lecture 1
Jignesh Shah
UCSC Extension, Silicon Valley
Spring 2024
Agenda
• Introduction
• Instructor, class and Students
• Introduction to timing closure
• Transistors and logic gates
• Combinational and sequential cells
• Timing model (aka liberty model)
• Lab
• Log on to student accounts
• Intro to HSPICE sims
• Characterize delay of inverter
• Characterize setup/hold for DFF
Something about Instructor

• Childhood in India.
• Immigrated to USA in 1999 for graduate study.
• Over 20+ years of industry experience in silicon valley. Jignesh Shah
• Currently working at SIMA.ai, a start up developing AI/ML solution.
• Approachable outside class room at jdshah@ucsc.edu.
• Enthusiastic in sharing his technical expertise through UCSC extension.
• Outside work & family life, enjoys watching sports, and listening to podcast.
 Something about Students

• Name
• Background in work or education.
• Expectation for timing closure class.
 Course Logistics Grade options %

• Ten Lectures Friday from 5:30 pm – 8:30 pm A Ø 93

A- 90 – 92
• Grading B+ 88 – 89
• Midterm on Week 6 (30%)
B 83 – 87
• Final is on Week 10 (30%)
B- 80 -82
• 8 equally weighted labs / homework (40%)
C+ 78 – 79
• For alternative grading options, contact
C 73 – 78
extengrade@ucsc.edu
C- 70 – 72
• Book Recommendation:
D+ 68 – 69
Static Timing Analysis for Nanometer Designs D 63 – 67
Authors: J. Bhasker, Rakesh Chadha D- 60 – 62
Publisher: Springer Science & Business Media F 59 and below
Credit 60 and above
No Credit 59 and below
Course Outline
Week / Module Topics (align with Learning Outcomes) Assignments
Week 1 Introduction Digital gate & Timing analysis Lab1 : Spice characterization of Inverter and flop
Lab2: STA on a design to understand the basic flow
Week 2 Setup & Hold timing check
and it's result
Lab3: STA on a design to understand how
Week 3 Manufacturing Variation
manufacturing variation is accounted.

Week 4 Design Constraint Lab 4: STA on a design to understand SDC.

Week 5 PVT and timing margin Lab 5: STA on a design across PVT corners.
Week 6 Clock Domain Crossing and Midterm No Lab . Midterm Quiz
Week 7 Signal Integrity / Crosstalk Lab 6: STA on a design to understand SI impact.
Lab 7: Run STA on different modes
Advance Topics, like multiple mode, Time
Week 8
borrowing

Week 9 Hierarchical Timing, Budgeting Lab8: <TBD>

Week 10 ECO, Final Exam None. Final Exam
 RTL-to-GDS of Digital Design
Functonal
Abstract Models,
Spec / Arch
Mfg Rules

RTL, Place
Design Intent Synthesis Floorplanning Clock Extraction Analysis
DFT
Route

Converts high Organizes blocks

level description based on timing DRC/LVS
language into and connectivity
physical gates Makes the physical
connections
Design Rule Check (DRC)
Register Transfer Level (RTL) is a form of a source Layout Versus Schematic (LVS)
code to describe the chip’s functionality Output: GDS TO
Graphic Database System (GDS) is the to the foundry
geometrical information of device and metal
layers released to foundries for silicon
What is Timing Analysis & Closure?

Timing Analysis: Verification methods to compute minimum speed of a circuit under all operating
conditions.

Timing Closure: Digital design changes to achieve a specified speed for a circuit under all operating
conditions.

RTL / Synthesis

Timing Signoff
Physical
Operation
implementation

Technology
What is Transistor?
• A semiconductor device to amplify or to switch the electrical
signals and power.
• It is one of the basic building blocks of any electronics
component.
Evolution of Transistor
Transistor operations (I)
• Complimentary Metal Oxide Semiconductor (CMOS)
• Feature size: 3um (3000nm) à 5nm
• Approximately 600x reduction in approximately 40 years
• Very less static power consumption compared other transistor types
• High packing densities
• Relative easy design, integration and manufacturing process
• CMOS is an electronic switch
• PMOS passes a strong 1
• NMOS passes a strong 0
Transistor operations (II)

VDD = 1
VSS = 0
(i.e. Binary logic)

Cross-section of transistor *
* Reference: https://www.researchgate.net/figure/Conventional-planar-CMOS-transistor-and-FinFET-IV-PROPOSED-APPROACH-A-Schmitt-Trigger_fig4_332470054
Building blocks of System On Chip (aka SoC)
● Digital Logic gates built using transistor
● Two stable state (i.e. 1 or 0, High or Low, Vdd or Gnd),
● Combinational cells like AND, NAND, OR, XOR etc propagate stage change from
input pin to output pin with some delay
● Sequential Cells like Flop, Latch etc store state when clock, a signal to
coordinate is not active.
● Memory Macros , Analog or mix signal IPs like PLL, ADC. IO pad

Fig1 : Digital logic

Fig2 : Components of a SoC
Logic gates/Combinational paths
• A logic gate is an elementary building block of a digital circuit
• Logic gates have one or more inputs and produces one more outputs
• At any given moment, every terminal (input/output) is in one of two
binary states – low (0) or high (1) represented by different voltage
levels
• In most logic gates/circuits, the low state is VSS (0V) and the high state is VDD
(depending on process technology)
• Most common primitive combinational logic gates:
• INV (NOT), NAND, NOR, AND, OR, XOR, and XNOR
Inverter

Symbol
Schematic Truth Table
NAND
NOR
Transmission gate (aka pass gate)

X = input
f = output
S’ = INV(S)
S =1, f = X
S =0, f = Tristate
Transmission gates
• Faster then ‘traditional’ logic
gates
• Uses fewer transistors
• But lacks drive and must be
careful with charge sharing
• More difficult to layout
Other combination cells
• Xor
• Xnor
• Mux
• AOI
• OAI
• One bit Adder
•…
• ..
Propagation Delay
• Delay through transistor = f(input_slew, output_load)
• Typically measured at 50% of input to 50% of output
Combinational Circuits
• Combinational logic (sometimes also referred to as time independent
logic) is where the output is a pure function of the present state of
the inputs
• Combinational logic/circuits have no memory
• The output does NOT depend on the history of input
• A combination of logic gates to perform a Boolean function
• Half adders, full adders, etc…

Sum = A ⊕ B ⊕ Cin
Cout = A * B + Cin (A ⊕ B )
Delay of single cell

Low to High logic delay Tlh = f ( Rp, CDp )

High to Low logic delay Thl = f ( Rn, CDn )

RC equivalent circuit
of an inverter
Combinational gate delay timing arcs

Inverting = Negative Unate

Non-inverting = Positive Unate
Rise/fall time (aka slew)
• Rise/fall time is the time taken by a signal to change from a low (or
high) value to a high (or low) value
• Typically measured at 10% to 90% or 20% to 80%
• Usually the most linear portion of the waveform
• Tools interpolate to 0 – 100%
Sequential Elements
• Level Trigger: Latches

fig 1: Negative level latch fig 2: Waveform of positive level latch

• Edge Trigger: Flop Flops

fig 3: Positive edge flop fig 2: Waveform of positive edge flop

Sequential Circuits
• Output depends on the present and past values of its inputs
• Contrast this to combinational logic whose outputs is a function of only the present
input.
• Sequential logic has state (more memory) while combinational logic does not or in
other words, sequential logic is combinational logic with memory.
• Synchronous sequential logic
• Most of sequential logic today is synchronous – or controlled by a clock
• The basic memory element is the flip flop (the output of the flip flop only changes
when triggered by the clock
• Thus, the entire logic all begin at the same time, at regular intervals, synchronized by
the clock
• Asynchronous sequential logic
• Does not depend on a clock but just the changes to its inputs
• Can be faster than synchronous logic but much more difficult to design
Setup/hold/Tcq
• Setup = data must be stable (not
transitioning) when clock arrives
• Hold = data must be stable after
the clock arrives so the next stage
can latch the data
• Tcq = CLK-to-Q, the delay from
when clock (CLK) arrives to when Q
is available
 Timing Characterization
• Generation of timing models (TM) of std cells, IO Pads, or custom IPs to
encompass delay, function, capacitance , and other attributes.

Input Transition
Output Load

• Characterization tools take user defined input waveforms & perform various
transistor level circuit simulations under several conditions to generate
circuit responses of specified criteria.
• Generated measurement undergoes data processing to produce timing
models which are used by implementation and analysis tools.
Flop timing characterization
• Vary the output pin Load and transition time of clock pin to measure
the clock to q delay.

• For setup & hold time measurement vary the input transition of data
and clock pin and criteria should be degradation of Tcq delay. (i.e.
delay of Clock to Q)
Some Attributes in Timing Model
• Look up table of Cell Propagation Vin

Delay between input & output

• Look up table of Output
50%

transition time t t
t

pHL pLH
• Input pin capacitance Vout
90%

• Look up table of Setup & hold arc 50%

for sequential cell 10% t
• Other pin conditions tf tr

• Function or State table

Some Key things to Note for cell delay
• Mobility of NMOS > Mobility of PMOS
- Roughly in the order between 2 & 3.
- Hence PMOS is scaled around 2 to 3 time bigger compared to NMOS to match
the rise/fall delay

• Temperature Inversion for 90 nm and lower process node:

- Threshold voltage of transistor increase as temp decrease
- Mobility of transistor decrease as temp increase
- Cell Delay is depend on Mobility & Threshold Voltage.
• Characterized library consists of multiple drive strength of a particular
standard cell for example: Buffer (2x, 4x, 6x, 8x, 12x)
Types of Delay model
• Non Linear Delay Model (aka NLDM). Widely used for 45 nm higher
process technology nodes

• Composite Current Source (aka CCS) from Synopsys

OR
Effective Current Source Model (aka ECSM) from Cadence
Current source models are recommended to use for 20 nm and below
process technology nodes due to delay & capacitance accuracy
Example of NLDM
Timing Path in Digital circuits

● Logic gates coordinate through a clock signal that oscillates

at regular interval.
● Longest delay between sequential cells through
combinational gate dictates the clock frequency.
Lab #1 – due at the beginning of next lecture
• Log on to student accounts using x2go or global VPN
• Reach out Andrew Lee alee99@ucsc.edu for any IT question
• Copy the directory
/home/jdshah/spring_2024_tc_labs/lab1
and refer lab_excercise.txt file.
- Characterize delay arcs of an Inverter.
- Characterize constraint arcs of a flop.
Thank You
Backup Slides
REF: https://www.semiwiki.com/forum/content/3084-
handel-jones-predicts-process-roadmap-slips.html
FINFETs è Gate Capacitance Increases
è Leakage Improvement
è FinFETs
è ~ 40% faster
è less than ½ dynamic power
è cuts static leakage current by > 60%.

Gate

Source Drain
 Structure of Transistor

Structure of a planar NMOS

Structure of a FinFet NMOS

Width of Channel = 2 X Fin Height + Fin Width

Structure of a Multi FinFet NMOS

Cell delay (aka gate delay)
• Cell delay is a function of
both input slew and
output load
• Input slew increases the
Vgs which in effect turns
on the transistor stronger
and stronger
• Gate delay is proportional
to its output capacitance
(output load which is a
combination of metal
routes and input gates)
Cell delay of cascaded gates
Sequential Check & Delay