FTP16N06B

N-Channel MOSFET Pb Lead Free Package and Finish

Applications:
• Automotive VDSS RDS(ON) (Typ.) ID
• DC Motor Control 60V 13 m: 65A
• Class D Amplifier
• Uninterruptible Power Supply (UPS)

Features: D
• RoHS Compliant
• Low ON Resistance
• Low Gate Charge
• Peak Current vs Pulse Width Curve
G

G
Ordering Information D
S
S
Package
PART NUMBER PACKAGE BRAND Not to Scale
FTP16N06B TO-220 IPS

Absolute Maximum Ratings TC=25 oC unless otherwise specified

Symbol Parameter Maximum Units
VDSS Drain-to-Source Voltage (NOTE *1) 60 V
ID Continuous Drain Current 65
o
ID@ 100 C Continuous Drain Current Figure 3 A
IDM Pulsed Drain Current, VGS@ 10V (NOTE *2) Figure 6
Power Dissipation 170 W
PD o o
Derating Factor above 25 C 1.14 W/ C
VGS Gate-to-Source Voltage ± 20 V
Single Pulse Avalanche Engergy
EAS 700 mJ
L=1mH
IAS Pulsed Avalanche Rating Figure 8
dv/dt Peak Diode Recovery dv/dt (NOTE *3) 5.0 V/ns
Maximum Temperature for Soldering
TL Leads at 0.063in (1.6mm) from Case for 10 seconds 300
TPKG Package Body for 10 seconds 260 o
C
Operating Junction and Storage
TJ and TSTG -55 to 175
Temperature Range
Caution: Stresses greater than those listed in the “Absolute Maximum Ratings” Table may cause permanent damage to the device.

Thermal Resistance
Symbol Parameter Maximum Units Test Conditions
Water cooled heatsink, PD adjusted for
RTJC Junction-to-Case 0.88 o
o
C/W a peak junction temperature of +175 C.
RTJA Junction-to-Ambient 62 1 cubic foot chamber, free air.

©2013 InPower Semiconductor Co., Ltd. Page 1 of 9 FTP16N06B REV. A. Jun. 2013
 o
OFF Characteristics TJ=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
BVDSS Drain-to-Source Breakdown Voltage 60 -- -- V VGS=0V, ID=250μA
o
BreakdownVoltage Temperature o Reference to 25 C,
'BVDSS /' TJ -- 0.06 -- V/ C
Coefficient, Figure 11. ID=250μA

-- -- 1.0 VDS=60V, VGS=0V

IDSS Drain-to-Source Leakage Current μA
VDS=48V, VGS=0V
-- -- 100 o
TJ=150 C
Gate-to-Source Forward Leakage -- -- 100 VGS=+20V
IGSS nA
Gate-to-Source Reverse Leakage -- -- -100 VGS= -20V

ON Characteristics TJ=25 oC unless otherwise specified

Symbol Parameter Min. Typ. Max. Units Test Conditions
Static Drain-to-Source On-Resistance VGS=10V, ID=40A
RDS(ON) -- 13 16 m:
Figure 9 and 10. (NOTE *4)
VGS(TH) Gate Threshold Voltage, Figure 12. 2.0 -- 4.0 V VDS=VGS, ID=250uA
VDS=15V, ID=40A
gfs Forward Transconductance -- 62 -- S
(NOTE *4)

Dynamic Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
Ciss Input Capacitance -- 1780 -- VGS=0V
Coss Output Capacitance -- 360 -- VDS=25V
pF
f =1.0MHz
Crss Reverse Transfer Capacitance -- 100 --
Figure 14
Qg Total Gate Charge -- 42 -- VDD=30V
Qgs Gate-to-Source Charge -- 9.0 -- nC ID=30A
Qgd Gate-to-Drain (“Miller”) Charge -- 13 -- Figure 15

Resistive Switching Characteristics Essentially independent of operating temperature

Symbol Parameter Min. Typ. Max. Units Test Conditions
td(ON) Turn-on Delay Time -- 17 -- VDD=30V
trise Rise Time -- 61 -- ID=30A
ns
td(OFF) Turn-Off Delay Time -- 45 -- VGS=10V
tfall Fall Time -- 26 -- RG=9.1:

©2013 InPower Semiconductor Co., Ltd. Page 2 of 9 FTP16N06B REV. A. Jun. 2013
 o
Source-Drain Diode Characteristics Tc=25 C unless otherwise specified
Symbol Parameter Min. Typ. Max. Units Test Conditions
IS Continuous Source Current (Body Diode) -- -- 65 A Integral pn-diode
ISM Maximum Pulsed Current (Body Diode) -- -- 260 A in MOSFET
VSD Diode Forward Voltage -- -- 1.5 V IS=40A, VGS=0V
trr Reverse Recovery Time -- 125 -- ns VGS=0V, VDD=-30V
Qrr Reverse Recovery Charge -- 250 -- nC IF=30A, di/dt=100 A/μs

Notes:

*1. TJ = +25 oC to +175 oC.

*2. Repetitive rating; pulse width limited by maximum junction temperature.
*3. ISD= 65A di/dt < 100 A/μs, VDD < BVDSS, TJ=+175oC.
*4. Pulse width < 380μs; duty cycle < 2%.

©2013 InPower Semiconductor Co., Ltd. Page 3 of 9 FTP16N06B REV. A. Jun. 2013
 Duty Factor Figure 1. Maximum Effective Thermal Impedance, Junction-to-Case
1.000
50%
20%
ZTJC, Thermal Impedance

10%
0.100
5%
(Normalized)

2%
0.010 PDM
1%
t1
t2
0.001
NOTES:
single pulse DUTY FACTOR: D=t1/t2
PEAK TJ=PDM x ZTJC x RTJC+TC

0.0001
1E-6 10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0

tp, Rectangular Pulse Duration (s)

Figure 2. Maximum Power Dissipation Figure 3. Maximum Continuous Drain Current

vs Case Temperature vs Case Temperature

200 80

175 70
PD, Power Dissipation (W)

ID, Drain Current (A)

150 60

125 50

100 40

75 30

50 20

25 10

0 0
25 50 75 100 125 150 175 25 50 75 100 125 150 175

TC, Case Temperature (oC) TC, Case Temperature (oC)

Figure 4. Typical Output Characteristics Figure5. Typical Drain-to-Source ON Resistance

vs Gate Voltage and Drain Current

150 0.065
PULSE DURATION = 10 μS
VGS = 10V
15V

DUTY FACTOR = 0.5% MAX

PULSE DURATION = 10 μS
RDS(ON), Drain-to-Source

TC = 25 oC
S=

125 DUTY FACTOR = 0.5% MAX, 0.052

ID, Drain Current (A)

VG

TC = 25 oC
ON Resistance (:

100 ID = 120A
VGS = 8.0V
0.039 ID = 65A
75 ID = 40A
VGS = 7.0V
ID = 10A
0.026
50
VGS = 6.0V
VGS = 5.5V 0.013
25
VGS = 5.0V
VGS = 4.5V
0 0.000
0 2 4 6 8 10 12 14 16 18 20 4 6 8 10 12 14 16
VDS, Drain-to-Source Voltage (V) VGS, Gate-to-Source Voltage (V)

©2013 InPower Semiconductor Co., Ltd. Page 4 of 9 FTP16N06B REV. A. Jun. 2013
 Figure 6. Maximum Peak Current Capability
1000
TRANSCONDUCTANCE FOR TEMPERATURES
MAY LIMIT CURRENT IN ABOVE 25 oC DERATE PEAK
THIS REGION CURRENT AS FOLLOWS:
IDM, Peak Current (A)

 – 7
, = ,  --------------------&-


100

VGS = 10V

10
10E-6 100E-6 1E-3 10E-3 100E-3 1E+0 10E+0

tp, Pulse Width (s)

Figure 7. Typical Transfer Characteristics Figure 8. Unclamped Inductive

Switching Capability
300 1000
PULSE DURATION = 10 μs
ID, Drain-to-Source Current (A)

DUTY CYCLE = 0.5% MAX

IAS, Avalanche Current (A)

250 VDS = 30 V

200 100
STARTING TJ = 25 oC
+175 oC
150 +25 oC
-55 oC STARTING TJ = 150 oC

100 10

f R= 0: tAV= (L×IAS)/(1.3BVDSS-VDD)
50
f Rz 0: tAV= (L/R) ln[IAS×R)/(1.3BVDSS-VDD)+1]
R equals total Series resistance of Drain circuit
0 1
2 3 4 5 6 7 8 9 10 1E-6 10E-6 100E-6 1E-3 10E-3

VGS, Gate-to-Source Voltage (V) tAV, Time in Avalanche (s)

Figure 9. Typical Drain-to-Source ON Figure 10. Typical Drain-to-Source ON Resistance

Resistance vs Drain Current vs Junction Temperature
0.048 2.5
PULSE DURATION = 10 μs
DUTY CYCLE = 0.5% MAX
RDS(ON), Drain-to-Source
RDS(ON), Drain-to-Source

Resistance (Normalized)

TC=25°C
2.0
ON Resistance (:)

0.032

V = 10V
GS 1.5

V = 20V
0.016 GS
1.0
PULSE DURATION = 10 μs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 40A
0.005 0.5
0 40 80 120 160 200 240 -75 -50 -25 0 25 50 75 100 125 150 175

ID, Drain Current (A) TJ, Junction Temperature (oC)

©2013 InPower Semiconductor Co., Ltd. Page 5 of 9 FTP16N06B REV. A. Jun. 2013
 Figure 11. Typical Breakdown Voltage vs Figure 12. Typical Threshold Voltage vs
Junction Temperature Junction Temperature
1.15 1.2
Breakdown Voltage (Normalized)

VGS(TH), Threshold Voltage

1.1
BVDSS, Drain-to-Source

1.10
1.0

(Normalized)
1.05
0.9

1.00 0.8

0.7
0.95
VGS = 0V 0.6 VGS = VDS
ID = 250 μA ID = 250 μA
0.90 0.5
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175

TJ, Junction Temperature (oC) TJ, Junction Temperature (oC)

Figure 13. Maximum Forward Bias Safe Figure 14. Typical Capacitance vs
Operating Area Drain-to-Source Voltage

1000 10000

Ciss
ID, Drain Current (A)

C, Capacitance (pF)

100 1000
10μs Coss

1ms
10 OPERATION IN THIS AREA 100
MAY BE LIMITED BY R VGS = 0V, f = 1MHz Crss
DS(ON) 10ms Ciss = Cgs + Cgd
TJ = MAX RATED DC Coss # Cds + Cgd
TC = 25 oC Single Pulse Crss = Cgd
1 10
1 10 100 0.1 1 10 100

VDS, Drain-to-Source Voltage (V) VDS, Drain Voltage (V)

Figure 15. Typical Gate Charge Figure 16. Typical Body Diode Transfer
vs Gate-to-Source Voltage Characteristics
12 300
VGS, Gate-to-Source Voltage (V)

ISD, Reverse Drain Current (A)

10 VDS = 15V 250

VDS = 30V
8 VDS = 40V 200

6 150
+175 oC
+25 oC
4 100

2 50
ID = 30A VGS = 0V
0 0
0 10 20 30 40 50 60 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

QG , Total Gate Charge (nC) VSD, Source-to-Drain Voltage (V)

©2013 InPower Semiconductor Co., Ltd. Page 6 of 9 FTP16N06B REV. A. Jun. 2013
 Test Circuits and Waveforms

VDS
ID
ID
VDS VGS
Miller
Region
VGS
VDD
D.U.T.
VGS(TH)

1 mA
Qgs Qgd
Qg

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveform

VDS
RL 90%
VDS

VGS
VDD
RG D.U.T.
10%
VGS

td(ON) trise td(OFF) tfall

Figure 19. Resistive Switching Test Circuit Figure 20. Resistive Switching Waveforms

©2013 InPower Semiconductor Co., Ltd. Page 7 of 9 FTP16N06B REV. A. Jun. 2013
 Test Circuits and Waveforms

di/dt adj. Current

Pump

di/dt = 100A/μA
ID
Double Pulse

D.U.T. VDD
Qrr
L
trr

ID

Figure 22. Diode Reverse Recovery Waveform

Figure 21. Diode Reverse Recovery Test Circuit

BVDSS

Series Switch
(MOSFET)
L
IAS

BVDSS

D.U.T. VDD VDD

Commutating
Diode
0 tAV

VGS 50:
IAS
VGS tp

I AS 2 L
E AS
2

Figure 23. Unclamped Inductive Switching Test Circuit Figure 24. Unclamped Inductive Switching Waveforms

©2013 InPower Semiconductor Co., Ltd. Page 8 of 9 FTP16N06B REV. A. Jun. 2013
 Disclaimers:
InPower Semiconductor Co., Ltd (IPS) reserves the right to make changes without notice in order to improve reliability, function
or design and to discontinue any product or service without notice. Customers should obtain the latest relevant information before
orders and should verify that such information is current and complete. All products are sold subject to IPS’s terms and conditions
supplied at the time of order acknowledgement.

InPower Semiconductor Co., Ltd warrants performance of its hardware products to the specifications at the time of sale, Testing,
reliability and quality control are used to the extent IPS deems necessary to support this warrantee. Except where agreed upon
by contractual agreement, testing of all parameters of each product is not necessarily performed.

InPower Semiconductor Co., Ltd does not assume any liability arising from the use of any product or circuit designs described
herein. Customers are responsible for their products and applications using IPS’s components. To minimize risk, customers must
provide adequate design and operating safeguards.

InPower Semiconductor Co., Ltd does not warrant or convey any license either expressed or implied under its patent rights, nor
the rights of others. Reproduction of information in IPS’s data sheets or data books is permissible only if reproduction is without
modification or alteration. Reproduction of this information with any alteration is an unfair and deceptive business practice.
InPower Semiconductor Co., Ltd is not responsible or liable for such altered documentation.

Resale of IPS’s products with statements different from or beyond the parameters stated by InPower Semiconductor Co., Ltd
for that product or service voids all express or implied warrantees for the associated IPS’s product or service and is unfair and
deceptive business practice. InPower Semiconductor Co., Ltd is not responsible or liable for any such statements.

The device is electrostatic sensitive. Proper electrostatic discharge (ESD) protection shall be implemented to avoid damaging
the device.

Life Support Policy:

InPower Semiconductor Co., Ltd’s products are not authorized for use as critical components in life support devices or
systems without the expressed written approval of InPower Semiconductor Co., Ltd.

As used herein:
1. Life support devices or systems are devices or systems which:
a. are intended for surgical implant into the human body,
b. support or sustain life,
c. whose failure to perform when properly used in accordance with instructions
for used provided in the labeling, can be reasonably expected to result in significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

©2013 InPower Semiconductor Co., Ltd. Page 9 of 9 FTP16N06B REV. A. Jun. 2013