UNITS MICRO OPERATIONS Each instruction cycle is made up of a number of smaller units. One subdivision that we found convenient is fetch, indirect, execute, and interrupt, with only fetch and execute cycles always occurring, Each of the smaller cycles involves aseries of steps,each of which involves the processor registers. We will refer to these steps as micro-operations The prefix micro refers to the fact that each step is very simple and accomplishes very little Following Figure depicts the relationship among the various concepts we have been discussing, To summarize, the execution of a program consists of the sequential execution of instructions. Each instruction is executed during an instruction cycle made up of shorter subcycles (e.g,,fetch, indirect, execute jnterrupt).The execution of each subcycle involves one or more shorter operations that is micro-operations. Program Esccution Instruction Cyele] — [instruedion Cyee tee Instruction Cyte Feich_] [inate] [[Bxecuie ] [interran AX or] OF] HOF] Fig: Constituent Elements of a Program Execution Micro-operations are the functional,or atomic operations of a processor The Fetch Cycle which occurs at the beginning of each instruction cycle and causes an instruction to be fetched from memory Mainly 4 registers are involved in fetch cycle + Memory Address Register (MAR) Connected to address bus ~Specifies address for read or writ operation + Memory Buffer Register (MBR) ~Connected to data busHolds data to write to memory or last data read from memory Program Counter (PC) Holds address of next instruction to be fetched Instruction Register (IR) “Holds last instruction fetched Fetch Sequence Address of next instruction is in PC ‘Address moved to MAR ‘Address of MAR is placed on address bus Control unit issues READ command Result (data from memory) appears on data bus Data from data bus copied into MBR PC incremented by 1 (in parallel with data fetch from memory) Data (instruction) moved from MBR to IR MBR is now free for further data fetches Fetch Sequence (symbolic) tl: MAR <-(PC) 12: MBR< (memory) PC <- (PC) +1 3: IR<-(MBR) (tx= time unit/clock cycle) or th: MAR <- (PC) 12: MBR< (memory) 13: PC<- (PC) +1 I< (MBR)The Indirect Cycle Once an instruction is fetched, the next step is to fetch source operands. If the instruction specifies an indirect address, then an indirect cycle must precede the execute cycle In case of a one address instruction using indirect mode of addressing following are the micro- operations: + MAR <: (IRaddress) - address field of IR + MBR <: (memory) + IRaddress <- (MBRaddress) The address field of the instruction is transferred to the MAR.This is then used to fetch the address of the operand. Finally, the address field of the IR is updated from the MBR;so that it now contains a direct rather than an indirect address. The IR is now in the same state as if indirect addressing had not been used, and it is ready for the execute cycle.We skip that cycle for a moment,to consider the interrupt cycle. The Interrupt Cycle ‘At the completion of the execute cycle,a test is made to determine whether any enabled interrupts have occurred. If so, the interrupt cycle occurs.The nature of this cycle varies greatly from one machine to another MBR <(PC) + 12: MAR < save-address ( address to which contents of PC are to be saved) PC <- routine-address memory <- (MBR) In the first step,the contents of the PC are transferred to the MBR,so that they can be saved for return from the interrupt.Then the MAR is loaded with the address at which the contents of the PC are to be saved,and the PC is loaded with the address of the start of the interrupt-processing routine, These two actions may each be a single micro-operation, However, because most processors provide multiple types and/or levels of interrupts, it may take one or more additional micro-operations to obtain the Save_Address and the Routine_Address before they can be transferred to the MAR and PC, respectively. In any case, once this is done, the final step is to store the MBR,which contains the old value of the PC,into memory. he processor is now ready to begin the next instruction cycle.The Execute Cycle ‘The fetch, indirect, and interrupt cycles are simple and predictable. Each involves a small fixed sequence of micro-operations and,in each case,the same micro-operations are repeated each time around. This not true of the execute cycle. Because of the variety opcodes,there are a number of different sequences of micro-operations that can occur Let us consider several hypothetical examples. First consider an add instruction: ADD R1, X which adds the contents of the location X to register R1.The following sequence of micro-operations might occur: U1: MAR € (IR(eddress)) ti : MBR & Memory £3: R1 © (RI) + (MBR) We begin with the IR containing the ADD instruction.In the first step,the address portion of the IR is loaded into the MAR.Then the referenced memory location is read.Finally,the contents of R1. and MBR are added by the ALU.Again,this is a simplified example Additional micro-operations may be required to extract the register reference from the IR and perhaps to stage the ALU inputs or outputs in some intermediate registers. A common instruction is increment and skip if zero: Iszx The content of location X is incremented by 1.if the result is 0,the next instruction is skipped.A possible sequence of micro-operations is t1: MAR € (IR(address)) 12: MBR & Memory 13: MBR € (MBR) +1 +4: Memory € (MBR) UF (MR) ) then (PC © (PC) +1) ‘The new feature introduced here is the conditional action. The PC is incremented if This test and action can be implemented as one micro-operation.Note also that this micro-operation can be Performed during the same time unit during which the updated value in MBR is stored back to memory.FUNCTIONAL REQUIREMENTS Functional Requirements are those functions that the control unit must perform.A definition of these functional requirements is the basis for the design and implementation of the control unit. The following three-step process leads to a characterization of the control unit: a) Defining the basic elements of the CPU b)_ Defining the micro-operations the CPU performs ) Determining the functions the control unit must perform to cause the execution of the micro-operations in the desired time sequence — Sequencing — Execution the basic functional elements of the processor are the following: alu + Registers sInternal data paths + External data paths * Control unit The ALU is the functional essence of the computer Registers are used to store data internal to the Processor.Some registers contain status information needed to manage instruction sequencing (e.g., a program status word). Others contain data that go to or come from the ALU, memory,and 1/0 modules.internal data paths are used to move data between registers and between register and ALU.External data paths link registers to memory and I/O modules,often by means of a system bus.The control unit causes operations to happen within the processor. The execution of a program consists of operations involving these processor elements. All micro-operations fall into one of the following categories: * Transfer data from one register to another. + Transfer data from a register to an external interface (e.g.,system bus). + Transfer data from an external interface to a register. ‘+ Perform an arithmetic or logic operation, using registers for input and outputThe control unit performs two basic tasks: + Sequencing: The control unit causes the processor to step through a series of micro-operations in the proper sequence, based on the program being executed. * Execution: The control unit causes each micro-operation to be performed. The key to how the control unit operates is the use of control signals. @ General layout of a control unit is shown below Tratraion Rainer | | u Conte Signate Wit CPU met = ‘Control Signals Control from System Bee nit cok | Consiga fesyemm oe Coa Ben ‘Clock: This is how the control unit “keeps time.”The control unit causes one micro-operation (or a set of simultaneous micro-operations) to be performed for each clock pulse. his is sometimes referred to as the processor cycle time, or the clock cycle time. ‘Instruction register: The opcode and addressing mode of the current instruction are used to determine which micro-operations to perform during the execute cycle. + Flags: These are needed by the control unit to determine the status of the processor and the outcome of previous ALU operations.For example,for the increment-and-skip-if-zero (ISZ) instruction, the control unit will increment the PC if the zero flag is set. + Control signals from control bus: The control bus portion of the system bus provides signals to the control unit. The outputs are as follows: + Control signals within the processor: These are two types: those that cause data to be moved from one register to another and those that activate specific ALU functions. * Control signals to control bus: These are also of two types: control signals to memory,and control signals to the /O modulesControl Uni ‘The basie tack of the centro! unit: = for each instruction the control unit causes the CPL to ga througn # sequence of central steps: in each control step the control unit issues 2 set of signals which cause the corresponding micrsoperations to ne svacutea + The contro! unit ie driven by the presescor clock, The signals to be generated at a certain moment depene on: = the actual step to be executed: ~ the condition and status flags of the processor = the actual instruction executed: ~ external signals received on the system bus (e.g. interrupt signals). Controt Unit (contey }iemnatte tie Geo | ‘Sn System Sus, | StosdCond Fag sl Sarees Oo 2. Microprogrammed contro! Control Unit Implementation For control unit implementation , a wide variety of techniques have been used . Its divided into two categories: > — Hardwired Implementation > — Micro programmed implementationHardwired Implementation Hardwired Control clreult Itgets a set of inputs (from IR, fisgs. clock, System bus) and wanstorms tem into a sei ot Soatrel sionals oe puree tees Bete] most. IT at gs 7 generator) == Bele CE}Es Z pales Hardwired Control (cont'd) + Hardwired control provides highest speed. + RISCs are implemented with hardwired control + Ifthe instruction set becomes very complex (CISCs) implementing hardwired contral is very difficult. In this case microprogrammed control units are used. Ina hardwired implementation, the control unit is essentially a state machine circult.tts input logic signals are transformed into a set of output logic signals,which are the control signalsos nig Se} > arate nT Cont ge The key inputs are the instruction register,the clock, flags,and control bus signals.in the case of the flags and control bus signals, each individual bit typically has some meaning (e.g., overflow).The other two inputs,however,are not directly useful to the control unit. First consider the instruction register.The control unit makes use of the opcode and will perform different actions (issue a different combination of control signals) for different instructions To simplify the control unit logic, there should be a unique logic input for each opcode. This function can be performed by a decoder, which takes an encoded input and produces a single output The clock portion of the control unit issues a repetitive sequence of pulses. This is useful for measuring the duration of micro-operations as we have seen, the control unit emits different control signals at different time units within a single instruction cycle. Thus,we would like a counter as input to the control unit,with a different control signal being used for and so forth.At the end of an instruction cycle,the control unit must feed back to the counter to reinitialize it at T1 Problems with Hardwired Implementation + Sequencing & micro-operation logic gets complex + Difficult to design, prototype, and test. + Adding new instructions requires major design and adds complexity quickly. Microprogrammed Control "A sequence of instructions is known as a Micro program.10 SH The language which is used to write instruction is known as Micro Programming Language. °@Aninstruction is known as Micro Instruction Control Atarans Regatar | The set of microinstructions is stored in the Control Memory. | The control address register contains the address of the next microinstruction to be read from the control memory and transferred to a control buffer register. | Asequencing unit that loads the control address register and issue a read command. aw AY tet Cakasioas Or Sana ‘vi CPU te Sande The control unit functions as follows: “To execute an instruction , the sequencing logic unit issues a READ command to the control memory.i 4 The word whose address is specified in the control address registers is read into the control buffer register. ‘The content of the control buffer register generates control signals and next address information for the sequencing logic unit. The sequencing logic unit loads a new address into the control address register based on the next address information from the control buffer register and the ALU flags. a The upper decoder translates the opcode of the IR into a control memory address. a The lower decoder is used in vertical microinstructions. Allthis happen during one clock pulse. Depending on the value of the ALU flags and the control buffer register, one of three decisions is made: Get the next instruction : Add 1 to the control address register. Jump to a new routine based on a jump microinstruction : Load the address field of the control buffer register into the control address register. Jump to a machine instruction routine : Load the control address register based on the opcode in the IR Advantages : SG. The principle advantage of the use of microprogramming to implement a control unit is that it simplifies the design of control unit. SW It is both cheaper and less error prone to implement. WW The decoders and sequencing logic unit of a micro programmed control unit are vary simple piece of logic. Disadvantages 4k tis slower than hardwired unit of comparable technology. Microinstruction Basic Tasks The two basic tasks performed by a micro programmed control unit are as follows : Microinstruction Sequencing : Get the next microinstruction from the control memory. Microinstruction Execution : Generate the control signals needed to execute the microinstruction12 Summary Control units can be implemented hardwired or microprogrammed. ‘A hardwired control unit is a combinatorial circuit which gets a set of inputs and transforms them into a set of control signals. ‘A microprogrammed control unit is implemented like another CPU in: executes microprogrammes stored in the control store. fe the CPU. It Each instruction of the microprogram practically represents the set of signals which the control unit has to issue in the respective control step. Hardwired controllers are faster then microprogrammed ones. They are used in all RISCs. If the instruction set is complex, hardwired controllers become too complicated. Therefore CISCs are implemented with microprogrammed controllers.