CHAPTER Three
CONTROL UNIT
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O UTLINE
3.1 Introduction
3.2 Micro-operations
3.3 Control Unit
Functional Requirements
Inputs
Outputs
Control Signals
3.4 Control Unit
Implementation
Hardwired Control Unit
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3.1 I NTRODUCTION
In Chapter 2, seen:
Machine instructions
Operations performed by the processor to execute
each instruction
But how exactly each individual operation
is caused to happen ?
The job of the Control Unit
The control unit
Portion of the processor that actually causes things
to happen by
Issuing a control signal
Internal as well as external to the processor
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3.2 M ICRO -O PERATIONS
A computer executes a program
Consists of a sequence of instruction cycles
Instruction cycle
Consists of the following smaller cycles
Fetch/indirect/execute/interrupt cycle
Each cycle in turn, involves a series of steps
These steps are called micro-operations
A single micro-operation does very little and
generally involves either of the following
A transfer between registers
A transfer between a register and an external bus or
A simple ALU operation
Atomic operation of CPU 4
M ICRO -O PERATIONS ...
A diagram showing the relationship among
the concepts discussed so far
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M ICRO -O PERATIONS ...
In the next sections, we will see
How the events of any instruction cycle
ca n be described as a sequence of micro
operations
How the concept of micro operations serve as a
guide to the design of the control unit
-written sequence of instructions vs execution time
sequence of instructions
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M ICRO -O PERATIONS ...
Fetch cycle
Sequence of events, seen from point of view of its effects on
processor registers
First Step
To move the address from PC to MAR
Second Step
Overall effect is to bring in the instruction
Address (in the MAR) is placed on address bus
Control unit issues READ command
Result (data from memory) appears on d a ta bus
D ata from d ata bus copied into MBR
PC incremented by 1 (in parallel with d a ta fetch from memory)
Third Step
D ata (instruction) moved from MBR to IR 7
Fetch cycle
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M ICRO -O PERATIONS ...
Fetch cycle (symbolic)
t1: MAR (PC)
t2: MBR memory
PC (PC) +1
t3: IR (MBR)
Fetch cycle
Involves three steps and four µop
Note t h a t each µop involves movement of d a t a into or out of
a register
Several µops can be performed in one clock cycle, so
long as these movements do not interfere with one 8
another
M ICRO -O PERATIONS ...
Assumptions
A clock is available for timing purpose
It emits regularly spaced clock pulses
Each clock pulse defines a time unit
Each single micro operation can be performed within
a time of a single time unit
Nota tions t 1,t2 and t 3 represen ts successive
tim e units
Note
The second an d third micro operations (µops) , both ,
takes place during the second time unit
The third µop could have been grouped 9
with the fourth without affecting the fetch operation
M ICRO -O PERATIONS ...
Rules for grouping of µops
Proper sequence of events mu st be followed
MAR (PC) must precede MBR (memory)
As memory read operation makes use of the address in
the MAR
Conflicts mu st be avoided
Must not read & write same register in one time unit
As the result would be unpredictable
MBR memory a nd IR (MBR) must not be in same
cycle
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M ICRO -O PERATIONS ...
Indirect Cycle
t1: MAR (IR[Address])
t2: MBR memory
t3: IR(Address)
(MBR[Address])
Note:
IR[Address]
Refers to the address field of the instruction
MBR contains a n address
IR is now in the same state as if direct addressing
had been used 11
M ICRO -O PERATIONS ...
Interrupt Cycle
t1 : MBR (PC)
t2: MAR Save_Address
PC Routine_Address
t3: memory (MBR)
Note:
Save_Address
The address a t which the contents of the PC are to be saved
Routine_Address
The starting address of the interrupt processing routine
This is a minimum
May be additional micro-ops to get addresses
The nature of this cycle varies greatly from one machine to
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another
M ICRO -O PERATIONS ...
Fetch, Indirect and Interrupt Cycles
Simple and predictable
E ach involves a sm all, fixed of micro
sequence operations
In each case, the same sequence of micro operations
repeated
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M ICRO -O PERATIONS ...
Execute Cycle
Different for each instruction
For a machine with N different opcodes
N different sequence of micro operation
Example:
ADD X, R1
(add the contents of location X to Register 1 , result in R1)
t1: MAR (IR[Address])
t2: MBR memory
t3: R1 (R1) + (MBR)
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M ICRO -O PERATIONS ...
Execute Cycle
Example:
ISZ X
(increment and skip if zero)
t 1: MAR (IR[Address])
t 2: MBR memory
t 3: MBR (MBR) + 1
t 4: memory (MBR)
if ((MBR) == 0) then
PC (PC) + 1
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M ICRO -O PERATIONS ...
So far we have seen
How the operation of the processor can be defined as
a sequence of micro operations
Next
How the control unit causes this sequence to occur
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3.3 C ONTROL U NIT
Functional Requirements
Functional requirements of the control unit,
those functions the control unit mu st perform,
Basis for the design a nd implementation of the
control unit
The control unit h as to perform two basic tasks
Sequencing
Cause the processor to step through a series of µops ,in
the proper sequence
Execution
Cause each µop to be performed
This is done using Control 18
Signals
C ONTROL U NIT ...
For the control u n it to perform its function,
it needs
Inputs
To determine the state of the system
Outputs
To control the behaviour of the system
The above are external specification of the
control unit
Internally the control unit
Must have the logic required to perform its
function 18
Sequencing
Execution
C ONTROL U NIT ...
Inputs
Clock
Used by control unit to keep time
One µops or a set of parallel µops occur per clock
cycle
Instruction register
Contains Op-code
Determines of current
which µops instruction
a re performed during th e
execute cycle
Flags
Used by control unit to determine the status of CPU
Also, to determine results of previous ALU operations
From control bus
Interrupts 19
Acknowledgements
C ONTROL U NIT ...
Outputs
Control signals within CPU
These are two types
Cause dat a movement
Activate specific ALU functions
Control signals to control bus
These are also two types
Control signals to memory
Control signals to I/O modules
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C ONTROL U NIT ...
Model of Control Unit
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C ONTROL U NIT ...
How does the control unit maintain control ?
Control signals
Example : consider the fetch cycle
Control unit generates the following control signals
MAR (PC)
Open gates between PC and MAR
MBR memory
Open gates between MAR and address bus
Memory read control signal
Open gates between data bus and MBR
Add 1 to contents of PC and store the result back to PC
IR (MBR) 22
Open gates between MBR and IR
C ONTROL U NIT ...
Data Pa t hs and
Control Signals
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C ONTROL U NIT ...
Maintains a knowledge of where it is in
the instruction cycle
Reads all of its inputs
Emits a sequence of control signals
That causes the right µops to occur at the
right time
The control unit is the engine that
runs the entire computer
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3.4 C ONTROL U NIT I MPLEMENTATION
Two ways to implement the control unit:
Hardwired Control Unit Implementation
Micro programmed Control Unit Implementation
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H ARDWIRED I MPLEMENTATION
The control unit is essentially a combinational
circuit
Its inputs logic signals are transformed into a set
of output logic signals which are the control
signals
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H ARDWIRED I MPLEMENTATION ...
Control Unit Inputs
Flags and control bus signals
Each individual bit typically h a s some meaning
The other two inputs (instruction register and clock) are
not directly useful to the control unit
Need to be modified as shown below
Instruction register
The control unit makes use of the opcode to issue different
combination of control signals for different instruction
To simplify the control unit logic, there should be a unique logic
input for each opcode
Performed by a decoder
A decoder with n binary inputs will have 2 n binary outputs
For any combination of inputs only on of its output is high 27
H ARDWIRED I MPLEMENTATION ...
Control Unit Inputs
Clock
Generates a repetitive sequence of pulses
Useful for measuring duration of micro-ops
The control unit emits different control signals a t different
times within instruction cycle
Realized using a counter as inputs to control unit
Which generates different control signals
• T1,T2,T3….
At the end of each instruction cycle, the control unit feeds
back to the counter to reinitialize it a t T1
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H ARDWIRED I MPLEMENTATION ...
Control Unit with Decoded
Inputs
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H ARDWIRED I MPLEMENTATION ...
Control Unit Internal Logic
Derive a boolean expression for each control signal as
a function of the inputs
Example:
Consider two control signals P a nd Q with the following
characteristics
PQ= 00 Fetch cycle
PQ=01 Indirect cycle
PQ=10 Execute cycle
PQ=11 Interrupt cycle
Then the boolean expression for C5 (a control signal t h a t
causes the d a t a to be read from the external d a t a bus into
MBR)
C5=P’Q’T2 + P’QT2
(C5 will be asserted during the second time unit of both the 30
fetch and indirect cycles)
H ARDWIRED I MPLEMENTATION ...
Control Unit Internal Logic
Repeat the above process for every control
signal generated by the CU
Result
A set of boolean equations th at define the behavior of the
control unit
Problems With Hardwired Designs
Complex sequencing & micro-operation logic
Difficult to design and test
Inflexible design
Difficult to add new instructions 31
Micro programmed Control Unit Implementation
(reading assignment)
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End of Chapter 3
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