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PCA9698

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PCA9698

40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
Rev. 3 — 3 August 2010 Product data sheet

1. General description
The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I2C-bus
applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable
of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct
driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output.

The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+
devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus
operation (up to 4000 pF).

The device is fully configurable: output ports can be programmed to be totem-pole or

open-drain and logic states can change at either the Acknowledge (bank change) or the
Stop Command (global change), each input port can be masked to prevent it from
generating interrupts when its state changes, I/O data logic state can be inverted when
read by the system master.

An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted
each time a change occurs in one or several input ports (unless masked).

The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an
input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle).

A ‘GPIO All Call’ command allows to program multiple Advanced GPIOs at the same time
even if they have different I2C-bus addresses. This allows optimal code programming
when more than one device needs to be programmed with the same instruction or if all
outputs need to be turned on or off at the same time (for example, LED test).

The Device ID, hard coded in the PCA9698, allows the system master to read
manufacturer, part type and revision information.

The SMBus Alert feature allows the SMBALERT pins of multiple devices with this feature
to be connected together to form a wired-AND signal and to be used in conjunction with
the SMBus Alert Response Address.

The internal Power-On Reset (POR) or hardware reset pin (RESET) initializes the 40 I/Os
as inputs. Three address select pins configure one of 64 slave addresses.

The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over
the −40 °C to +85 °C industrial temperature range.

2. Features and benefits

1 MHz Fast-mode Plus I2C-bus serial interface
Compliant with I2C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)
NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

40 configurable I/O pins that default to inputs at power-up
Outputs:
Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink)
with controlled edge rate output structure. Default to totem-pole on power-up.
Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be
programmed to active HIGH through the I2C-bus. Defaults to OE on power-up.
Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time respectively. Defaults to
Acknowledge on power-up.
Inputs:
Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs
Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change
Polarity Inverter register allows inversion of the polarity of the I/O pins when read
Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus ‘Alert
Response Address’ sequence. Own slave address sent when sequence initiated.
Active LOW Reset (RESET) input pin resets device to power-up default state
GPIO All Call address allows programming of more than one device at the same time
with the same parameters
64 programmable slave addresses using 3 address pins
Readable Device ID (manufacturer, device type and revision)
Designed for live insertion in PICMG applications
Minimize line disturbance (IOFF and power-up 3-state)
Signal transient rejection (50 ns noise filter and robust I2C-bus state machine)
Low standby current
−40 °C to +85 °C operation
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: TSSOP56, and HVQFN56

3. Applications
Servers
RAID systems
Industrial control
Medical equipment
PLCs
Cell phones
Gaming machines
Instrumentation and test measurement

Product data sheet Rev. 3 — 3 August 2010 2 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

4. Ordering information
Table 1. Ordering information
Tamb = −40 °C to +85 °C
Type number Topside mark Package
Name Description Version
PCA9698DGG PCA9698DGG TSSOP56 plastic thin shrink small outline package; 56 leads; SOT364-1
body width 6.1 mm
PCA9698BS PCA9698BS HVQFN56 plastic thermal enhanced very thin quad flat package; SOT684-1
no leads; 56 terminals; body 8 × 8 × 0.85 mm

5. Block diagram

PCA9698
IO0_0
IO0_1
8-bit INPUT/ IO0_2
AD0
ADDRESS OUTPUT IO0_3
AD1 PORTS
DECODER IO0_4
AD2
read pulse 0 BANK 0 IO0_5
write pulse 0 IO0_6
IO0_7
BANK 1
SCL LOW PASS
INPUT I2C-BUS/SMBUS BANK 2
SDA FILTERS CONTROL
BANK 3
IO4_0
IO4_1
8-bit INPUT/ IO4_2
OUTPUT IO4_3
VDD PORTS
IO4_4
POWER-ON read pulse 4 BANK 4 IO4_5
VSS
RESET IO4_6
write pulse 4
RESET IO4_7

INTERRUPT
MANAGEMENT

INT/SMBALERT
LP FILTER

002aab935

Remark: All I/Os are set to inputs at power-up and RESET.

Fig 1. Block diagram of PCA9698

Product data sheet Rev. 3 — 3 August 2010 3 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

configuration port register data (Cx[y])

output port register data (Ox[y])

OE
OEPOL
I/O
configuration VDD
register
data from
shift register D Q OUTx

FF
write configuration
CK Q
pulse
IOx_y

output port
register
data from
shift register D Q
D Q
FF Mx[y]
FF OCH
CK
write pulse CK
STOP INTERRUPT
pulse INT
MANAGEMENT

input port
register

D Q
input port
FF register data
(Ix[y])
read pulse CK

polarity inversion
register
data from
D Q polarity inversion
shift register
register data
FF (Px[y])
write polarity
pulse CK
002aab936

On power-up or RESET, all registers return to default values.

Fig 2. Simplified schematic of the I/Os (IO0_0 to IO4_7)

Product data sheet Rev. 3 — 3 August 2010 4 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

6. Pinning information

6.1 Pinning

SDA 1 56 RESET
SCL 2 55 INT/SMBALERT
IO0_0 3 54 IO4_7
IO0_1 4 53 IO4_6
IO0_2 5 52 IO4_5
VSS 6 51 VSS
IO0_3 7 50 IO4_4
IO0_4 8 49 IO4_3
IO0_5 9 48 IO4_2
IO0_6 10 47 IO4_1
VSS 11 46 VDD
IO0_7 12 45 IO4_0
IO1_0 13 44 IO3_7
IO1_1 14 43 IO3_6
PCA9698DGG
IO1_2 15 42 IO3_5
IO1_3 16 41 IO3_4
IO1_4 17 40 IO3_3
VDD 18 39 VSS
IO1_5 19 38 IO3_2
IO1_6 20 37 IO3_1
IO1_7 21 36 IO3_0
IO2_0 22 35 IO2_7
VSS 23 34 VSS
IO2_1 24 33 IO2_6
IO2_2 25 32 IO2_5
IO2_3 26 31 IO2_4
AD0 27 30 OE
AD1 28 29 AD2

002aab932

Fig 3. Pin configuration for TSSOP56

Product data sheet Rev. 3 — 3 August 2010 5 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

48 INT/SMBALERT
49 RESET
56 IO0_3

54 IO0_2
53 IO0_1
52 IO0_0

47 IO4_7
46 IO4_6
45 IO4_5

43 IO4_4
50 SDA
51 SCL
55 VSS

44 VSS
terminal 1
index area

IO0_4 1 42 IO4_3
IO0_5 2 41 IO4_2
IO0_6 3 40 IO4_1
VSS 4 39 VDD
IO0_7 5 38 IO4_0
IO1_0 6 37 IO3_7
IO1_1 7 36 IO3_6
PCA9698BS
IO1_2 8 35 IO3_5
IO1_3 9 34 IO3_4
IO1_4 10 33 IO3_3
VDD 11 32 VSS
IO1_5 12 31 IO3_2
IO1_6 13 30 IO3_1
IO1_7 14 29 IO3_0
IO2_0 15
VSS 16
IO2_1 17
IO2_2 18
IO2_3 19
AD0 20
AD1 21
AD2 22
OE 23
IO2_4 24
IO2_5 25
IO2_6 26
VSS 27
IO2_7 28
002aab934

Transparent top view

Fig 4. Pin configuration for HVQFN56

6.2 Pin description

Table 2. Pin description
Symbol Pin Type Description
TSSOP56 HVQFN56
SDA 1 50 input/output serial data line
SCL 2 51 input serial clock line
IO0_0 to IO0_7 3, 4, 5, 7, 52, 53, 54, 56, input/output input/output bank 0
8, 9, 10, 12 1, 2, 3, 5
IO1_0 to IO1_7 13, 14, 15, 16, 6, 7, 8, 9, 10, input/output input/output bank 1
17, 19, 20, 21 12, 13, 14
IO2_0 to IO2_7 22, 24, 25, 26, 15, 17, 18, 19, input/output input/output bank 2
31, 32, 33, 35 24, 25, 26, 28
IO3_0 to IO3_7 36, 37, 38, 40, 29, 30, 31, 33, input/output input/output bank 3
41, 42, 43, 44 34, 35, 36, 37
IO4_0 to IO4_7 45, 47, 48, 49, 38, 40, 41, 42, input/output input/output bank 4
50, 52, 53, 54 43, 45, 46, 47
VSS 6, 11, 23, 4, 16, 27, 32, power supply supply ground
34, 39, 51 44, 55[1]
VDD 18, 46 11, 39 power supply supply voltage
AD0 27 20 input address input 0
AD1 28 21 input address input 1

Product data sheet Rev. 3 — 3 August 2010 6 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

Table 2. Pin description …continued

Symbol Pin Type Description
TSSOP56 HVQFN56
AD2 29 22 input address input 2
OE 30 23 input active LOW output enable
INT/SMBALERT 55 48 output active LOW interrupt output/
active LOW SMBus alert
output
RESET 56 49 input active LOW reset input

[1] HVQFN56 package die supply ground is connected to both VSS pins and exposed center pad. VSS pins
must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and
board level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board and for proper heat conduction through the board, thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.

7. Functional description
Refer to Figure 1 “Block diagram of PCA9698”.

7.1 Device address

Following a START condition the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9698 is shown in Figure 5. Slave address pins AD2, AD1 and AD0 choose 1 of
64 slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1 and AD0. Address values depending on AD2, AD1 and AD0 can be found in
Table 12 “PCA9698 address map”.

slave address

A6 A5 A4 A3 A2 A1 A0 R/W

programmable
002aab937

Fig 5. PCA9698 device address

The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected while a logic 0 selects a write operation.

Product data sheet Rev. 3 — 3 August 2010 7 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.2 Alert response, GPIO All Call and Device ID addresses

Three other different addresses can be sent to the PCA9698.

• Alert Response address: allows to perform an ‘SMBus Alert’ operation as defined in

the SMBus specification. This address is always used to perform a Read operation.
See Section 7.11 “SMBus Alert output (SMBALERT)” for more information.
• GPIO All Call address: allows to program several Advanced GPIO devices at the
same time. This address is always used to perform a Write operation. See Section 7.6
“GPIO All Call” for more information.
• Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.5 “Device ID - PCA9698 ID field” for more
information.

R/W R/W

0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 0 1 1 1 1 1 0 0 R/W
002aab938 002aab939 002aab940

Fig 6. Alert Response address Fig 7. GPIO All Call address Fig 8. Device ID address

7.3 Command register

Following the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9698, which will be stored in the Command register.

AI − D5 D4 D3 D2 D1 D0
default at power-up
1 0 0 0 0 0 0 0
or after RESET

Fig 9. Command register

The lowest 6 bits are used as a pointer to determine which register will be accessed.

Registers are divided into 2 categories: 5-bank register category, and 1-bank register
category.

Only a command register code with the 7 least significant bits equal to the 28 allowable
values as defined in Table 3 “Register summary” will be acknowledged. Reserved or
undefined command codes will not be acknowledged. At power-up, this register defaults
to 80h, with the AI bit set to ‘1’, and the lowest 7 bits set to ‘0'.

During a write operation, the PCA9698 will acknowledge a byte sent to the OP, PI, IOC,
MSK, OUTCONF, ALLBNK, and MODE registers, but will not acknowledge a byte sent to
the IPx registers since these are read-only registers.

Product data sheet Rev. 3 — 3 August 2010 8 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.3.1 5-bank register category

• IP – Input registers
• OP – Output registers
• PI – Polarity Inversion registers
• IOC – I/O Configuration registers
• MSK – Mask interrupt registers

If the Auto-Increment flag is set (AI = 1), the 3 least significant bits are automatically
incremented after a read or write. This allows the user to program and/or read the
5 register banks sequentially.

If more than 5 bytes of data are written and AI = 1, previous data in the selected registers
will be overwritten or reread. Reserved registers are skipped and not accessed (refer to
Table 3).

If the Auto-Increment flag is cleared (AI = 0), the 3 least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.

7.3.2 1-bank register category

• OUTCONF – Output Structure Configuration register
• ALLBNK – All Bank Control register
• MODE – Mode Selection register
If more than 1 byte of data is written or read, previous data in the same register is
overwritten independently of the value of AI.

7.4 Register definitions

Table 3. Register summary
Reg # D5 D4 D3 D2 D1 D0 Name Type Function
Input Port registers
00h 0 0 0 0 0 0 IP0 read only Input Port register bank 0
01h 0 0 0 0 0 1 IP1 read only Input Port register bank 1
02h 0 0 0 0 1 0 IP2 read only Input Port register bank 2
03h 0 0 0 0 1 1 IP3 read only Input Port register bank 3
04h 0 0 0 1 0 0 IP4 read only Input Port register bank 4
05h 0 0 0 1 0 1 - - reserved for future use
06h 0 0 0 1 1 0 - - reserved for future use
07h 0 0 0 1 1 1 - - reserved for future use

Product data sheet Rev. 3 — 3 August 2010 9 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

Table 3. Register summary …continued

Reg # D5 D4 D3 D2 D1 D0 Name Type Function
Output Port registers
08h 0 0 1 0 0 0 OP0 read/write Output Port register bank 0
09h 0 0 1 0 0 1 OP1 read/write Output Port register bank 1
0Ah 0 0 1 0 1 0 OP2 read/write Output Port register bank 2
0Bh 0 0 1 0 1 1 OP3 read/write Output Port register bank 3
0Ch 0 0 1 1 0 0 OP4 read/write Output Port register bank 4
0Dh 0 0 1 1 0 1 - - reserved for future use
0Eh 0 0 1 1 1 0 - - reserved for future use
0Fh 0 0 1 1 1 1 - - reserved for future use
Polarity Inversion registers
10h 0 1 0 0 0 0 PI0 read/write Polarity Inversion register bank 0
11h 0 1 0 0 0 1 PI1 read/write Polarity Inversion register bank 1
12h 0 1 0 0 1 0 PI2 read/write Polarity Inversion register bank 2
13h 0 1 0 0 1 1 PI3 read/write Polarity Inversion register bank 3
14h 0 1 0 1 0 0 PI4 read/write Polarity Inversion register bank 4
15h 0 1 0 1 0 1 - - reserved for future use
16h 0 1 0 1 1 0 - - reserved for future use
17h 0 1 0 1 1 1 - - reserved for future use
I/O Configuration registers
18h 0 1 1 0 0 0 IOC0 read/write I/O Configuration register bank 0
19h 0 1 1 0 0 1 IOC1 read/write I/O Configuration register bank 1
1Ah 0 1 1 0 1 0 IOC2 read/write I/O Configuration register bank 2
1Bh 0 1 1 0 1 1 IOC3 read/write I/O Configuration register bank 3
1Ch 0 1 1 1 0 0 IOC4 read/write I/O Configuration register bank 4
1Dh 0 1 1 1 0 1 - - reserved for future use
1Eh 0 1 1 1 1 0 - - reserved for future use
1Fh 0 1 1 1 1 1 - - reserved for future use
Mask Interrupt registers
20h 1 0 0 0 0 0 MSK0 read/write Mask interrupt register bank 0
21h 1 0 0 0 0 1 MSK1 read/write Mask interrupt register bank 1
22h 1 0 0 0 1 0 MSK2 read/write Mask interrupt register bank 2
23h 1 0 0 0 1 1 MSK3 read/write Mask interrupt register bank 3
24h 1 0 0 1 0 0 MSK4 read/write Mask interrupt register bank 4
25h 1 0 0 1 0 1 - - reserved for future use
26h 1 0 0 1 1 0 - - reserved for future use
27h 1 0 0 1 1 1 - - reserved for future use
Miscellaneous
28h 1 0 1 0 0 0 OUTCONF read/write output structure configuration
29h 1 0 1 0 0 1 ALLBNK read/write control all banks
2Ah 1 0 1 0 1 0 MODE read/write PCA9698 mode selection

Product data sheet Rev. 3 — 3 August 2010 10 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.4.1 IP0 to IP4 - Input Port registers

These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to 1. Writes to
these registers have no effect.

Table 4. IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
Legend: * default value ‘X’ determined by the externally applied logic level.
Address Register Bit Symbol Access Value Description
00h IP0 7 to 0 I0[7:0] R XXXX XXXX* Input Port register bank 0
01h IP1 7 to 0 I1[7:0] R XXXX XXXX* Input Port register bank 1
02h IP2 7 to 0 I2[7:0] R XXXX XXXX* Input Port register bank 2
03h IP3 7 to 0 I3[7:0] R XXXX XXXX* Input Port register bank 3
04h IP4 7 to 0 I4[7:0] R XXXX XXXX* Input Port register bank 4

The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to 1. The polarity of
the corresponding bit is not inverted when Px[y] bits in the PI register is set to 0.

7.4.2 OP0 to OP4 - Output Port registers

These registers reflect the outgoing logic levels of the pins defined as outputs by the
I/O Configuration register. Bit values in these registers have no effect on pins defined as
inputs. In turn, reads from these registers reflect the values that are in the flip-flops
controlling the output selection, not the actual pin values.

Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).

Ox[y] = 1: IOx_y = 1 if IOx_y defined as output (Cx[y] in IOC register = 0).

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Table 5. OP0 to OP4 - Output Port registers (address 08h to 0Ch) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
08h OP0 7 to 0 O0[7:0] R/W 0000 0000* Output Port register bank 0
09h OP1 7 to 0 O1[7:0] R/W 0000 0000* Output Port register bank 1
0Ah OP2 7 to 0 O2[7:0] R/W 0000 0000* Output Port register bank 2
0Bh OP3 7 to 0 O3[7:0] R/W 0000 0000* Output Port register bank 3
0Ch OP4 7 to 0 O4[7:0] R/W 0000 0000* Output Port register bank 4

Product data sheet Rev. 3 — 3 August 2010 11 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.4.3 PI0 to PI4 - Polarity Inversion registers

These registers allow inversion of the polarity of the corresponding Input Port register.

Px[y] = 0: The corresponding Input Port register data polarity is retained.

Px[y] = 1: The corresponding Input Port register data polarity is inverted.

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Table 6. PI0 to PI4 - Polarity Inversion registers (address 10h to 14h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
10h PI0 7 to 0 P0[7:0] R/W 0000 0000* Polarity Inversion register bank 0
11h PI1 7 to 0 P1[7:0] R/W 0000 0000* Polarity Inversion register bank 1
12h PI2 7 to 0 P2[7:0] R/W 0000 0000* Polarity Inversion register bank 2
13h PI3 7 to 0 P3[7:0] R/W 0000 0000* Polarity Inversion register bank 3
14h PI4 7 to 0 P4[7:0] R/W 0000 0000* Polarity Inversion register bank 4

7.4.4 IOC0 to IOC4 - I/O Configuration registers

These registers configure the direction of the I/O pins.

Cx[y] = 0: The corresponding port pin is an output.

Cx[y] = 1: The corresponding port pin is an input.

Where ‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Table 7. IOC0 to IOC4 - I/O Configuration registers (address 18h to 1Ch) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
18h IOC0 7 to 0 C0[7:0] R/W 1111 1111* I/O Configuration register bank 0
19h IOC1 7 to 0 C1[7:0] R/W 1111 1111* I/O Configuration register bank 1
1Ah IOC2 7 to 0 C2[7:0] R/W 1111 1111* I/O Configuration register bank 2
1Bh IOC3 7 to 0 C3[7:0] R/W 1111 1111* I/O Configuration register bank 3
1Ch IOC4 7 to 0 C4[7:0] R/W 1111 1111* I/O Configuration register bank 4

Product data sheet Rev. 3 — 3 August 2010 12 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.4.5 MSK0 to MSK4 - Mask interrupt registers

These registers mask the interrupt due to a change in the I/O pins configured as inputs.
‘x’ refers to the bank number (0 to 4); ‘y’ refers to the bit number (0 to 7).

Mx[y] = 0: A level change at the I/O will generate an interrupt if IOx_y defined as input
(Cx[y] in IOC register = 1).
Mx[y] = 1: A level change in the input port will not generate an interrupt if IOx_y defined
as input (Cx[y] in IOC register = 1).

Table 8. MSK0 to MSK4 - Mask interrupt registers (address 20h to 24h) bit description
Legend: * default value.
Address Register Bit Symbol Access Value Description
20h MSK0 7 to 0 M0[7:0] R/W 1111 1111* Mask Interrupt register bank 0
21h MSK1 7 to 0 M1[7:0] R/W 1111 1111* Mask Interrupt register bank 1
22h MSK2 7 to 0 M2[7:0] R/W 1111 1111* Mask Interrupt register bank 2
23h MSK3 7 to 0 M3[7:0] R/W 1111 1111* Mask Interrupt register bank 3
24h MSK4 7 to 0 M4[7:0] R/W 1111 1111* Mask Interrupt register bank 4

7.4.6 OUTCONF - output structure configuration register

Table 9. OUTCONF - output structure configuration register (address 28h) description
Bit 7 6 5 4 3 2 1 0
Symbol OUT4 OUT3 OUT2 OUT1 OUT067 OUT045 OUT023 OUT001
Default 1 1 1 1 1 1 1 1

This register controls the configuration of the output ports as open-drain or totem-pole.

The 4 least significant bits control the output architecture for bank 0, 2 bits at a time.

OUT001 controls the output structure for IO0_0 and IO0_1

OUT023 controls the output structure for IO0_2 and IO0_3
OUT045 controls the output structure for IO0_4 and IO0_5
OUT067 controls the output structure for IO0_6 and IO0_7

The 4 most significant bits control the output architectures for bank 1 to bank 4, each bit
controlling one bank.

OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)

OUT2 controls the output structure for bank 2 (IO2_0 to IO2_7)
OUT3 controls the output structure for bank 3 (IO3_0 to IO3_7)
OUT4 controls the output structure for bank 4 (IO4_0 to IO4_7)

OUTx = 0: The I/Os are configured with an open-drain structure.

OUTx = 1: The I/Os are configured with a totem-pole structure.

Product data sheet Rev. 3 — 3 August 2010 13 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.4.7 ALLBNK - All Bank control register

Table 10. ALLBNK - All Bank control register (address 29h) description
Bit 7 6 5 4 3 2 1 0
Symbol BSEL X X B4 B3 B2 B1 B0
Default 1 0 0 0 0 0 0 0

This register allows all the I/Os configured as outputs to be programmed with the same
logic value. This programming is applied to all the banks or a selection of banks.

When this register is programmed, values in the Output Port registers are not changed
and do not reflect the states of I/Os configured as outputs anymore.

• B0 to B4 controls the logic level to be applied to Bank 0 to Bank 4, respectively.

– Bx = 0: All the I/Os configured as outputs in the corresponding Bank x are
programmed with 0s.
– Bx = 1: All the I/Os configured as outputs in the corresponding Bank x are
programmed with 1s.
• Bit 5 and bit 6 are not used and can be programmed to either ‘1’ or ‘0’.
• BSEL is a filter bit that allows programming of some banks only, and not the others.
– BSEL = 0:
When Bx = 0, all the I/Os configured as output in the corresponding Bank x are
programmed with 0s.
When Bx = 1, all the I/Os configured as output in the corresponding Bank x are
programmed with their actual value from the corresponding output register.
– BSEL = 1:
When Bx = 0, all the I/Os configured as output in the corresponding Bank x are
programmed with their actual value from the corresponding output register.
When Bx = 1, all the I/Os configured as output in the corresponding Bank x are
programmed with 1s.

7.4.7.1 Examples

• If ALLBNK = 0XX0 0000:

All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 0s,
overwriting values programmed in the five Output Port registers.
• If ALLBNK = 1XX1 1111:
All I/Os configured as outputs in Bank 0 to Bank 4 will be programmed with 1s,
overwriting values programmed in the five Output Port registers.
• If ALLBNK = 0XX0 0110:
All I/Os configured as outputs in Banks 0, 3, and 4 only will be programmed with 0s,
overwriting values programmed in the Output Port registers 0, 3, and 4, while I/Os
configured as outputs in Bank 1 and Bank 2 are programmed with values in Output
Port registers 1 and 2.

Product data sheet Rev. 3 — 3 August 2010 14 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

• If ALLBNK = 1XX0 1100:

All I/Os configured as outputs in Bank 2 and 3 will be programmed with 1s, overwriting
values programmed in the Output Port registers 2 and 3, while I/Os configured as
outputs in Bank 0, 1, and 4 are programmed with values in Output Port registers 0, 1,
and 4.

7.4.8 MODE - PCA9698 mode selection register

Table 11. MODE - mode selection register (address 2Ah) description
Bit 7 6 5 4 3 2 1 0
Symbol X X X SMBA IOAC X OCH OEPOL
Default 0 0 0 0 0 0 1 0

This register allows programming of the PCA9698 modes.

• OEPOL bit controls the polarity of OE pin.

– OEPOL = 0: OE pin is active LOW.
– OEPOL = 1: OE pin is active HIGH (equivalent to OE pin).
• OCH bit selects the I2C-bus event where the state of the I/Os configured as outputs
change.
– OCH = 0: outputs change on STOP command.
– OCH = 1: outputs change on ACK.

• IOAC bit controls the ability of the device to respond to a ‘GPIO All Call’ command
(see Section 7.6 “GPIO All Call” for more information), allowing programming of more
than one device at the same time.
– IOAC = 0: The device cannot respond to a ‘GPIO All Call’ command.
– IOAC = 1: The device can respond to a ‘GPIO All Call’ command.
Remark: The ‘GPIO ALL CALL’ command defined for the PCA9698 is different from
the I2C-bus protocol ‘General Call’ command.
• SMBA bit controls the capability of the PCA9698 to respond to a SMBAlert command.
– SMBA = 0: PCA9698 does not respond to an Alert Response Address.
– SMBA = 1: PCA9698 responds to an Alert Response Address. Bits 5, 6 and 7 are
reserved and must be programmed with 0s.
• Unused bits (bits 2, 5, 6 and 7) must be programmed with 0s for proper device
operation.

Product data sheet Rev. 3 — 3 August 2010 15 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.5 Device ID - PCA9698 ID field

The Device ID field is a 3 byte read-only (24 bits) word giving the following information:

• 12 bits with the manufacturer name, unique per manufacturer (e.g., NXP)
• 9 bits with the part identification, assigned by manufacturer (e.g., PCA9698)
• 3 bits with the die revision, assigned by manufacturer (e.g., RevX)
The Device ID is read-only, hard-wired in the device and can be accessed as follows:

1. START command
2. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to ‘0’ (write): ‘1111 1000’.
3. The master sends the I2C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID Read cannot be performed. Also, a STOP command or a
Re-START command followed by an access to another slave device will reset the
slave state machine and the Device ID Read cannot be performed.
5. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to ‘1’ (read): ‘1111 1001’.
6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte +
4 MSBs of the second byte), followed by the 9 part identification bits (4 LSBs of the
second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of
the third byte).
7. The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
If the master continues to ACK the bytes after the third byte, the PCA9698 rolls back
to the first byte and keeps sending the Device ID sequence until a NACK has been
detected.

For the PCA9698, the Device ID is as shown in Figure 10.

manufacturer 0 0 0 0 0 0 0 0 0 0 0 0

part identification 0 0 0 0 0 0 0 0 0

revision 0 0 0
002aab942

Fig 10. PCA9698 ID field

Product data sheet Rev. 3 — 3 August 2010 16 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.6 GPIO All Call

A ‘GPIO All Call’ command allows the programming of multiple advanced GPIOs with
different I2C-bus addresses at the same time. This allows to optimize code programming
when the master needs to send the same instruction to several devices. To respond to
such a command and sequence, the PCA9698 needs to have its IOAC bit (register 2Ah,
bit 3) set to 1. Devices that have this bit set to 0 do not participate in any ‘GPIO All Call’
sequence.

The ‘GPIO All Call’ command can be performed only for a write operation and cannot be
used in conjunction with a read operation.

• Master initiates a command sequence with the START command, the ‘GPIO All Call’
command associated with a Write command: Start − 1101 110 + Write
• All the devices that are programmed to respond to this command will acknowledge
• The master then sends the data and all the devices that are programmed to respond
acknowledge the byte(s)
• The master ends the sequence by sending a STOP or Repeated START command.
If the master initiates a ‘GPIO All Call’ sequence with a Read command, none of the slave
devices acknowledge.

7.7 Output state change on ACK or STOP

State change of the I/Os programmed as outputs can be done either:

• during the ACK phase every time an Output Port register is modified. The output state
is then updated one-by-one (at a bank level): OCH bit = 1 (register 2Ah, bit 1)
• at a STOP command allowing all the outputs to change at the exact same moment:
OCH bit = 0 (register 2Ah, bit 1).

Change of the outputs at the STOP command allows synchronizing of all the programmed
banks in a single device, and also allows synchronizing outputs of more than one
PCA9698.

Example 1: Only one PCA9698 is used on the I2C-bus and all the outputs need to change
at the same time.

• OCH bit (Mode Selection Register, bit 1) must be equal to ‘0’.

• The master accesses the device and programs the Output Port register(s) that has
(have) to be changed (up to 5 ports).
• When done, the master must generate a STOP command.
• At the STOP command, the PCA9698 will update the Output Port register(s) that has
(have) been programmed and change the output states all at the same time.

Example 2: More than one PCA9698 is used on the I2C-bus and all the outputs need to
change at the same time.

• OCH bit (Mode Selection Register, bit 1) must be equal to ‘0’ in all the devices.
• The master device must access the devices one-by-one.
• Access to each device must be separated by a Re-START command.

Product data sheet Rev. 3 — 3 August 2010 17 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

• When all the devices have been accessed, the master must generate a STOP
command.
• At the STOP command, all the PCA9698s that have been accessed will update their
Output Port registers that have been programmed and change the output states all at
the same time.

Remark: After programming a PCA9698, its state machine will be in a

‘wait-for-STOP-condition’ until a STOP condition is received to update the Output Port
registers. Since this state machine will be in a ‘wait-state’, the part will not respond to its
own address until this state machine gets out to the idle condition, which means that the
device can be programmed only once and is not addressable again until a STOP
condition has been received.

Remark: The PCA9698 has one level of buffers to store 5 bytes of data, and the actual
Output Port registers will get updated on the STOP condition. If the master sends more
than 5 bytes of data (with AI = 1), the data in the buffer will get overwritten.

7.8 Power-on reset

When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9698 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9698 registers and I2C-bus/SMBus state machine will initialize to their default
states. Thereafter, VDD must be lowered below 0.2 V to reset the device.

7.9 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9698 registers and I2C-bus state machine will be held in their default state until the
RESET input is once again HIGH.

7.10 Interrupt output (INT)

The open-drain active LOW interrupt is activated when one of the port pins changes state
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port register is read.

It is highly recommended to program the MSK register, and the IOC registers during the
initialization sequence after power-up, since any change to them during Normal mode
operation may cause undesirable interrupt events to happen.

Remark: Changing an I/O from an output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.

Only a Read of the Input Port register that contains the bit(s) image of the input(s) that
generated the interrupt clears the interrupt condition.

If more than one input register changed state before a read of the Input Port register is
initiated, the interrupt is cleared when all the input registers containing all the inputs that
changed are read.

Example: If IO0_5, IO2_3, and IO3_7 change state at the same time, the interrupt is
cleared only when INREG0, INREG2, and INREG3 are read.

Product data sheet Rev. 3 — 3 August 2010 18 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.11 SMBus Alert output (SMBALERT)

The interrupt output pin (INT) can also be used as an Alert line (SMBALERT).

The SMBALERT pins of multiple devices with this feature can be connected together to
form a wired-AND signal and can be used in conjunction with the SMBus Alert Response
Address. ‘SMBus Alert’ message is 2 bytes long and allows the master to determine
which device generated the Alert (SMBALERT going LOW).

When SMBA bit = 1 (register 2Ah, bit 4), the PCA9698 supports the SMBus Alert function
and its INT/SMBALERT pin may be connected as an SMBus Alert signal.

When a master device senses that an ‘SMBus Alert’ condition is present on the ALERT
line (SMBALERT pin of the PCA9698 and/or other devices going LOW):

• It accesses the slave device(s) through the Alert Response Address (ARA)
associated with a Read Command: Start − 0001 100 + R/W = 1.
• If the PCA9698 is the device that generated the ‘SMBus Alert’ condition (and its
SMBA bit = 1), it will acknowledge the SMBus Alert command and respond by
transmitting its slave address on the SDA line. The 8th bit (LSB) of the slave address
byte will be a zero.
• The device will acknowledge an ARA command only if the SMBALERT signal has
been previously asserted (SMBALERT = LOW).
• If more than one device pulls its SMBALERT pin LOW, the highest priority (lowest
I2C-bus address) device will win communication rights via standard I2C-bus arbitration
during the slave address transfer.
• If the PCA9698 wins the arbitration, its SMBALERT pin will become inactive (will go
HIGH) at the completion of the slave address transmission (9th clock pulse, NACK
phase).
• If the PCA9698 loses the arbitration, its SMBALERT pin will remain active (will stay
LOW).
• The master ends the sequence by sending a NACK and then STOP command.
• If the SMBALERT is still LOW after transfer is complete, it means that more than one
device made the request. Another full transaction is then required.

Remark: If the master initiates an ‘SMBus Alert’ sequence with a Write Command, none
of the slave devices acknowledge. The SMBALERT is open-drain and requires a pull-up
resistor to VDD.

Remark: If the master sends an ACK after reading the I2C-bus slave address, the slave
device keeps sending ‘1’s until a NACK is received.

Product data sheet Rev. 3 — 3 August 2010 19 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.12 Output enable input (OE)

The configurable active LOW or active HIGH output enable pin allows to enable or disable
all the I/Os at the same time.

• When a LOW level is applied to the OE pin, with OEPOL = 0 (register 2Ah, bit 4) or a
HIGH level is applied to the OE pin, with OEPOL = 1 (register 2Ah, bit 0), all the I/Os
configured as outputs are enabled and the logic value programmed in their respective
OP registers is applied to the pins.
• When a HIGH level is applied to the OE pin, with OEPOL = 0 (register 2Ah, bit 0) or a
LOW level is applied to the OE pin, with OEPOL = 1 (register 2Ah, bit 0), all the I/Os
configured as outputs are 3-stated.

For applications requiring LED blinking with brightness control, this pin can be used to
control the brightness by applying a high frequency PWM signal on the OE pin. LEDs can
be blinked using the Output Port registers and can be dimmed using the PWM signal on
the OE pin thus controlling the brightness by adjusting the duty cycle.

Default is OEPOL = 0, so if the OE pin is held HIGH, the outputs are disabled. The OE pin
needs to be pulled LOW or OEPOL changed to ‘1’ to enable the outputs.

It is recommended to define the required polarity of the OE input by programing the value
of OEPOL before programming the configuration registers (IOC register).

7.13 Live insertion

The PCA9698 is fully specified for live-insertion applications using IOFF, power-up
3-states, robust state machine, and 50 ns noise filter. The IOFF circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-states circuitry places the outputs in the high-impedance state
during power-up and power-down, which prevents driver conflict and bus contention.

The robust state machine does not respond until it sees a valid START condition and the
50 ns noise filter will filter out any insertion glitches. The PCA9698 will not cause
corruption of active data on the bus nor will the device be damaged or cause damage to
devices already on the bus when similar featured devices are being used.

7.14 Standby
The PCA9698 goes into standby when the I2C-bus is idle. Standby supply current is lower
than 1.0 μA (typical).

Product data sheet Rev. 3 — 3 August 2010 20 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

7.15 Address map

Table 12. PCA9698 address map
AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 Address
VSS SCL VSS 0 0 1 0 0 0 0 20h
VSS SCL VDD 0 0 1 0 0 0 1 22h
VSS SDA VSS 0 0 1 0 0 1 0 24h
VSS SDA VDD 0 0 1 0 0 1 1 26h
VDD SCL VSS 0 0 1 0 1 0 0 28h
VDD SCL VDD 0 0 1 0 1 0 1 2Ah
VDD SDA VSS 0 0 1 0 1 1 0 2Ch
VDD SDA VDD 0 0 1 0 1 1 1 2Eh
VSS SCL SCL 0 0 1 1 0 0 0 30h
VSS SCL SDA 0 0 1 1 0 0 1 32h
VSS SDA SCL 0 0 1 1 0 1 0 34h
VSS SDA SDA 0 0 1 1 0 1 1 36h
VDD SCL SCL 0 0 1 1 1 0 0 38h
VDD SCL SDA 0 0 1 1 1 0 1 3Ah
VDD SDA SCL 0 0 1 1 1 1 0 3Ch
VDD SDA SDA 0 0 1 1 1 1 1 3Eh
VSS VSS VSS 0 1 0 0 0 0 0 40h
VSS VSS VDD 0 1 0 0 0 0 1 42h
VSS VDD VSS 0 1 0 0 0 1 0 44h
VSS VDD VDD 0 1 0 0 0 1 1 46h
VDD VSS VSS 0 1 0 0 1 0 0 48h
VDD VSS VDD 0 1 0 0 1 0 1 4Ah
VDD VDD VSS 0 1 0 0 1 1 0 4Ch
VDD VDD VDD 0 1 0 0 1 1 1 4Eh
VSS VSS SCL 0 1 0 1 0 0 0 50h
VSS VSS SDA 0 1 0 1 0 0 1 52h
VSS VDD SCL 0 1 0 1 0 1 0 54h
VSS VDD SDA 0 1 0 1 0 1 1 56h
VDD VSS SCL 0 1 0 1 1 0 0 58h
VDD VSS SDA 0 1 0 1 1 0 1 5Ah
VDD VDD SCL 0 1 0 1 1 1 0 5Ch
VDD VDD SDA 0 1 0 1 1 1 1 5Eh

Product data sheet Rev. 3 — 3 August 2010 21 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

Table 12. PCA9698 address map …continued

AD2 AD1 AD0 A6 A5 A4 A3 A2 A1 A0 Address
SCL SCL VSS 1 0 1 0 0 0 0 A0h
SCL SCL VDD 1 0 1 0 0 0 1 A2h
SCL SDA VSS 1 0 1 0 0 1 0 A4h
SCL SDA VDD 1 0 1 0 0 1 1 A6h
SDA SCL VSS 1 0 1 0 1 0 0 A8h
SDA SCL VDD 1 0 1 0 1 0 1 AAh
SDA SDA VSS 1 0 1 0 1 1 0 ACh
SDA SDA VDD 1 0 1 0 1 1 1 AEh
SCL SCL SCL 1 0 1 1 0 0 0 B0h
SCL SCL SDA 1 0 1 1 0 0 1 B2h
SCL SDA SCL 1 0 1 1 0 1 0 B4h
SCL SDA SDA 1 0 1 1 0 1 1 B6h
SDA SCL SCL 1 0 1 1 1 0 0 B8h
SDA SCL SDA 1 0 1 1 1 0 1 BAh
SDA SDA SCL 1 0 1 1 1 1 0 BCh
SDA SDA SDA 1 0 1 1 1 1 1 BEh
SCL VSS VSS 1 1 0 0 0 0 0 C0h
SCL VSS VDD 1 1 0 0 0 0 1 C2h
SCL VDD VSS 1 1 0 0 0 1 0 C4h
SCL VDD VDD 1 1 0 0 0 1 1 C6h
SDA VSS VSS 1 1 0 0 1 0 0 C8h
SDA VSS VDD 1 1 0 0 1 0 1 CAh
SDA VDD VSS 1 1 0 0 1 1 0 CCh
SDA VDD VDD 1 1 0 0 1 1 1 CEh
SCL VSS SCL 1 1 1 0 0 0 1 E0h
SCL VSS SDA 1 1 1 0 0 1 0 E2h
SCL VDD SCL 1 1 1 0 0 1 1 E4h
SCL VDD SDA 1 1 1 0 1 0 0 E6h
SDA VSS SCL 1 1 1 0 1 0 1 E8h
SDA VSS SDA 1 1 1 0 1 1 0 EAh
SDA VDD SCL 1 1 1 0 1 1 1 ECh
SDA VDD SDA 1 1 1 0 0 0 1 EEh

Product data sheet Rev. 3 — 3 August 2010 22 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

8. Characteristics of the I2C-bus

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 11).

SDA

SCL

data line change

stable; of data
data valid allowed mba607

Fig 11. Bit transfer

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 12.)

SDA

SCL
S P

START condition STOP condition

mba608

Fig 12. Definition of START and STOP conditions

Product data sheet Rev. 3 — 3 August 2010 23 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

8.2 System configuration

A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 13).

SDA
SCL

MASTER SLAVE MASTER

SLAVE MASTER I2C-BUS
TRANSMITTER/ RECEIVER TRANSMITTER/ TRANSMITTER TRANSMITTER/
MULTIPLEXER
RECEIVER RECEIVER RECEIVER

SLAVE

002aaa966

Fig 13. System configuration

8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.

data output
by transmitter
not acknowledge

data output
by receiver
acknowledge

SCL from master 1 2 8 9

S
clock pulse for
START acknowledgement
condition 002aaa987

Fig 14. Acknowledgement on the I2C-bus

Product data sheet Rev. 3 — 3 August 2010 24 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

8.4 Bus transactions

Data is transmitted to the PCA9698 registers using ‘Write Byte’ transfers (see Figure 15,
Figure 16, Figure 17, and Figure 18).

Data is read from the PCA9698 registers using ‘Read Byte’ and ‘Receive Byte’ transfers
(see Figure 19 and Figure 20).

Product data sheet Rev. 3 — 3 August 2010 25 of 48

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
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Product data sheet
PCA9698

NXP Semiconductors
acknowledge
from slave
acknowledge
from slave acknowledge acknowledge acknowledge acknowledge acknowledge STOP
from slave from slave from slave from slave from slave condition
slave address command register

SDA S A6 A5 A4 A3 A2 A1 A0 0 A 1 0 0 0 1 0 0 0 A DATA BANK 0 A DATA BANK 1 A DATA BANK 2 A DATA BANK 3 A DATA BANK 4 A P
Output Port
START condition R/W register bank 0
is selected
AI = 1
write to port when OCH = 0
tv(Q)

data out from port when OCH = 0

data valid
All information provided in this document is subject to legal disclaimers.

all banks
write to port when OCH = 1

tv(Q)

40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT
Rev. 3 — 3 August 2010

data out from port when OCH = 1

data valid data valid data valid data valid data valid
bank 0 bank 1 bank 2 bank 3 bank 4
002aab944

OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs.
If more than 5 bytes are written, previous data are overwritten.
Fig 15. Write to the 5 output ports

PCA9698
© NXP B.V. 2010. All rights reserved.
26 of 48
NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

acknowledge bank X acknowledge

slave address from slave determined by from slave
D2, D1, D0
SDA S A6 A5 A4 A3 A2 A1 A0 0 A AI 0 0 0 1 D2 D1 D0 A DATA BANK X A P

START condition R/W acknowledge STOP

from slave condition

write to port
tv(Q)

data out from port data X valid

002aab945

OE is LOW (with OEPOL = 0) or HIGH (with OEPOL = 1) to observe a change in the outputs.
OCH = 0. When OCH = 1, the change in the port happens at the acknowledge phase.
Two, three, or four adjacent banks can be programmed by using the Auto-Increment feature (AI = 1) and change at the
corresponding output port becomes effective at the STOP command when OCH = 0, or at each acknowledge when OCH = 1.
Fig 16. Write to a specific output port

acknowledge
from slave acknowledge acknowledge acknowledge
from slave from slave from slave
slave address command register

SDA S A6 A5 A4 A3 A2 A1 A0 0 A 1 0 D5 D4 D3 D2 D1 D0 A DATA BANK 0 A DATA BANK 1 A

START condition R/W AI = 1 01 0000 for Polarity Inversion register programming bank 0
01 1000 for Configuration register programming bank 0
10 0000 for Mask interrupt register programming bank 0

acknowledge acknowledge acknowledge

from slave from slave from slave

DATA BANK 2 A DATA BANK 3 A DATA BANK 4 A P

STOP
condition
002aab946

The programing becomes effective at the Acknowledge.

Less than 5 bytes can be programmed by using the same scheme. ‘D5 D4 D3 D2 D1 D0’ refers to the first register to be
programmed.
If more than 5 bytes are written, previous data are overwritten (the sixth configuration register will roll over to the first addressed
configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion register, the sixth
Mask interrupt register will roll over to the first addressed Mask interrupt register.
Fig 17. Write to the I/O Configuration, Polarity Inversion, or Mask interrupt registers (5 banks)

Product data sheet Rev. 3 — 3 August 2010 27 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

acknowledge
from slave acknowledge acknowledge
from slave from slave
slave address command register

SDA S A6 A5 A4 A3 A2 A1 A0 0 A X 0 1 0 1 0 D1 D0 A DATA A P

START condition R/W AI = 'don't care' STOP condition

00 for output structure configuration programming

01 for all bank control register programming
10 for mode selection register programming
002aab947

The programming becomes effective at the Acknowledge.

If more than 1 byte is written, previous data is overwritten.
Fig 18. Write to the output structure configuration, all bank control, or mode selection

acknowledge acknowledge acknowledge

from slave from slave from slave
slave address command register slave address

SDA S A6 A5 A4 A3 A2 A1 A0 0 A 1 0 D5 D4 D3 D2 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 1 A

START condition R/W AI = 1 repeated START R/W

condition
D[5:0] = 00 0000 for Input Port register bank 0
D[5:0] = 00 1000 for Output Port register bank 0
D[5:0] = 01 0000 for Polarity Inversion register bank 0
D[5:0] = 01 1000 for Configuration register bank 0
D[5:0] = 10 0000 for Mask Interrupt register bank 0
no acknowledge
from master
data from register data from register data from register

DATA A DATA DATA A P

first byte second byte last byte

STOP condition
register determined acknowledge
by D4 D3 D2 D1 D0 from master
002aab948

If AI = 0, the same register is read during the whole sequence.

If AI = 1, the register value is incremented after each read. When the last register bank is read, it rolls over to the first byte of the
category (see category definition in Section 7.3 “Command register”).
The INT signal is released only when the last register containing an input that changed has been read. For example, when
IO2_4 and IO4_7 change at the same time and an Input Port register read sequence is initiated, starting with IP0, INT is
released after IP4 is read (and not after IP2 is read).
Fig 19. Read from Input Port, Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers

Product data sheet Rev. 3 — 3 August 2010 28 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

acknowledge acknowledge acknowledge no acknowledge

from slave from slave from slave from master
slave address command register slave address data from register

SDA S A6 A5 A4 A3 A2 A1 A0 0 A X 0 1 0 1 0 D1 D0 A Sr A6 A5 A4 A3 A2 A1 A0 1 A DATA A P

last byte
START condition R/W AI = 'don't care' repeated START R/W STOP
condition condition
00 for output structure configuration register reading At this moment master-transmitter
01 for for all bank control register reading becomes master-receiver, and
10 for mode selection register reading slave-receiver becomes slave-transmitter.
002aab949

If AI = 0 or 1, the same register is read during the all sequence.

Fig 20. Read from output structure configuration, all bank control or mode selection registers

acknowledge from slave

that generated the alert
no acknowledge
SMBus Alert PCA9698 I2C-bus
from master
response address slave address

S 0 0 0 1 1 0 0 1 A A6 A5 A4 A3 A2 A1 A0 0 A P

START condition R/W R/W STOP condition

At this moment master-transmitter
becomes master-receiver and
SMBALERT signal is released
slave receiver becomes slave-transmitter.
(assuming that only one device
generated the alert)

SMBALERT
002aab950

Fig 21. SMBus Alert procedure

acknowledge from acknowledge from acknowledge from

one or several slaves slave to be identified slave to be identified
I2C-bus slave address
Device ID address of the device to be identified Device ID address

S 1 1 1 1 1 0 0 0 A A6 A5 A4 A3 A2 A1 A0 0 A Sr 1 1 1 1 1 0 0 1 A

START condition R/W don't care repeated START R/W

condition

acknowledge acknowledge no acknowledge

from master from master from master

M M M9 M8 M7 M6 M5 M4 A M3 M2 M1 M0 P8 P7 P6 P5 A P4 P3 P2 P1 P0 R2 R1 R0 A P
11 10

STOP condition
manufacturer name = 000000000000 part identification = 000000000 revision = 000
002aab951

If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the
master generates a ‘No Acknowledge’.
Fig 22. Device ID field reading

Product data sheet Rev. 3 — 3 August 2010 29 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

acknowledge
from slave acknowledge acknowledge acknowledge
from slave(s) from slave(s) from slave(s)
GPIO All Call address command register

SDA S 1 1 0 1 1 1 0 0 A 1 0 D5 D4 D3 D2 D1 D0 A DATA BANK 0 A DATA BANK 1 A

START condition R/W AI = 1 00 1000 for Output Port register programming bank 0
01 0000 for Polarity Inversion register programming bank 0
01 1000 for Configuration register programming bank 0
10 0000 for Mask interrupt register programming bank 0
acknowledge acknowledge acknowledge
from slave(s) from slave(s) from slave

DATA BANK 2 A DATA BANK 3 A DATA BANK 4 A P

STOP
condition
002aab952

Only slave devices with bit IOAC = 1 answer to the GPIO All Call transaction.
Output Port register programming becomes effective at the STOP command if OCH = 0, at each acknowledge if OCH = 1.
Configuration, Polarity Inversion, and Mask interrupt registers become effective at the acknowledge.
Less than 5 bytes can be programmed by using the same scheme.
‘D5 D4 D3 D2 D1 D0’ refers to the first register to be programmed.
If more than 5 bytes are written, previous data are overwritten (the sixth Configuration register will roll over to the first
addressed Configuration register, the sixth Polarity Inversion register will roll over to the first addressed Polarity Inversion
register, the sixth Mask interrupt register will roll over to the first addressed Mask interrupt register).
Fig 23. GPIO All Call write to the Output Port, I/O Configuration, Polarity Inversion, or Mask interrupt registers

acknowledge acknowledge acknowledge

from slave(s) from slave(s) from slave(s)
slave address command register

SDA S 1 1 0 1 1 1 0 0 A X 0 1 0 1 0 D1 D0 A DATA A P

START condition R/W AI = 'don't care' STOP

condition
00 for Output structure configuration register programming
01 for All Bank Control register programming
10 for Mode selection register programming
002aab953

Only slave devices with bit 0 IOAC = 1 answer the GPIO All Call transaction.
The programming becomes effective at the acknowledge.
If more than 1 byte is written, previous data is overwritten.
Fig 24. GPIO All Call write to the Output structure configuration, All Bank Control, or Mode selection registers

Product data sheet Rev. 3 — 3 August 2010 30 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

9. Application design-in information

5V
VDD
1.1 kΩ 1.1 kΩ 2 kΩ
1.6 kΩ 1.6 kΩ 2 kΩ
(optional) (optional)
VDD VDD
MASTER PCA9698
CONTROLLER SUBSYSTEM 1
SCL SCL IO0_0 (e.g., temp. sensor)

SDA SDA IO0_1 INT

RESET RESET IO0_2
RESET
INT INT/SMBALERT IO0_3
OE OE IO0_4 SUBSYSTEM 2
VSS (e.g., counter)
IO0_5

A
IO1_0

enable controlled switch

IO3_7 (e.g., CBT device)

IO4_0 B

IO4_7
ALARM

AD2 SUBSYSTEM 3
AD1 (e.g., alarm system)

AD0
VDD
VSS
24 LED MATRIX

ALPHANUMERIC
KEYPAD
002aab954

Device address configured as ‘0100 000x’ for this example.

IO0_0, IO0_2, IO0_3, IO1_0 to IO3_7 are configured as outputs.
IO0_1, IO0_4, IO4_0 to IO4_7 are configured as inputs.
Fig 25. Typical application

Product data sheet Rev. 3 — 3 August 2010 31 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

10. Limiting values

Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDD supply voltage −0.5 +6 V
VI input voltage VSS − 0.5 5.5 V
II input current - ±20 mA
VI/O voltage on an input/output pin VSS − 0.5 5.5 V
IO(IOx_y) output current on pin IOx_y −20 +50 mA
IDD supply current - 500 mA
ISS ground supply current - 1100 mA
Ptot total power dissipation - 500 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
Tj junction temperature operating - 125 °C
storage - 150 °C

Product data sheet Rev. 3 — 3 August 2010 32 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

11. Static characteristics

Table 14. Static characteristics
VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VDD supply voltage 2.3 - 5.5 V
IDD supply current Operating mode; no load; fSCL = 1 MHz;
AD0, AD1, AD2 = static H or L
VDD = 2.3 V - 135 200 μA
VDD = 3.3 V - 250 400 μA
VDD = 5.5 V - 550 800 μA
Istb standby current no load; fSCL = 0 kHz; I/O = inputs;
VI = VDD
VDD = 2.3 V - 0.15 11 μA
VDD = 3.3 V - 0.25 12 μA
VDD = 5.5 V - 0.75 15.5 μA
VPOR power-on reset voltage no load; VI = VDD or VSS [1] - 1.70 2.0 V
Input SCL; input/output SDA
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
IOL LOW-level output current VOL = 0.4 V 20 - - mA
IL leakage current VI = VDD or VSS −1 - +1 μA
Ci input capacitance VI = VSS - 5 10 pF
I/Os
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 2 - 5.5 V
IOL LOW-level output current VOL = 0.5 V; VDD = 2.3 V [2] 12 - - mA
VOL = 0.5 V; VDD = 3.0 V [2] 17 - - mA
VOL = 0.5 V; VDD = 4.5 V [2] 25 - - mA
IOL(tot) total LOW-level output VOL = 0.5 V; VDD = 4.5 V
current TSSOP56 package [2] - - 0.86 A
HVQFN56 package [2] - - 1.0 A
VOH HIGH-level output voltage IOH = −10 mA; VDD = 2.3 V 1.6 - - V
IOH = −10 mA; VDD = 3.0 V 2.3 - - V
IOH = −10 mA; VDD = 4.5 V 4.0 - - V
ILIH HIGH-level input leakage VDD = 3.6 V; VI/O = VDD −1 - +1 μA
current
ILIL LOW-level input leakage VDD = 5.5 V; VI/O = VSS −1 - +1 μA
current
Ci input capacitance - 6 7 pF
Co output capacitance - 6 7 pF

Product data sheet Rev. 3 — 3 August 2010 33 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

Table 14. Static characteristics …continued

VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Interrupt INT
IOL LOW-level output current VOL = 0.4 V 6 - - mA
Co output capacitance - 3 5 pF
Inputs RESET and OE
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2 - 5.5 V
ILI input leakage current −1 - +1 μA
Ci input capacitance - 3 5 pF
Inputs AD0, AD1, AD2
VIL LOW-level input voltage −0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD - 5.5 V
ILI input leakage current −1 - +1 μA
Ci input capacitance - 3.5 5 pF

[1] VDD must be lowered to 0.2 V in order to reset part.

[2] Each bit must be limited to a maximum of 25 mA and the total package limited to the package maximum limit due to internal busing
limits.

11.1 Performance curves

002aab955 002aab956
1.2 1.2

IDD IDD
(μA) (μA)
VDD = 5 V VDD = 5 V
0.8 0.8

3.3 V 3.3 V
0.4 0.4
2.3 V 2.3 V

0 0
−50 0 50 100 −50 0 50 100
Tamb (°C) Tamb (°C)

fSCL = 400 kHz; all I/Os unloaded SCL = VDD; all I/Os unloaded
Fig 26. Supply current as a function of temperature Fig 27. Standby current as a function of temperature

Product data sheet Rev. 3 — 3 August 2010 34 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

002aab957 002aab958
600 50
IDD Isink
(μA) (mA)
40
Tamb = −40 °C
400
+25 °C
30
+85 °C

fSCL = 1 MHz 20
200

400 kHz 10

100 kHz
0 0
2.0 3.0 4.0 5.0 6.0 0 0.2 0.4 0.6
VDD (V) VOL (V)

All I/Os unloaded; address pins static HIGH or LOW

Fig 28. Supply current as a function of supply voltage Fig 29. I/O sink current as a function of LOW-level
output voltage (VDD = 2.3 V)

002aab959 002aab960
50 50
Isink Isink
(mA) (mA)
40 40
Tamb = −40 °C Tamb = −40 °C
+25 °C +25 °C
30 30
+85 °C +85 °C

20 20

10 10

0 0
0 0.2 0.4 0.6 0 0.2 0.4 0.6
VOL (V) VOL (V)

Fig 30. I/O sink current as a function of LOW-level Fig 31. I/O sink current as a function of LOW-level
output voltage (VDD = 3.0 V) output voltage (VDD = 4.5 V)

002aab961 002aab962
30 50
Isource Tamb = −40 °C
Isource (mA)
(mA) 40 +25 °C
Tamb = −40 °C +85 °C
20 +25 °C
30
+85 °C

20
10

0 0
0 0.2 0.4 0.6 0.8 0 0.2 0.4 0.6 0.8
VDD − VOH (V) VDD − VOH (V)

Fig 32. I/O source current as a function of HIGH-level Fig 33. I/O source current as a function of HIGH-level
output voltage (VDD = 2 V) output voltage (VDD = 3.3 V)

Product data sheet Rev. 3 — 3 August 2010 35 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

002aab965 002aab963
50 400
Isource Tamb = −40 °C VOL
(mA) (mV)
40 +25 °C
+85 °C 300
(1)
30
200
20
(2)
100
10
(3)
(4)
0 0
0 0.2 0.4 0.6 −50 0 50 100
VDD − VOH (V) Tamb (°C)

(1) VDD = 5 V; Isink = 10 mA

(2) VDD = 2.3 V; Isink = 10 mA
(3) VDD = 5 V; Isink = 1 mA
(4) VDD = 2.3 V; Isink = 1 mA
Fig 34. I/O source current as a function of HIGH-level Fig 35. I/O LOW-level output voltage as a function of
output voltage (VDD = 5 V) temperature

002aab964
600

VDD − VOH
(V)

400

(1)

200

(2)
0
−50 0 50 100
Tamb (°C)

(1) VDD = 2.3 V; Isource = 10 mA

(2) VDD = 5 V; Isource = 10 mA
Fig 36. HIGH-level output voltage as a function of temperature

Product data sheet Rev. 3 — 3 August 2010 36 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

12. Dynamic characteristics

Table 15. Dynamic characteristics
Symbol Parameter Conditions Standard-mode Fast-mode I2C-bus Fast-mode Plus Unit
I2C-bus I2C-bus
Min Max Min Max Min Max
fSCL SCL clock frequency [3] 0 100 0 400 0 1000 kHz
tBUF bus free time between a 4.7 - 1.3 - 0.5 - μs
STOP and START
condition
tHD;STA hold time (repeated) 4.0 - 0.6 - 0.26 - μs
START condition
tSU;STA set-up time for a repeated 4.7 - 0.6 - 0.26 - μs
START condition
tSU;STO set-up time for STOP 4.0 - 0.6 - 0.26 - μs
condition
tHD;DAT data hold time 0 - 0 - 0 - ns
tVD;ACK data valid acknowledge [1] 0.1 3.45 0.1 0.9 0.05 0.45 μs
time
tVD;DAT data valid time [2] 300 - 75 - 75 450 ns
tSU;DAT data set-up time 250 - 100 - 50 - ns
tLOW LOW period of the SCL 4.7 - 1.3 - 0.5 - μs
clock
tHIGH HIGH period of the SCL 4.0 - 0.6 - 0.26 - μs
clock
tf fall time of both SDA and [4][6] - 300 20 + 0.1Cb[5] 300 - 120 ns
SCL signals
tr rise time of both SDA and [4][6] - 1000 20 + 0.1Cb[5] 300 - 120 ns
SCL signals
tSP pulse width of spikes that [7] - 50 - 50 - 50 ns
must be suppressed by the
input filter
Port timing
ten enable time output - 80 - 80 - 80 ns
tdis disable time output - 40 - 40 - 40 ns
tv(Q) data output valid time - 250 - 250 - 250 ns
tsu(D) data input set-up time 100 - 100 - 100 - ns
th(D) data input hold time 250 - 250 - 250 - ns
Interrupt timing
tv(INT_N) valid time on pin INT - 4 - 4 - 4 μs
trst(INT_N) reset time on pin INT - 4 - 4 - 4 μs
Reset
tw(rst) reset pulse width 4 - 4 - 4 - ns
trec(rst) reset recovery time 0 - 0 - 0 - ns
trst reset time 100 - 100 - 100 - ns

[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.

Product data sheet Rev. 3 — 3 August 2010 37 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
[3] Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either SDA or SCL is held
LOW for a minimum of 25 ms. Disable bus time-out feature for DC operation.
[4] A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
[5] Cb = total capacitance of one bus line in pF.
[6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified tf.
[7] Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.

SDA

tBUF tr tf tHD;STA tSP

tLOW

SCL

tHD;STA tSU;STA tSU;STO

P S tHD;DAT tHIGH tSU;DAT Sr P
002aaa986

Fig 37. Definition of timing on the I2C-bus

START bit 7 STOP

bit 6 bit 0 acknowledge
protocol condition MSB condition
(A6) (R/W) (A)
(S) (A7) (P)

tSU;STA tLOW tHIGH

1/f
SCL

SCL

tBUF tf
tr

SDA

tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO

002aab175

Rise and fall times refer to VIL and VIH.

Fig 38. I2C-bus timing diagram

Product data sheet Rev. 3 — 3 August 2010 38 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

START ACK or read cycle

SCL

SDA
30 %

trst

RESET 50 % 50 % 50 %
trec(rst)
tw(rst)
trst
50 %
IOx_y
output off
002aac018

Fig 39. Reset timing

13. Test information

2VDD
open
VSS
VDD RL
500 Ω
VI VO
PULSE
DUT
GENERATOR
CL
RT 500 Ω
50 pF

002aac019

RL = load resistance.
CL = load capacitance includes jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generators.
Fig 40. Test circuitry for switching times

Product data sheet Rev. 3 — 3 August 2010 39 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

14. Package outline

TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1

D E A
X

y HE v M A

56 29

Q
A2 (A 3) A
A1

pin 1 index
θ
Lp
L

1 28 detail X

w M
e bp

0 2.5 5 mm
scale

DIMENSIONS (mm are the original dimensions).

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ
max.
o
0.15 1.05 0.28 0.2 14.1 6.2 8.3 0.8 0.50 0.5 8
mm 1.2 0.25 0.5 1 0.25 0.08 0.1 o
0.05 0.85 0.17 0.1 13.9 6.0 7.9 0.4 0.35 0.1 0

Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

99-12-27
SOT364-1 MO-153
03-02-19

Fig 41. Package outline SOT364-1 (TSSOP56)

Product data sheet Rev. 3 — 3 August 2010 40 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

HVQFN56: plastic thermal enhanced very thin quad flat package; no leads;
56 terminals; body 8 x 8 x 0.85 mm SOT684-1

D B A

terminal 1
index area A
E A1
c

detail X

e1 C

e 1/2 e b v M C A B y1 C y
15 28 w M C
L
29
14
e

Eh e2

1/2 e

1
42
terminal 1
56 43
index area
Dh X
0 2.5 5 mm

scale
DIMENSIONS (mm are the original dimensions)
A(1)
UNIT A1 b c D(1) Dh E(1) Eh e e1 e2 L v w y y1
max.

mm 0.05 0.30 8.1 4.45 8.1 4.45 0.5

1 0.2 0.5 6.5 6.5 0.1 0.05 0.05 0.1
0.00 0.18 7.9 4.15 7.9 4.15 0.3

Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

01-08-08
SOT684-1 --- MO-220 ---
02-10-22

Fig 42. Package outline SOT684-1 (HVQFN56)

Product data sheet Rev. 3 — 3 August 2010 41 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

15. Handling information

All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.

16. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.

16.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.

16.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:

• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.

The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.

Key characteristics in both wave and reflow soldering are:

• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering

16.3 Wave soldering

Product data sheet Rev. 3 — 3 August 2010 42 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

16.4 Reflow soldering

Key characteristics in reflow soldering are:

• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 43) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 16 and 17

Table 16. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220

Table 17. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245

Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.

Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 43.

Product data sheet Rev. 3 — 3 August 2010 43 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

maximum peak temperature

temperature = MSL limit, damage level

minimum peak temperature

= minimum soldering temperature

peak
temperature

time
001aac844

MSL: Moisture Sensitivity Level

Fig 43. Temperature profiles for large and small components

For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.

17. Abbreviations
Table 18. Abbreviations
Acronym Description
CDM Charged Device Model
DUT Device Under Test
ESD ElectroStatic Discharge
GPIO General Purpose Input/Output
HBM Human Body Model
I2C-bus Inter-Integrated Circuit bus
LED Light Emitting Diode
MM Machine Model
PICMG PCI Industrial Computer Manufacturers Group
PLC Programmable Logic Controller
POR Power-On Reset
PWM Pulse Width Modulation
RAID Redundant Array of Independent Discs
SMBus System Management Bus

Product data sheet Rev. 3 — 3 August 2010 44 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

18. Revision history

Table 19. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9698 v.3 20100803 Product data sheet - PCA9698 v.2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Figure 25 “Typical application”: text below figure corrected from “Device address configured as
‘0010 000x’ for this example.” to “Device address configured as ‘0100 000x’ for this example.”
• Table 14 “Static characteristics”, sub-section “Inputs RESET and OE” is corrected by removing
IOH specification.
PCA9698 v.2 20060719 Product data sheet - PCA9698_1
PCA9698 v.1 20060224 Product data sheet - -
(9397 750 13751)

Product data sheet Rev. 3 — 3 August 2010 45 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

19. Legal information

19.1 Data sheet status

Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.

19.2 Definitions malfunction of an NXP Semiconductors product can reasonably be expected

to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
Draft — The document is a draft version only. The content is still under
NXP Semiconductors products in such equipment or applications and
internal review and subject to formal approval, which may result in
therefore such inclusion and/or use is at the customer’s own risk.
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of Applications — Applications that are described herein for any of these
information included herein and shall have no liability for the consequences of products are for illustrative purposes only. NXP Semiconductors makes no
use of such information. representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended Customers are responsible for the design and operation of their applications
for quick reference only and should not be relied upon to contain detailed and and products using NXP Semiconductors products, and NXP Semiconductors
full information. For detailed and full information see the relevant full data accepts no liability for any assistance with applications or customer product
sheet, which is available on request via the local NXP Semiconductors sales design. It is customer’s sole responsibility to determine whether the NXP
office. In case of any inconsistency or conflict with the short data sheet, the Semiconductors product is suitable and fit for the customer’s applications and
full data sheet shall prevail. products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
Product specification — The information and data provided in a Product design and operating safeguards to minimize the risks associated with their
data sheet shall define the specification of the product as agreed between applications and products.
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however, NXP Semiconductors does not accept any liability related to any default,
shall an agreement be valid in which the NXP Semiconductors product is damage, costs or problem which is based on any weakness or default in the
deemed to offer functions and qualities beyond those described in the customer’s applications or products, or the application or use by customer’s
Product data sheet. third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
19.3 Disclaimers the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.

Limited warranty and liability — Information in this document is believed to Limiting values — Stress above one or more limiting values (as defined in
be accurate and reliable. However, NXP Semiconductors does not give any the Absolute Maximum Ratings System of IEC 60134) will cause permanent
representations or warranties, expressed or implied, as to the accuracy or damage to the device. Limiting values are stress ratings only and (proper)
completeness of such information and shall have no liability for the operation of the device at these or any other conditions above those given in
consequences of use of such information. the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
In no event shall NXP Semiconductors be liable for any indirect, incidental,
repeated exposure to limiting values will permanently and irreversibly affect
punitive, special or consequential damages (including - without limitation - lost
the quality and reliability of the device.
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such Terms and conditions of commercial sale — NXP Semiconductors
damages are based on tort (including negligence), warranty, breach of products are sold subject to the general terms and conditions of commercial
contract or any other legal theory. sale, as published at http://www.nxp.com/profile/terms, unless otherwise
Notwithstanding any damages that customer might incur for any reason agreed in a valid written individual agreement. In case an individual
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards agreement is concluded only the terms and conditions of the respective
customer for the products described herein shall be limited in accordance agreement shall apply. NXP Semiconductors hereby expressly objects to
with the Terms and conditions of commercial sale of NXP Semiconductors. applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without No offer to sell or license — Nothing in this document may be interpreted or
limitation specifications and product descriptions, at any time and without construed as an offer to sell products that is open for acceptance or the grant,
notice. This document supersedes and replaces all information supplied prior conveyance or implication of any license under any copyrights, patents or
to the publication hereof. other industrial or intellectual property rights.

Suitability for use — NXP Semiconductors products are not designed, Export control — This document as well as the item(s) described herein
authorized or warranted to be suitable for use in life support, life-critical or may be subject to export control regulations. Export might require a prior
safety-critical systems or equipment, nor in applications where failure or authorization from national authorities.

Product data sheet Rev. 3 — 3 August 2010 46 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

Non-automotive qualified products — Unless this data sheet expressly own risk, and (c) customer fully indemnifies NXP Semiconductors for any
states that this specific NXP Semiconductors product is automotive qualified, liability, damages or failed product claims resulting from customer design and
the product is not suitable for automotive use. It is neither qualified nor tested use of the product for automotive applications beyond NXP Semiconductors’
in accordance with automotive testing or application requirements. NXP standard warranty and NXP Semiconductors’ product specifications.
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in 19.4 Trademarks
automotive applications to automotive specifications and standards, customer
Notice: All referenced brands, product names, service names and trademarks
(a) shall use the product without NXP Semiconductors’ warranty of the
are the property of their respective owners.
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond I2C-bus — logo is a trademark of NXP B.V.
NXP Semiconductors’ specifications such use shall be solely at customer’s

20. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 3 — 3 August 2010 47 of 48

NXP Semiconductors PCA9698
40-bit Fm+ I2C-bus advanced I/O port with RESET, OE and INT

21. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 11.1 Performance curves. . . . . . . . . . . . . . . . . . . . 34
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 12 Dynamic characteristics. . . . . . . . . . . . . . . . . 37
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 13 Test information . . . . . . . . . . . . . . . . . . . . . . . 39
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 14 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 40
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 15 Handling information . . . . . . . . . . . . . . . . . . . 42
6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 16 Soldering of SMD packages . . . . . . . . . . . . . . 42
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 16.1 Introduction to soldering. . . . . . . . . . . . . . . . . 42
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 16.2 Wave and reflow soldering. . . . . . . . . . . . . . . 42
7 Functional description . . . . . . . . . . . . . . . . . . . 7 16.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42
7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 16.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43
7.2 Alert response, GPIO All Call and Device ID 17 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44
addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . 45
7.3 Command register . . . . . . . . . . . . . . . . . . . . . . 8 19 Legal information . . . . . . . . . . . . . . . . . . . . . . 46
7.3.1 5-bank register category . . . . . . . . . . . . . . . . . . 9 19.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 46
7.3.2 1-bank register category . . . . . . . . . . . . . . . . . . 9 19.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4 Register definitions . . . . . . . . . . . . . . . . . . . . . . 9 19.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46
7.4.1 IP0 to IP4 - Input Port registers . . . . . . . . . . . 11 19.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47
7.4.2 OP0 to OP4 - Output Port registers . . . . . . . . 11
20 Contact information . . . . . . . . . . . . . . . . . . . . 47
7.4.3 PI0 to PI4 - Polarity Inversion registers . . . . . 12
7.4.4 IOC0 to IOC4 - I/O Configuration registers. . . 12 21 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
7.4.5 MSK0 to MSK4 - Mask interrupt registers . . . 13
7.4.6 OUTCONF - output structure configuration
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.4.7 ALLBNK - All Bank control register. . . . . . . . . 14
7.4.7.1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.4.8 MODE - PCA9698 mode selection register . . 15
7.5 Device ID - PCA9698 ID field . . . . . . . . . . . . . 16
7.6 GPIO All Call . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.7 Output state change on ACK or STOP . . . . . . 17
7.8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 18
7.9 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.10 Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 18
7.11 SMBus Alert output (SMBALERT) . . . . . . . . . 19
7.12 Output enable input (OE) . . . . . . . . . . . . . . . . 20
7.13 Live insertion . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.14 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.15 Address map . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Characteristics of the I2C-bus . . . . . . . . . . . . 23
8.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8.1.1 START and STOP conditions . . . . . . . . . . . . . 23
8.2 System configuration . . . . . . . . . . . . . . . . . . . 24
8.3 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24
8.4 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 25
9 Application design-in information . . . . . . . . . 31
10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Static characteristics. . . . . . . . . . . . . . . . . . . . 33

Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 3 August 2010
Document identifier: PCA9698

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PCA9698

Uploaded by

PCA9698

Uploaded by

PCA9698

The device is fully configurable: output ports can be programmed to be totem-pole or

2. Features and benefits

 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os

Product data sheet Rev. 3 — 3 August 2010 2 of 48

Remark: All I/Os are set to inputs at power-up and RESET.

Product data sheet Rev. 3 — 3 August 2010 3 of 48

configuration port register data (Cx[y])

On power-up or RESET, all registers return to default values.

Product data sheet Rev. 3 — 3 August 2010 4 of 48

Fig 3. Pin configuration for TSSOP56

Product data sheet Rev. 3 — 3 August 2010 5 of 48

Transparent top view

Fig 4. Pin configuration for HVQFN56

6.2 Pin description

Product data sheet Rev. 3 — 3 August 2010 6 of 48

Table 2. Pin description …continued

7.1 Device address

Fig 5. PCA9698 device address

Product data sheet Rev. 3 — 3 August 2010 7 of 48

7.2 Alert response, GPIO All Call and Device ID addresses

• Alert Response address: allows to perform an ‘SMBus Alert’ operation as defined in

7.3 Command register

Fig 9. Command register

Product data sheet Rev. 3 — 3 August 2010 8 of 48

7.3.1 5-bank register category

7.3.2 1-bank register category

7.4 Register definitions

Product data sheet Rev. 3 — 3 August 2010 9 of 48

Table 3. Register summary …continued

Product data sheet Rev. 3 — 3 August 2010 10 of 48

7.4.1 IP0 to IP4 - Input Port registers

7.4.2 OP0 to OP4 - Output Port registers

Ox[y] = 0: IOx_y = 0 if IOx_y defined as output (Cx[y] in IOC register = 0).

Product data sheet Rev. 3 — 3 August 2010 11 of 48

7.4.3 PI0 to PI4 - Polarity Inversion registers

Px[y] = 0: The corresponding Input Port register data polarity is retained.

7.4.4 IOC0 to IOC4 - I/O Configuration registers

Cx[y] = 0: The corresponding port pin is an output.

Product data sheet Rev. 3 — 3 August 2010 12 of 48

7.4.5 MSK0 to MSK4 - Mask interrupt registers

7.4.6 OUTCONF - output structure configuration register

OUT001 controls the output structure for IO0_0 and IO0_1

OUT1 controls the output structure for bank 1 (IO1_0 to IO1_7)

OUTx = 0: The I/Os are configured with an open-drain structure.

OUTx = 1: The I/Os are configured with a totem-pole structure.

Product data sheet Rev. 3 — 3 August 2010 13 of 48

7.4.7 ALLBNK - All Bank control register

• B0 to B4 controls the logic level to be applied to Bank 0 to Bank 4, respectively.

• If ALLBNK = 0XX0 0000:

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• If ALLBNK = 1XX0 1100:

7.4.8 MODE - PCA9698 mode selection register

This register allows programming of the PCA9698 modes.

• OEPOL bit controls the polarity of OE pin.

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7.5 Device ID - PCA9698 ID field

For the PCA9698, the Device ID is as shown in Figure 10.

Fig 10. PCA9698 ID field

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7.6 GPIO All Call

7.7 Output state change on ACK or STOP

• OCH bit (Mode Selection Register, bit 1) must be equal to ‘0’.

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Remark: After programming a PCA9698, its state machine will be in a

7.8 Power-on reset

7.9 RESET input

7.10 Interrupt output (INT)

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7.11 SMBus Alert output (SMBALERT)

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7.12 Output enable input (OE)

7.13 Live insertion

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7.15 Address map

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2.3 V to 5.5 V operation with 5.5 V tolerant I/Os