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LVS CheatSheet WithDiagram

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Bharath Sai Bontala
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12 views2 pages

LVS CheatSheet WithDiagram

Uploaded by

Bharath Sai Bontala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LVS (Layout vs.

Schematic) – Quick Reference Cheat Sheet


What is LVS?
LVS (Layout vs. Schematic) is a critical step in Physical Verification that ensures the drawn layout
matches the intended schematic/netlist.

Inputs to LVS:
• Layout database (GDSII/OASIS)
• Schematic netlist (SPICE/Verilog – golden reference)
• Foundry LVS rule deck (device recognition + connectivity rules)

LVS Flow:
1. Extract devices from layout (using rule deck).
2. Generate an extracted netlist from layout.
3. Compare extracted netlist vs schematic netlist.
4. Report errors (if any) or declare LVS Clean.

Common LVS Errors:


■ Shorts – unintended net connections.
■ Opens – missing wires, broken connections.
■ Missing Device – present in schematic but not in layout.
■ Extra Device – present in layout but not in schematic.
■ Parameter mismatch – incorrect W/L, R, or C values.

Tool Commands (Example – Calibre):


• calibre -lvs mydesign.lvs
• Inside Virtuoso: check_lvs -layout mydesign.gds -schematic mydesign.sp -rules foundry.lvs

Tip: Always run DRC first, then LVS, and finally ERC before tape-out.
Foundry will not accept a design unless LVS is Clean.

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