2 CMOS Logic Structures

1 Introduction
In earlier discussions, we introduced CMOS logic under the assumption that MOS transistors
behave as ideal switches.

However, real MOS transistors exhibit certain limitations that deviate from this idealized
behavior.

So far, we have primarily focused on fully complementary CMOS logic structures and the
ratioed CMOS inverter.

Here we will explore:

1. Alternative CMOS logic configurations beyond fully complementary logic.

2. The impact of non-ideal switch behavior on circuit performance.
3. A comparative analysis of different logic structures to evaluate their advantages and
trade-offs.

1.1 Key Design Considerations

When designing CMOS circuits, two crucial aspects must be addressed to achieve the desired
performance:

1. Circuit (Structural) Design – This involves selecting the appropriate logic configuration
and transistor arrangements.
2. Layout (Physical) Design – This deals with the physical placement and interconnections
of transistors on a chip.

These two design phases are closely interconnected.

The behavior of circuits at a lower level can influence high-level architectural decisions.

Therefore, system designers must have a fundamental understanding of low-level circuit

design to make informed choices at higher levels of abstraction.

2 CMOS Logic Structures

In certain situations, fully complementary static CMOS gates may not be the most efficient
choice.

3 CMOS Complementary Logic

 The area required for implementation might be excessive, the speed may be too slow, or the
function may not be directly realizable using a purely complementary structure — such as in
the case of large Programmable Logic Arrays (PLAs).

In such cases, alternative CMOS logic structures can be employed to design smaller and faster
gates.

However, these improvements often come at the cost of increased design complexity, greater
operational challenges, and potential reductions in circuit stability.

2.1 Need for Alternative CMOS Logic Structures

The motivation for exploring alternative CMOS logic structures arises from the following factors:

Area Constraints: Fully complementary CMOS gates can occupy a large silicon area, which is
undesirable in high-density designs.

Speed Limitations: The propagation delay of traditional CMOS logic may be too high for
certain high-performance applications.

Design Feasibility: Some logic functions, such as those required in large PLAs, may not be
efficiently implemented using complementary CMOS alone.

To address these issues, alternative logic styles are explored, each with its own trade-offs in terms of
power consumption, speed, and complexity.

3 CMOS Complementary Logic

Complementary CMOS logic is widely used due to its robustness and ratioless operation.

3.1 Properties of CMOS Complementary Logic

Ratioless Operation: All complementary CMOS gates can be designed such that the circuit
functions correctly even when all transistors are of equal size.

Optimization: Although basic functionality is achieved with uniform transistor sizing, speed
optimization techniques involving different transistor sizes will be introduced later.

Complex Logic Implementation: More complex gates can also be implemented using CMOS
logic.

For example, a complex gate implementing the function:

Z = (A · B) + C · (D + E)

is used as a basis for comparison between various logic families.

4 Pseudo - nMOS Logic

 Figure 1: CMOS Complementary Logic

3.2 Substrate Connection Considerations

In the schematics, the substrate connection may be omitted. But it plays a crucial role in MOS circuit
behavior. The substrate connection impacts key electrical properties, such as:

Body Effect: Affects the threshold voltage of transistors, influencing circuit performance.

Leakage Currents: Improper substrate connections may lead to increased leakage or latch-up
issues.

Power Integrity: Proper substrate biasing ensures reliable operation across varying process
conditions.

This understanding of complementary CMOS logic forms the foundation for further discussions on
optimizing logic circuits for speed and efficiency.

4 Pseudo - nMOS Logic

A typical pseudo - nMOS gate is illustrated in figure below.

In this configuration, a single pMOS transistor acts as the load device, with its gate
permanently connected to ground (VSS).

This design is similar to conventional nMOS logic, where the depletion or enhancement-mode
nMOS load transistor is replaced with a pMOS device.

4 Pseudo - nMOS Logic

 Figure 2: Pseudo - nMOS Logic

4.1 Operation and Design Considerations

The pull-up device (pMOS) is always turned on, meaning the circuit operates with ratioed
logic, where the gain ratio of the p-load to the nMOS driver transistors, βload/βdriver, must be
carefully selected.
The transistor sizing must ensure proper switching and logic level generation. The effective
βn/βp ratio must be chosen in accordance with values derived from circuit equations.

One of the main drawbacks of pseudo-nMOS logic, as with conventional nMOS logic, is static
power dissipation. Since the pMOS load is always on, current continuously flows whenever
the pull-down network is active.

4.2 Transistor Count and Input Loading

An n-input pseudo-nMOS gate requires n+1 transistors.

In a fully complementary CMOS gate, the capacitive load on each input is at least two unit gate
loads. In pseudo-nMOS logic, the minimum input load can be just one unit gate load since only
a single transistor is used per input term.

However, if minimum-sized driver transistors are used, the pull-up gain must be reduced to
maintain adequate noise margins, which in turn slows the gate’s rise time.

4.3 Comparison with Conventional nMOS and CMOS Logic

Pseudo-nMOS gates do not have a significant advantage over conventional nMOS depletion
load gates, except that they allow emulation of nMOS circuits in a CMOS process.

One potential advantage of using a pMOS load is the absence of the body effect, which affects
nMOS depletion loads.
A pseudo-nMOS gate can offer a higher circuit density compared to fully complementary
CMOS gates due to the reduced transistor count.
In summary, pseudo-nMOS logic provides a method for implementing logic gates with fewer
transistors, but at the cost of static power dissipation and slower rise times in some cases.

5 Dynamic CMOS Logic

Dynamic CMOS logic is a logic family that reduces transistor count while achieving high-speed
operation.

Unlike static CMOS logic, which maintains a stable output using both pull-up and pull-down
networks, dynamic CMOS logic relies on clocked operation and charge storage principles.

The main features of dynamic CMOS logic are:

– Uses clock-driven precharge and evaluation phases.

– Reduces transistor count, leading to increased logic density.
– Offers higher speed compared to static CMOS due to reduced capacitance.
– Requires careful clock synchronization to avoid errors.

5.1 Structure and Working of Dynamic CMOS Gates

5.1.1 Basic Structure
A simple dynamic CMOS logic gate is shown in figure below.

Figure 3: Dynamic CMOS Logic

It consists of:

An nMOS logic network, responsible for evaluating the logic function.

 A pMOS precharge transistor, which charges the output to VDD during the precharge phase.

An nMOS evaluation transistor, which selectively discharges the output during evaluation.
A clock signal (ϕ), controlling the switching between precharge and evaluation phases.

5.1.2 Operation Phases

The dynamic CMOS gate operates in two main phases, controlled by the clock signal ϕ:

1. Precharge Phase (ϕ = 0)
The pMOS precharge transistor turns ON, charging the output node to VDD.
The nMOS evaluation transistor is OFF, preventing any discharge.
The output is temporarily set to HIGH regardless of input values.

2. Evaluation Phase (ϕ = 1)
The pMOS precharge transistor turns OFF.
The nMOS evaluation transistor turns ON, allowing the nMOS logic block to evaluate the
function.
If the input logic network forms a conducting path to ground, the output discharges to LOW.
If no conducting path exists, the output remains at its precharged HIGH state.
This approach reduces the number of transistors needed, since a pull-up network is not required.

5.2 Limitations and Challenges

Although dynamic CMOS logic provides higher speed and reduced area, it has several challenges:

5.2.1 Charge Leakage and Charge Sharing

The output node holds charge dynamically without a steady pull-up.
Over time, leakage currents can reduce the output voltage, causing incorrect logic levels.
Charge sharing between nodes can alter the stored charge, leading to unstable outputs.

5.2.2 Input Switching Restriction

Inputs must only change during the precharge phase.
If inputs change during evaluation, charge redistribution effects may corrupt the output.

5.2.3 Cascading Issue

Dynamic CMOS gates cannot be directly cascaded using a single-phase clock.
 The first gate must evaluate before the next stage begins evaluation, causing timing
constraints.

Figure 4: Cascaded Dynamic CMOS

5.3 Multi-Phase Clocking Strategies

To overcome cascading issues, multi-phase clocking techniques are used. These techniques
introduce additional clock phases that improve charge retention, control signal propagation, and
enable correct logic evaluation.

5.3.1 Four-Phase Dynamic Logic

The four-phase logic approach introduces a structured clocking sequence that ensures that outputs
are properly evaluated and stored before being used as inputs in the next stage.
 Figure 5: 4- Phase Logic

Working Principle The four-phase logic cycle consists of:

Phase ϕ1 (Precharge of PZ): During this phase, node PZ is precharged to VDD, while node Z
retains its previous value.

Phase ϕ2 (Precharge of Z): The precharge of node PZ is maintained, and a transmission gate
turns on, allowing node Z to also precharge.

Phase ϕ3 (Evaluation): The gate evaluates, and if the pull-down network is activated, node PZ
discharges conditionally.

Phase ϕ4 (Hold Phase): Node Z is held in its evaluated state, ensuring that it does not change
prematurely.

Advantages
Reduces charge-sharing issues by ensuring proper storage of values before evaluation.
Enables cascading of multiple logic stages without the risk of premature discharge.
Ensures that evaluated values remain stable during computation.

Limitations
Requires four separate clock signals, increasing circuit complexity.
Additional clocking transistors increase power consumption.
Strict timing requirements must be met for reliable operation.
5.3.2 Two-Phase Dynamic Logic
An alternative to four-phase logic is a two-phase approach, which simplifies clocking at the cost of
slightly reduced reliability.

Figure 6: 2- Phase Logic

Working Principle A two-phase logic scheme utilizes alternating clock cycles:

Phase ϕA: Certain gates evaluate their logic function.

Phase ϕB: Other gates evaluate, while the outputs of the previous phase are held constant.

Advantages
Reduces the number of required clock signals from four to two.
Simpler circuit design and reduced power consumption compared to four-phase logic.

Limitations
More susceptible to charge leakage compared to four-phase logic.
Requires careful synchronization to prevent timing mismatches.

Table 1: Comparison of Two-Phase and Four-Phase Logic

Feature Four-Phase Logic Two-Phase Logic
Clock Signals Four (ϕ1,ϕ2,ϕ3,ϕ4) Two (ϕA,ϕB)
Stability Higher, due to hold phases Moderate, more charge leakage
Circuit Complexity Higher Lower
Power Consumption Higher Lower
Suitability for Cascading More suitable Requires careful
synchronization
5.4 Transistor Count Analysis
The number of transistors in dynamic CMOS logic is significantly lower than in static CMOS:
A static CMOS logic gate requires 2N transistors for an N-input gate.
A dynamic CMOS gate requires N+2 transistors.
The reduced transistor count results in lower capacitance and higher speed.

5.5 Advantages of Dynamic CMOS Logic

High Speed: Reduced capacitance leads to faster switching times.

Lower Power Consumption: Only consumes dynamic power during switching.

Reduced Area: Uses fewer transistors compared to static CMOS.

5.6 Disadvantages of Dynamic CMOS Logic

Charge Leakage: Output logic levels degrade over time.

Timing Constraints: Requires careful synchronization of clock signals.

Complex Cascading: Cannot directly cascade without multi-phase clocking.

 6 Clocked CMOS Logic (C†MOS)

5.7 Conclusion
Dynamic CMOS logic is a powerful alternative to static CMOS for high-speed, low-power digital
circuits. However, its reliance on clock-driven operation introduces challenges such as charge
leakage and complex timing synchronization. Proper clocking techniques, such as two-phase and
four-phase logic, are necessary for reliable operation.

†
6 Clocked CMOS Logic (C MOS)
Clocked CMOS logic, also known as C†MOS, is a dynamic logic technique that enhances power
efficiency and integrates latches within logic circuits. Originally developed for low-power CMOS logic
†
design, C MOS is now primarily used for synchronizing dynamic circuits and interfacing with other
clocked logic structures.

6.1 Structure and Operation

 Figure 7: Clocked CMOS Logic (C†MOS)

A typical clocked CMOS gate consists of:

6 Clocked CMOS Logic (C†MOS)

A standard CMOS logic gate.

Additional transistors controlled by a clock signal (ϕ) to regulate switching behavior.

During operation:

When ϕ = 0, the circuit holds its previous state.

When ϕ = 1, normal evaluation occurs.

6.2 Advantages of C†MOS Logic

Reduced Power Dissipation: Originally designed for metal-gate CMOS, the clocked design
minimizes unnecessary switching activity.

Latching Capability: C†MOS logic inherently functions as a latch, holding data when the clock
is low.

Compatibility with Dynamic Logic: It effectively interfaces with other dynamic logic families,
improving timing synchronization.

6.3 Limitations of C†MOS Logic

Increased Rise and Fall Times: Due to additional clocking transistors in series, switching
speed is reduced.

Higher Input Capacitance: Although similar to static CMOS gates, the presence of clocking
elements increases parasitic capacitance.

Complex Timing Requirements: The circuit behavior depends on the correct synchronization
of clock signals.

6.4 Applications
C†MOS logic is widely used in:
Low-power digital circuits.

Clocked latches and flip-flops.

Interface circuits between static and dynamic logic.

6.5 Conclusion
Clocked CMOS logic provides a power-efficient and synchronous alternative to conventional static
CMOS gates. While it introduces increased rise and fall times, its benefits in latch-based designs and
dynamic logic interfacing make it a crucial component in modern VLSI systems.

7 Cascade Voltage Switch Logic (CVSL)

7 Cascade Voltage Switch Logic (CVSL)

Cascade Voltage Switch Logic (CVSL) is a differential CMOS logic style that utilizes both true
and complement input signals for computation.

Unlike conventional static CMOS logic, CVSL relies on two complementary nMOS switching
networks, combined with cross-coupled pMOS transistors for positive feedback.

7.1 Structure and Operation

Figure 8: Cascade Voltage Switch Logic (CVSL)

A typical CVSL gate consists of:

Two complementary nMOS logic trees that implement the desired logic function.

Cross-coupled pMOS pull-up transistors that ensure positive feedback and bistable
operation.

The key working principle involves:

1. Differential Signaling: The logic trees receive both the input and its complement, ensuring
robust operation.
2. Pull-Up Mechanism: The cross-coupled pMOS transistors ensure that one output node is
strongly pulled high while the other remains low.

3. Switching Mechanism: When the inputs change, one of the nMOS logic trees will conduct,
forcing one node to be pulled low while the other remains high, resulting in a strong logic
transition.
7.2 Advantages of CVSL
Strong Signal Integrity: Positive feedback ensures sharp transitions and improved noise
immunity.

Logical Completeness: CVSL can implement any logic function efficiently, making it suitable
for automated logic synthesis.

Lower Power Consumption: Unlike domino logic, CVSL gates do not require precharge and
evaluate cycles, reducing dynamic power dissipation.

7.3 Limitations of CVSL

Increased Complexity: CVSL requires both true and complement signals, increasing the
number of interconnections.

Larger Area Requirement: Additional routing and double-rail logic consume more chip area.

Slower Switching Speed: During transitions, the pMOS pull-ups must counteract the nMOS
pull-down networks, leading to delays compared to conventional static CMOS gates.

7.4 Applications
High-speed arithmetic and logic units (ALUs) in microprocessors.

Circuits requiring differential signaling for noise reduction.

Automated logic synthesis applications where arbitrary logic expressions need to be

implemented efficiently.

7.5 Conclusion
CVSL is a powerful logic family that provides robust differential operation and logical completeness
at the cost of increased complexity and area. While it may not always be as fast as traditional CMOS
or domino logic, its ability to implement any logic function makes it useful in specific applications.

8 Pass Transistor Logic

Pass Transistor Logic (PTL) is an alternative logic design methodology that reduces transistor
count and enhances circuit efficiency.

It is particularly popular in nMOS circuits, with a fundamental application being the 2-input
multiplexer.

A notable implementation of PTL is found in the ALU function unit of the OM-1 computer.
8.1 nMOS and CMOS Implementations of Pass Transistor Logic
8.1.1 nMOS Pass Transistor Logic

In nMOS-based PTL, the pass transistors are used to steer signals to the output based on
control inputs.

Figure below illustrates the nMOS structure, where only nMOS transistors are used.

Figure 9: nMOS PTL

Advantages:

Provides the fastest fall time due to strong nMOS pull-down.

Disadvantages:

Suffers from threshold voltage loss (Vth drop), leading to degraded high-level signals.

8.1.2 CMOS Pass Transistor Logic

To overcome the limitations of nMOS PTL, a CMOS version can be designed by replacing each
nMOS transistor with a full transmission gate, as shown in figure below.

Figure 10: CMOS PTL

CMOS PTL uses both nMOS and pMOS transistors, ensuring full voltage swing.
 This implementation provides strong pull-up and pull-down characteristics.

8.2 Alternative Implementations of Pass Transistor Logic 8.2.1

Optimized Layout for CMOS PTL

Figure 11: Modified CMOS for better layout

A more realizable layout is depicted in above figure, which:

Reduces direct n-to-p transistor connections.

Enhances circuit practicality and performance.

8.2.2 Dynamic Pass Transistor Logic

Figure 12: Dynamic PTL (p-pullup version)

Figure above shows a dynamic version of PTL, which requires a precharge phase before operation.
Performance comparison:
Comparable speed to nMOS PTL.
 Requires a precharge period, which may extend clock cycle times.
8.2.3 Static Pass Transistor Logic with Feedback Buffer

An alternative to the dynamic version is the static PTL implementation, where:

A feedback buffer drives the p-transistor pull-up.

This design achieves zero DC power dissipation.

To ensure correct operation, the p-transistor pull-up and n-transistor pull-down must be
properly ratioed.

8.3 Formal Methods for Designing Pass Transistor Logic

Formal methods for deriving pass transistor networks in nMOS have been developed by Whitaker.
These methods are based on:

1. A model as shown in figure below, where control variables steer a pass transistor network.

2. The pass function, which determines how input variables propagate through the network.

Figure 13: PTL model

8.3.1 XOR Gate using Pass Transistor Logic

Table 2: Truth table of XOR gate

A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Let us take A as control signal.
 We can observe from the truth table that:

– When A = 0; Y = B.

– When A = 1; Y = B

The PTL implementation of XOR gate is shown in figure below.

Figure 14: PTL structure for XOR function.

8.4 Challenges and Considerations in Pass Transistor Logic

While PTL offers advantages in reducing transistor count and increasing speed, several challenges
must be addressed:

1. Voltage Degradation (Vth drop)

The output voltage may not reach the full supply level due to threshold voltage loss in
nMOS PTL.
Complementary pass networks (nMOS + pMOS) help mitigate this but introduce
additional delay.

2. Increased Internal Node Capacitance

The merging of source and drain regions makes PTL design complex, leading to higher
internal capacitances.

3. Requirement for Complementary Control Signals

Both true and complemented versions of control variables are needed, increasing
circuit complexity.

4. Slower Pull-Down in Complementary Structures

Complementary PTL networks incur extra delay in pull-down operations compared to

standard CMOS gates.
8.5 Best Practices for Pass Transistor Logic
To achieve efficient PTL circuits, the following techniques should be considered:

Precharged Output Nodes: Helps mitigate voltage degradation issues.

 Static PTL with Feedback Buffers: Ensures full voltage swing and eliminates DC power
dissipation.

Complementary Pass Networks (CVSL): Can be integrated with CVSL logic for improved
performance.
Finally, any PTL design should be evaluated through simulation and layout analysis to determine
its effectiveness for a given application.

8.6 Conclusion
Pass Transistor Logic (PTL) provides an efficient alternative to conventional logic gates,
particularly in multiplexers, arithmetic logic units (ALUs), and XOR gates.
While PTL reduces transistor count and improves speed, it introduces challenges such as
threshold voltage drop, increased capacitance, and control signal complexity.

By using complementary networks, precharge techniques, and static implementations,

these challenges can be mitigated, making PTL a valuable approach for optimized circuit
design.

9 Electrical and Physical Design of Logic Gates

9.1 The Inverter
9.1.1 Basic Schematic Representation

Figure below illustrates the standard CMOS inverter circuit, where:

The pMOS transistor is connected to the power supply (VDD).

The nMOS transistor is connected to ground (VSS).

The input is applied to both transistor gates.

The output is taken from the connection between the pMOS drain and nMOS drain.

Figure 15: CMOS Inverter Circuit

In a schematic, connections are represented by lines. However, in a physical layout, interconnections
involve different materials such as polysilicon, diffusion regions, and metal layers.

9.1.2 Physical Layout Considerations

To implement the inverter physically, we must account for:

The nMOS source and drain being in n-diffusion.

The pMOS source and drain being in p-diffusion.

The fact that direct n-diffusion to p-diffusion connections are not possible in bulk CMOS.

The need for metal interconnects to connect different layers.

Figure below shows the symbolic layout representation where:

The inverter’s drains are connected using a metal wire and two contacts.

Power (VDD) and ground (VSS) connections use metal for low resistance.

The gate connection is made using a polysilicon wire.

Figure 16: Symbolic layout representation of CMOS Inverter

The corresponding layout is shown in figure below.

 Figure 17: Standard Layout of CMOS Inverter

An alternative layout is shown in figure below where the transistors are aligned horizontally.

Figure 18: Layout of CMOS Inverter with horizontal transistors

9.1.3 Alternative Layout Strategies

Topology Variations Different topologies exist for inverter layouts:

1. Horizontal Metal Straps with Vertical Polysilicon:

Suitable when a metal line must pass through the cell.

The vertical polysilicon connects the transistor drains.

Figure 19: Alternative CMOS inverter layout with vertical polysilicon

 2. Power and Ground in Diffusion Layers:
Enables horizontal metal interconnections through the cell.
Reduces metal congestion.

Figure 20: CMOS inverter layout with diffusion power and ground

Performance Considerations

Using a vertical polysilicon drain connection introduces extra resistance and capacitance:
Rtotal ≈ 2Rcontact + Rpoly
where Rcontact is the resistance of a metal-polysilicon contact, and Rpoly is the resistance of the
polysilicon wire.

Using diffusion for power and ground connections adds series resistance and
capacitance.

To ensure good performance, the resistance should be at least an order of magnitude lower
than the transistor’s “on” resistance.

Using Additional Metal Layers The introduction of a second metal layer enhances layout
flexibility:

The second metal layer can be used for VDD and VSS supply lines.

Alternatively, it can be used to strap polysilicon to reduce resistance and improve signal
propagation.

Layouts remain largely unchanged except for the addition of metal-2 wires and metal-1
connection stubs.
 Figure 21: CMOS inverter layout using additional metal layers

9.1.4 Large Inverter Designs

A large inverter can be created by parallelizing smaller inverters.

Source and drain regions are merged to reduce resistance.

The diffusion regions are stitched together to minimize parasitic capacitance.

Figure 22: Large CMOS inverter using parallel transistors

Further improvements can be achieved by placing transistors back-to-back to optimize drain

capacitance.
 Figure 23: Back-to-Back transistor placement for large inverters

9.1.5 Advanced Drain Capacitance Reduction

Further drain capacitance reduction can be achieved using the star connection.

The transistors’ drains form a single continuous region.

No corner gaps exist, which increases transistor gain (β) while minimizing capacitance.

The effective gain is quadrupled with minimal drain area increase.

Figure 24: Star connection for CMOS inverter layout optimization

9.2 NAND Gate
The design principles used for the CMOS inverter layout can be extended to implement NAND
and NOR gates.

The layout considerations involve transistor orientation, interconnect optimization, and

capacitance minimization.

9.2.1 NAND Gate Layout

Basic Layout Translation

A 2-input NAND gate can be implemented using a combination of series nMOS transistors and
parallel pMOS transistors.

Figure below represents the direct translation of schematic into layout of a 2-input NAND gate.

Figure 25: Basic layout translation of a 2-input NAND gate

Horizontal Transistor Orientation

By orienting the transistors horizontally, we obtain the layout shown in figure below, which is
cleaner and more compact.
 Figure 26: Optimized layout for NAND Gate

9.2.2 Design Style

For multiple-input static gates, the following layout style is adopted:

Transistors are oriented horizontally.

Polysilicon gate signals run vertically.

In cases where deviations from this style occur, specific design reasons will be provided.

The NAND gate could be rotated by 90◦ to have vertical metal and horizontal polysilicon
connections.

9.3 NOR Gate

9.3.1 NOR Gate Layout

Symbolic Layout A 2-input NOR gate follows the opposite arrangement of the NAND gate, where:

nMOS transistors are in parallel.

pMOS transistors are in series.

The symbolic layout of the NOR gate is shown in figure below.

 Figure 27: Symbolic layout of NOR gate

Alternative Layout for Faster Performance An alternative NOR layout is shown in figure below,
where the connection to the parallel transistors is optimized.

Figure 28: An alternative layout of NOR gate

The alternative layout has the following advantages:

Reduced drain area connected to the output, minimizing capacitance.

Faster gate operation, since the reduced capacitance improves switching speed.

The same optimization can be applied to the NAND gate, improving its speed.
9.4 Factors Affecting Complex Gate Design
For more complex logic gates, four key factors influence their electrical and physical design:
1. Series Transistor Connection: Increased resistance affects speed.

2. Body Effect: Threshold voltage variation impacts performance.

3. Source-Drain Capacitance: Larger diffusion areas increase capacitance.

4. Charge Redistribution: Affects node voltages and dynamic behavior.

9.5 Body Effect

The body effect refers to the modification of the threshold voltage (Vt) due to a voltage difference
between the source and substrate. Specifically, the threshold voltage variation can be expressed as:
∆Vt = γpVsb
where:
∆Vt is the change in threshold voltage,

Vsb is the source-to-body voltage,

The proportionality constant (γ) depends on the fabrication process.

9.5.1 Impact on NAND Gates

In a multi-input NAND gate, the nMOS transistor at the output switches slower if its source
potential is not the same as the substrate.
Figure below illustrates such a scenario.

Figure 29: Multiple-input NAND gate affected by body effect

Consider the situation in figure below:

Figure 30: Capacitive charging effect in body effect

Initially, nMOS transistors A, B, and C are OFF (VgsA = VgsB = VgsC = 0).

The nMOS transistor D is turned ON, causing VgsD = VDD.

When transistor D is switched OFF, the internal node capacitance C1 gets charged, leading to a
nonzero Vsb.

If all inputs are then driven HIGH (VgsA = VgsB = VgsC = VDD), the source of transistor D will be at
VDD − Vt.

The fall time of the gate output will be slower than expected due to this internal charge
buildup.

9.5.2 Minimizing the Body Effect

To reduce body effect and improve circuit speed, the following strategies should be used:

Minimize internal node capacitance to reduce parasitic charging effects.

Consider the relative impact of body effect in nMOS and pMOS transistors.

If nMOS body effect is worse, using NOR structures instead of NAND may be preferable.

9.5.3 Optimization Techniques

Since body effect is a dynamic issue related to parasitic capacitances, two optimization techniques
can be applied:

1. Optimized Transistor Placement:

Place transistors with late-arriving signals closest to the output.

 Early-arriving signals discharge internal nodes, reducing body effect for transistors
switching later.

2. Minimizing Internal Node Capacitance:

Use metal interconnects instead of diffusion wires for internal node connections.
If buried contacts are allowed, use polysilicon instead of diffusion for interconnects.
Minimize the diffusion area attached to transistors to reduce parasitic capacitance.

9.6 Physical Layout of Logic gates

All complementary CMOS gates can be designed using a single row of nMOS transistors and a
single row of pMOS transistors, aligned at common gate connections.
Most simple gates can be designed using an unbroken row of transistors, following the line of
diffusion rule.
This means that source-drain connections are made by abutment.

9.6.1 Graph Representation of CMOS Circuits

To automate layout generation, a graph-theoretic approach is used.
The CMOS circuit is converted into a graph, where:

1. Vertices represent the source/drain connections.

2. Edges represent transistors that connect particular source-drain vertices.
This results in two graphs: one for the nMOS network and another for the pMOS network.
An example of this graph transformation is shown in figure below.

Figure 31: CMOS logic gate graph representation

 The p-graph and n-graph are dual to each other, as the pMOS pull-up network is the
complement of the nMOS pull-down network.

9.6.2 Euler Paths in CMOS Layout

If two edges are adjacent in the p- or n-graph, then:
They may share a common source-drain connection.
They can be connected by abutment.
A gate can be designed through breaks if an Euler path exists in both the p-graph and n-graph with
identical labeling. The main algorithm for finding such paths is:

1. Find all Euler paths in the graph.

2. Identify a p- and n-Euler path with identical labeling.

3. If none exist, break the gate in the minimum number of places to achieve this condition.
An Euler path example and the corresponding layout generation is shown in figure below.

Figure 32: Euler paths in CMOS gate and the corresponding layout
9.6.3 Automated Layout Techniques
A graph-theoretic approach can automate layout generation, using interval graphs to optimally
place transistors in a gate matrix style.
 The final layout is shown in figure below.

Figure 33: Outline of automated approach to CMOS gate layout

Steps in this approach:

1. Group transistors in strips to maximize source/drain abutment.

2. Interchange polysilicon columns to improve abutment.
3. Place transistor groups in rows, with VDD and GND rails at the edges.
4. Route connections using metal or diffusion wires.

10 Input-output (I/0) structures

CMOS I/O structures are critical in VLSI due to their sensitivity to both circuit design and
process-specific characteristics.
 In practice, system designers should use well-characterized library cells instead of designing
pads from scratch.

These notes provide foundational insights into the structure and layout of I/O pads.

10.1 Overall Organization of I/O Pads

Standard pad size: ∼ 150µm × 150µm, suitable for bond wire attachment.

Connection points and VDD/VSS rails are placed consistently for uniformity.
Wider power/ground buses are used based on worst-case power estimates; multiple pads may
be employed to reduce noise.

Often, VSS is placed as the outermost rail for protection.

Figure below illustrate some of these concepts.
 Figure 34: General pad layouts

Pad frames may be auto-generated from text descriptions. Example:

LEFT;
INPUT A
INPUT B TOP;
VDD VDD
INPUT C
RIGHT;
OUTPUT Z
OUTPUT Y
BOTTOM;
 OUTPUT W
VSS VSS

The resulting I/O frame is shown in figure below.

Figure 35: I/O frame generation

10.2 VDD and VSS Pads

Simple metal pads connected directly to power rails.
If discontinuity occurs, complete the path using:

– Polysilicon bridges as shown in figure below.

Figure 36: VDD pad design

– Multi-metal crossover with sufficient vias

10.3 Output Pads

Key Requirements
Sufficient drive strength to drive capacitive loads.
Adequate rise/fall times.
DC characteristics compliance when driving TTL or other logic levels.

Design Strategy
Use two-stage inverters with optimal sizing (2.7:1 or within 2–10 range).
 Include buffering to reduce internal loading.
Apply latch-up protection:

– Separate nMOS/pMOS regions

– Use guard rings tied to VDD/VSS

TTL Load Compatibility

CMOS VOH = 5V, TTL VIH = 2.4V ⇒ OK

CMOS VOL = 0V, TTL VIL = 0.4V ⇒ OK

Must sink 1.6mA for LOW state ⇒ usually not an issue

10.4 Input Pads

The design of input pads shares several principles with output pad design, particularly in
terms of transistor sizing.
In fact, transistors used in output pads can often be reused by simply reversing their function.

However, one critical issue must be addressed in input pad design: electrostatic discharge
(ESD) protection.

High Input Resistance and Gate Breakdown

The gate of a MOS transistor typically exhibits very high input resistance, in the range of 1012
to 1013 Ω.

As a result, even tiny leakage currents can cause a substantial voltage build-up across the gate
oxide.

The voltage V that develops on the gate can be estimated using the equation:

where:

– I is the charging current,

– ∆t is the charging time, and – Cg is the gate capacitance.

Example: Let:
I = 10µA, Cg = 0.03pF, ∆t = 1µs
Then:
 330V
Such high voltages can easily exceed the oxide breakdown voltage (typically 40 - 100 V),
causing permanent damage.

ESD Protection: Clamp Diodes and Series Resistance

Figure 37: Typical input protection circuit

To protect the gate from high-voltage transients, input pads include a resistor and diode
clamps:

– Clamp Diodes (D1 and D2): Turn on if the input voltage exceeds VDD or falls below VSS.
– Series Resistor (R): Limits the peak current during voltage excursions. Typical values:
200Ω to 3kΩ.

Note: The resistor and the parasitic input capacitance form an RC time constant, which
can limit high-speed operation.

A polysilicon resistor is preferable over a diffusion resistor in a p-well process, as it reduces

unwanted substrate charge injection and helps avoid latch-up.

In an n-well process, full n-device I/O circuitry can be built.

Here, n+ diffused protection resistors and punch-through devices are employed:

– A punch-through device has closely spaced source and drain regions but no gate.
– It acts like an avalanche diode, turning on around 50 V.
– This structure does not require additional well formation.

Interfacing TTL Logic with CMOS

When interfacing TTL outputs with CMOS inputs:
 TTL levels: VOL = 0.4V, VOH = 2.4V

CMOS inverters should switch around 1.4 V (midpoint of TTL range)

This can be achieved either by:

Ratioing the p- and n-MOS sizes in the inverter, or

Using a reference voltage.

In some cases, the TTL output may use an external resistor to 5 V to improve VOH. This resistor
can even be integrated into the pad using a p-MOS transistor.

10.5 Tri-state Pads

Based on tri-state inverter design.

Alternate design, as shown in figure below, offers faster switching.

Figure 38: Tri-state Pad

Must prevent short-circuit (DC) current during transitions.

10.6 Bi-directional Pads

Combine input pad + tri-state output buffer.

Example shown in figure below.

 Figure 39: Bi-directional Pad

Useful for shared data/address lines.