Bapuji Educational Association®

BAPUJI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DAVANGERE-577 004

Department of Electronics & Communication Engineering

Odd Semester 2024-25

Quiz Question Bank
Course Name: Hardware Description Language Course Code: VLSI05N04
Semester /Sec: 7th / A & B Date: 02/12/2024

Q.
Questions
No.
1 Code coverage is specification coverage, while functional coverage is implementation
coverage.
a) TRUE b) FALSE
2 Which of the following methods can be used to specify the time unit and precision?
a) `timescale compiler directive
b) System Verilog keywords "timeunit" and "timeprecision"
c) Specify them through compile switch –timescale with the vlog command
d) All of the above
3 Which of the following system tasks can be used to schedule simulation breakpoints?
a) $stop b) $finish
c) $timeformat d) $display
4 Which of the following is a legal name in SystemVerilog?
a) $Data_Bus b) _Data_Bus
c) 01_Data_Bus d) None of the above
5 The binary representation of 4’hCA in SystemVerilog is.
a) 1100 b) 1010 c) 100 d) 11001010
6 If you have an 8- bit logic vector named Z, you can set all bits of Z to ‘1’ by writing.
a) Z=1; b) Z='hF; c) Z='1; d) All of the above
7 Default initial value for variables of “logic” type is ‘X’ while variables of “bit” data type are
initialized to ‘0’.
a) TRUE b) FALSE
8 Consider this declaration: “enum logic [2:0] { RED = 3’b001, GREEN=3’b010,
BLUE=3’b011} color”. Which of the following is a legal assignment?
a) color = 3'b001; b) color = 3;
c) color = RED; d) color = color'(3'b010);
9 When the syntax ( .clk, .rst, …) is used to make port connections, this means that.
a) ports are left unconnected.
b) ports are connected to signals of the same name and size.
c) ports are connected by order.
d) None of the above
10 Which of the following statements is true?
a) Initial blocks start before always blocks.
b) Always blocks start before initial blocks.
c) System Verilog does not specify the order to start initial and always blocks.
d) None of the above.
11 A SystemVerilog function must.
a) Always returns a value.
b) Must have at least one input.
c) Must be recursive.
d) Must execute in zero time.

Vision of the Department

To be in the forefront in providing quality technical education and research in Electronics & Communication Engineering
to produce skilled professionals to cater to the challenges of the society
 Bapuji Educational Association®
BAPUJI INSTITUTE OF ENGINEERING AND TECHNOLOGY, DAVANGERE-577 004
Department of Electronics & Communication Engineering

Q.
Questions
No.
12 If an array’s size changes often and the index of an entry is able to change, what array type
should you choose?
a) A queue b) An associative array
c) A string d) A fixed-size array
13 What is the most common import type?
a) Wildcard import: import my_pkg::*.
b) Explicit import: import my_pkg::my_name.
c) Direct reference: y = my_pkg::my_var.
d) None of the above
14 If “my_bus” is an interface that connects to module mod1, which of the following can be a
correct header for mod1?
a) module mod1 (input logic clk, input logic rst, output logic [7:0] data);
b) module mod1 (input my_bus);
c) module mod1 (my_bus inf_port);
d) None of the above
15 Why do we use the final block?
a) To close log files b) To report the simulation results
c) Both a and b d) None of the above
16 In OOP, what is a property?
a) A task b) A variable
c) An object d) None of the above
17 The fork-join any functions similar to
a) a logic and gate b) a logic or gate
c) a wire d) None of the above
18 Which blocking statement can be used to ensure blocking until all child threads of fork-
join_none are done?
a) wait fork b) #0 ns
c) #100 ns d) None of the above

These types of questions asked in written test of product and service based companies like
synopsys,nvidia,cadence,nxp,mentor graphics,qualcomm,xilinx,amd and intel etc.
Answers: 1.b 2.d 3.a 4.b 5.b 6.c 7.a 8.c 9.b 10.c 11.d 12.a 13.a 14.c 15.c 16. b 17.b 18.a

Dr.Banumathi K L
Smt. Savithri G R Dr.Banumathi K L Dr.Nirmala S O Dr. G S Sunitha
Course Instructors Course Coordinator DQAC Program Coordinator

Vision of the Department

To be in the forefront in providing quality technical education and research in Electronics & Communication Engineering
to produce skilled professionals to cater to the challenges of the society