[1] Passive circuit

Characteristic impedance: Parallel-wire line

Characteristic impedance: coaxial transmission line

Velocity Factor
Characteristic impedance: microstrip transmission line

Reflection coefficient: ΓL

Where:
- ZL = line impedance
- Zo = load impedance

Voltage standing wave ratio (VSWR):

Where:
- ΓL = reflection coefficient
2-port parameters: S11, S12, S21, S22
S21 = power flowing from input to output (forward voltage gain)
S11 = reflection coefficient measured in port 1
S22 = reflection coefficient measured in port 2
S12 = power flowing from output to input (reverse voltage gain)

Q-factor, conversion between components, conversion between parallel/series

Unloaded Q - Inductors

Unloaded Q – capacitors

Loaded Q

Example:
Conversion table:

Matching technique: Quarter-Wave transformers

Matching technique: L-section matching on paper

When Rsource < Rload:

When Rsource > Rload:

Matching technique: L-section matching by simulation

Low pass: shunt L + series C

High pass: series L + shunt C

Example:

Since load is purely resistive, PORT 1 sees an impedance on the 0 reactance line (marked by red
circle):
Match the circle to point B either by adding:
1. Shunt cap -> Series ind
2. Shunt ind -> series cap

Limitation:

High-pass low-pass

Resonates at 100 MHz, very poor bandwidth bad insertion loss

1. Low loaded Q
2. Bandwidth determined by input and output impedances
3. Can be improved by T and π networks
Matching technique: π-matching (with specific Q)

Plot constant Q-circle: linear -> circles -> Q_CONT

Matching steps:
1. Match PORT 1 impedance to constant Q circle
2. Continue the steps from L-section match

Compared to L-section:
• Better insertion loss
• Better Q factor (therefore operable 3dB bandwidth)
Matching technique: T-matching (with specific Q)

Same with π-matching but 2 series elements and 1 shunt element

T network Pi network
Low pass

High pass

Matching technique: complex conjugate match [if ZL is complex, not purely resistive]

Same with L-section matching but match to conjugate

Filter technique: transmission zeros
Matching technique: transmission line match

1. Start with a 0-length transmission line connected in series

2. Tune the line such that it intersects with a constant-conductance or constant-resistance

circle

3. Then add a shunt/series element to complete the match

a. Shunt element : TLOC/TLSC
b. Series element: C/L

Think about distributed/lumped components

TLSC = inductor TLOC = capacitor

Downside: TLSC and TLOC elements are always in shunt

• When using tx line match, make sure to tune your electrical length until you can add a
shunt element
Downside:
• Frequency response is poor for TLOC
o At double the desired frequency, there will be a drop in insertion loss (S21) because
the 45° line now looks like a 90° line (electrical length ∝ frequency)
o This flips whatever is at the end of the line (OC -> SC)
o No power goes in, all reflected
*note: for every 1° of electrical length, you’re turning 2° on a constant-VSWR circle on the smith
chart, that’s because
 [2] Active Circuit
Transistor design: biasing, resistor values, dc blocking capacitors

Common-emitter configuration:

To find the bias, connect IVCURVEI [Swp-> collector, Step -> B]

To find RC and RBias:

To verify: Add annotation -> add DCIA, DCVA_N

Transistor design: high frequency model, parasitics, ideal vs real

Measuring port parameters require putting a source at collector & base, has source resistance Rs
• Will divert current back into source terminal
• To block current backflow, use DC-blocking capacitors → DC current can’t flow through,
isolates DC network with RF network
Problem: although DC current can’t go through, RF current can
• source impedance = power loss
1
• increasing C will decrease Z [𝑍 = 𝑗𝜔𝐶 ], but never to 0, ideally we want Z=0

Solution: capacitor has Lp and RESR, they resonate at fres, this will lead to Z=0
• plot smith chart and tune f until point intercepts with real-axis

Transistor design: RF chokes, measuring feedback and choosing appropriate value

Problem: we equally don’t want RF current to flow into DC power supply

Solution: put RF chokes (inductor) between each bias resistors (RC and RB), as such:

Problem: how do we determine the values of RF chokes?

Solution: alter the circuit as such and measure Iin vs Iout, Vin vs Vout

• increasing L value reduces current ripple, 270nH is the ideal case here
• having a bigger choke doesn’t mean less ripple

Measuring port parameters: Linear → port parameters → S

Transistor design: characterisation using 2-port parameters

S21 = forward voltage gain

S11 = reflection coefficient measured in port 1
S22 = reflection coefficient measured in port 2

S21 vs frequency:
• as we increase frequency, lower gain and lower phase shift between output and input
signal
• would create negative feedback, stabilizes transistor
S11 and S22 mismatched:
• design input and output matching networks to increase gain S21

Goal: match the impedance seen from input (S11) with its conjugate (S11*)

• S11 hugely decreased, input very well matched

• S21 increased slightly
• S22 now above 1, which means can go into instability/introduce oscillations
Transistor stability: stability, μ factor, resistive stabilisation

To have an unconditionally stable transistor, μ1 > 1 at all frequencies

Problem: Varying input matching network reactance (resistance=constant), we can see p10-p14
falls into the “potentially unstable area” of the SCIR1 circle
• We don’t want those combinations
Solution: tune the resistance such that none of those combination falls into the circle
• Note you can connect shunt/series resistor to stabilise
• Safe choice is a series R, because shunt R leads to short circuit, which can fall inside SCIR1
To stabilise the output resistance:
• put a marker on SCIR2 and find the largest possible r
• Put Rmax in series with output port

Transistor stability: stabilisation through emitter degeneration, low frequency stabilisation,

reactive stabilisation, performance analysis & improvements

• Easier tuning strategy: just connect resistor between input port and base until stability
circles are fully pushed away from smith chart
• Downside: putting resistor in series will increase noise
• Solution: shunt resistor at output and put DC-blocking capacitor in series
• Downside: gain decreases
Inductor in series with emitter:
• In this case, 0.8nH → unconditional stability at operating frequency (1900 MHz)
• Same voltage gain as putting shunt resistor at output

Use BOTH Le and Rout attaching CDCBLOCK in series:

• Transistor unconditionally stable for broadband operation, just requires tuning

Problem: gain is HUGELY compromised

Solution: Recover gain using quarter-wave transformer attached to capacitor

• Quarter wave flips
• This makes resistor inactive at operating frequencies → we know transistor is already
stable
• Makes resistor active at LOWER frequencies

Trade-Off between transistor unconditional stability (μ1)[S11 and S22 better matched] and gain (S22)
Transistor matching: unilateral match using distributed matching networks, constant VSWR and Γ
circles, limitations

Using unilateral match means we assume:

• the termination at input won’t affect the output
• no power is flowing back from the output to the input
• essentially, S12 = 0

1 1
𝐺𝐼𝑀𝐴𝑋 = 1−|𝑆 2 and 𝐺𝑂𝑀𝐴𝑋 = 1−|𝑆 2 and 𝑇𝑜𝑡𝑎𝑙 𝑔𝑎𝑖𝑛 = 𝐺𝑖𝑛 + 𝐺𝑜 + 𝐺𝑜𝑢𝑡
11 | 22 |

To carry out unilateral match, look at input first:

 • measure S11 of transistor and plot the conjugate (S11*) on smith chart
• create new schematic of input matching network, plot its S11 (not conjugate!)
• match the input network S11 to the transistor S11*
o add a constant VSWR circle by measuring VSWR on port 1 of transistor
o TLOC in shunt to move from midpoint → VSWR circle
o TLIN to move along VSWR circle

• Copy the transistor schematic and paste the input matching network
• Check S-parameters and see if it agrees with theory

To carry out output match:

• Duplicate the input match schematic (such that graphs will have the same measurements,
BUT referenced to the old schematic)
• Modify measurements according to the newly created schematic (S11* → S22*[transistor],
S11 [input] → S11[output])
• Repeat the steps with input
• Check S-parameters to see if agree with theory

What’s happening:
• Match input to decrease S11 and increase S21, but also increases S22
• Match output to decrease S22 and increase S21, but also increases S11
• Long iterative process to match S11 and S22, because S12 is not 0
• Simultaneous conjugate match can solve this
Transistor matching: simultaneous conjugate match (1), achieving max gain using GM1/GM2,
design of distributed network

We first assume:
• Transistor is unconditionally stable – check µ1 and µ2 >1
o Tune emitter inductor – rmb to account for real-life effects (e.g. fabrication
tolerance), better to set 10% more than minimum
• GM1 and GM2 already are impedances we want to match
o No need to use CONJUGATE
To match input:
• Create new schematic (input network) and match S11 of input network to GM1
• TLOC → TLIN (rmb to use constant VSWR circle)
o Calculate VSWR from marker’s reflection coefficient magnitude:
1+|Γ|
o 𝑉𝑆𝑊𝑅 = 1−|Γ|
To match output:
• Duplicate input network schematic as usual
• Change measurement: S11[input] →S11[output], GM1→GM2
• Repeat steps above

Result:
• Extra 1.6 dB of gain
• Much lower values of S11 and S22

Transistor matching: simultaneous conjugate match (2), broadband gain profile, matching with
TLOC (quarter-wave effect)/TLSC (resonance), limitations

Observation 1: Low pass behavior

• TLOC looks like a capacitor at EL<90◦
• Shunt capacitor is basically a low pass filter
Observation 2: Gain vs frequency dips – quarter wave transformer effect
• Electrical length of TLOC is proportional to frequency
• At EL = 90◦, flips OC to SC, all current sunk there

Solution to gain troughs:

• Use TLSC in shunt instead of TLOC in shunt
• When tuning, default to EL = 90◦ because flipping a SC to OC = no effect in network
• Tune until point reaches constant VSWR circle and then tune TLIN
• Finally, connect DC-blocking capacitor in series with stub
• Verify performance with S parameters
 With blocking capacitor without block capacitor

Observation 3: troughs in the new matching network @ low freq

• TLSC behaves like inductor when EL<90◦
• Matching network is basically a RL circuit, resonates at those frequencies

Solution: lower troughs cannot be removed

• If DC-blocking capacitors are taken away, DC current will flow to ground and mess up
transistor biasing points
• Gain plummets
Transistor design: stable design -> operating gain circles (GPC_max and GMAX), writing 2-port
parameter files (.s2p), effects and limitations
Previously, we can tune the overall gain by unilateral/simultaneous matching:
• Limitation of unilateral matching:
o Only applicable if S12 = 0
• Limitation of simultaneous matching:
o GM1 and GM2 only achieved if unconditional stability is achieved
o Can’t tune output/input network to achieve another overall gain Gtotal

.s2p files have this format:{

!example s2p file
!Unit of frequency,
!parameter type (S, Y, Z, G, H....),
!Format (MA, RI, DB),
!Normalising impedance (R Z)

# GHz S MA R 50

!Freq S11m S11a S21m S21a S12m S12a S22m S22a}

Advantage of power gain circles:

• Gain can be adjusted to a custom value, but Go > Gmax
• Done by creating mismatch in output and/or input matching networks
• Adjust input mismatch using available gain circles
• Adjust output mismatch using operable gain circles

First:
• check µ1 and µ2 >1

To match starting with the output:

• Use GM2 and plot GPC_max
o Gain step = amount of gain in dB between each equi-gain circle
o Number of circles = accounts for max gain circle when GPC_max = Gmax
• Create new schematic [output match] and measure S11 with 50 ohm load
• Pick a (arbitrary) point on GPC_max to match to
• Find its reflection coefficient (ΓL) and transform into constant-VSWR circle
• Match S11 into arbitrary point
o Shunt TLOC → series TLIN

• Make left port → PORT1, right port → PORT2

• Transform into sub-circuit and paste into transistor schematic
Afterward, to match the input:
• Match input network S11 into transistor S11* (CONJUGATE NEEDED)
• Repeat steps above, without gain circles
o Find reflection coefficient (ΓL) → constant-VSWR circle
o Shunt TLOC → series TLIN
o Make left port → PORT1, right port → PORT2

Result :

• Output VSWR(2) is mismatched to create desired gain (S21)

To match starting with the input:

• Identical to starting with output, with 2 exceptions
• Instead of using GM2, we use GM1(2,1) as reference
• Instead of using GPC_max, we use GAC_max

In the special case that GAC_max circle crosses the real axis:
• We don’t need TLOC/TLSC to give us a complex impedance
• We can straight up use TLIN by setting:
o EL = 90 [quarter wave transformer]
o 𝑍1 = √𝑅𝐿 𝑍𝑜 where Zo = 50 and RL = the point that intersects real axis

Afterward, to match the output:

• Match output network S11 into transistor S22* (CONJUGATE NEEDED)
• Repeat the steps as before:
o Find reflection coefficient (ΓL) → constant-VSWR circle
o Shunt TLOC → series TLIN
o Make left port → PORT1, right port → PORT2
Result:

• Mismatched input to achieve desired gain (relatively high S11)

• High VSWR(1) but low VSWR(2) signalling input is mismatched