VLSI DESIGN

VLSI DESIGN

Prepared by

I.Swathi Priya,M.Tech.,
K.Aishwarya.,M.E.,

Assistant Professor / Department of E.C.E

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VLSI DESIGN

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY,HYDERABAD

L T/P/D C
III YEAR B.TECH ECE II SEM 4 -/ -/- 4

(A60432 VLSI DESIGN)

UNIT I :
INTRODUCTION: Introduction to IC Technology – MOS, PMOS, NMOS, CMOS & BiCMOS
BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and BiCMOS Circuits: Ids-Vds
relationships, MOS transistor threshold voltage, gm, gds, figure of merit , Pass transistor, NMOS Inverter,
Various pull ups, CMOS Inverter analysis and design, Bi-CMOS Inverters.

UNIT II :
VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS layers, Stick Diagrams, Design Rules
and Layout, 2μm CMOS design rules for wires, Contacts and Transistors Layout Diagrams for NMOS and
CMOS Inverters and Gates, Scaling of MOS circuits.

UNIT III:
GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, time
delays, Driving large Capacitive Loads, Wiring Capacitances, Fan-in and fan-out, Choice of layers.

UNIT IV :
DATAPATH SUBSYSTEM : Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity generators,
Comparators, Zero/One Detectors, Counters.
ARRAY SUBSYSTEMS: SRAM, DRAM, ROM, Serial access memories.

UNIT V :
PROGRAMMABLE LOGIC DEVICES :
PLAs, FPGAs, CPLDs, Standard Cells, Programmable Array Logic, Design Approach, parameters influencing
low power design.
CMOS TESTING :
CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chip level Test Techniques.

TEXT BOOKS:
1. Essentials of VLSI circuits and systems – Kamran Eshraghian, EshraghianDougles and A. Pucknell, PHI,
2005 Edition.
2. VLSI DESIGN - K. Lal Kishore, V.S.V Prabhakar, I.K International, 2009.
3. CMOS VLSI Design- Neil H.E Weste, David Harris, AyanBanerjee, Pearson Education, 1999.

REFERENCES:

1. CMOS logic circuit design- John P. Uyemura, Springer, 2007.

2. Modern VLSI Design – Wayne Wolf, Pearson Education, 3rd Edition, 1997.
3. Introduction to VLSI-Mead and convey, BS publications, 2010
4. Application Specific Integrated Circuits-smith

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COURSE OBJECTIVES

The objectives of the course are to

 Give exposure to different steps involved in the fabrication of II s using MOS transistor,
CMOS/BICMOS transistors and passi components.

 Explain electrical properties of MOS and BiCMOS devices to analyse the behaviour of
inverts designed with various loads.

 Give exposure to the design rules to be followed to draw the layout of any logic circuit.

 Provide concept to design different types of logic gates using CMttS inverter and analyze
their transfer characteristics.

 Provide design concepts to design building blocks of data path of any system using gates.

 Understand basic programmable logic devices and testing of CM S circuits.

COURSE OUTCOMES

Upon successfully completing the course, the student should be able to:

 Acquire qualitative knowledge about the fabrication process of integrated circuit using MOS
transistors.
 Choose an appropriate inverter depending on specifications required for a circuit
 Draw the layout of any logic circuit which helps to understand and estimate parasitics of any
logic circuit
 Design different types of logic gates using CMOS inverter and analyse their transfer
characteristics
 Provide design concepts required to design building blocks of date, path using gates.
 Design simple memories using MOS transistors and can understand Design of large memories.
 Design simple logic circuit using PLA, PAL, FPGA and CPLD.
 Understand different types of faults that can occur in a system and learn the concept of testing
and adding extra hardware to improve testability of system

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TABLE OF CONTENTS

S.NO. TOPIC NAME PAGE

NO.
UNIT I INTRODUCTION & BASIC ELECTRICAL PROPERTIES 7-42
1.1 Introduction 8
1.1.1Metal-oxide-semiconductor (MOS) and related VLSI technology 8
1.1.2 Basic MOS Transistors 9
1.1.3 Enhancement Mode Transistors 10
1.1.4 Enhancement mode transistor action 11
1.1.5 Depletion mode transistor action 13
1.1.6 nMOS fabrication 14
1.1.7 CMOS fabrication 17
1.1.8 BiCMOS technology 20
1.2 Basic electrical properties 22
1.2.1 Ids vs Vds Characteristics of MOS transistors 22
1.2.2 Ids vs Vds Relationship 23
1.2.3 MOS threshold voltage Vt 27
1.2.4 Body Effect 27
1.2.5 nMOS inverter 28
1.2.5.1 nMOS inverter transfer characteristics 29
1.2.6 CMOS inverter 29
1.2.7 Determination of Pull-up to Pull –Down Ratio (Zp.u}Zp.d.)for an 33
nMOS Inverter driven by another nMOS Inverter
1.2.8 Pull -Up to Pull-Down ratio for an nMOS Inverter driven through 35
one or more Pass Transistors
1.2.9 Alternative forms of pull up 38
1.2.10 BiCMOS inverter 40
1.2.11 Comparison of BiCMOS and C-MOS technologies 42
UNIT II VLSI CIRCUIT DESIGN PROCESSES 43-66
2.1 Introduction 44
2.2 VLSI Design Flow 44
2.3 MOS layers 48
2.4 Stick Diagrams 48
2.4.1 nMOS design style 51
2.4.2 CMOS design style 53
2.5 Design Rules and Layout 55
2.5.1 Lambda based design rules 55
2.5.2 Contact cuts 57
2.5.3 Double metal MOS transistor 58
2.5.4 CMOS lambda based design rules 59
2.5.5 2μm CMOS design rules for wires, Contacts and Transistors 61
2.6 Layout Diagrams for NMOS and CMOS Inverters and Gates 64
2.7 Scaling of MOS circuits 65

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UNIT III GATE LEVEL DESIGN 67-103

3.1 Introduction 68
3.2 CMOS Logic Gates and Other complex gates 69
3.2.1 CMOS static logic 69
3.2.2 CMOS inverter 70
3.2.3 CMOS NAND gate 71
3.2.4 CMOS NOR gate 73
3.3 Complex gates in CMOS logic 74
3.4 Switch logic 78
3.4.1 Pass transistors 78
3.4.2 Transmission gate 79
3.5 Alternative gate circuits 81
3.5.1 Pseudo nMOS logic 81
3.5.2 CMOS Domino logic 83
3.5.3 Clocked CMOS logic 85
3.5.5 np CMOS logic 87
3.6 Time delays 89
3.7 Driving large Capacitive Loads 93
3.8 Wiring Capacitances 93
3.9 Fan-in and fan-out 101
3.10 Choice of layers 103
UNIT IV DATA PATH SYSTEMS & ARRAY SUBSYTEM 106-144
4.1 Data Path systems 106
4.1.1 Subsytem design 106
4.1.2 Shifters 106
4.1.3 Adders 107
4.1.3.1 Single bit adder 108
4.1.3.2 n-bit parallel adder or Ripple carry adder 110
4.1.3.3 Carry look ahead adder 111
4.1.3.4 Manchester Carry chain 114
4.1.4 Multipliers 115
4.1.4.1 Array multiplication 116
4.1.4.2 Wallace tree multiplication 118
4.1.5 Parity generator 121
4.1.6 Zero/ one detector 123
4.1.7 Comparator 124
4.1.8 Counters 126
4.1.8.1 Asynchronous Up counter with T flipflops 126
4.1.8.2 Asynchronous down counter with T flipflops 127
4.1.8.3 Synchronous counter 128
4.1.8.4 Synchronous up counter with T flipflops 128
4.2 Array subsystem 131
4.2.1 Memory classification 132
4.2.2 Memory architecture & building block 134
4.2.3 Static & dynamic ROM 136
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4.2.3.1 SRAM basics 137

4.2.3.2 DRAM basics 143
4.2.4 ROM 144

UNIT V PROGRAMMABLE LOGIC DEVICES & CMOS TESTING 147-169

5.1 Programable logic devices 147
5.1.1 Introduction 147
5.1.2 Programmable Logic device (PLD) 147
5.1.3 PLA 150
5.1.4 PAL 152
5.1.5 CPLD 155
5.1.6 FPGA 157
5.1.8 Standard cell 159
5.1.9 Design Approach 163
5.2 CMOS testing 167
5.2.1 Need for testing 167
5.2.2 Test principles 168
5.2.3 Design strategies for test 168
5.2.4 Chip level test techniques 169
Appendix
I Tutorial sheets
II Model questions(Descriptive & objective questions)
III Previous University examination question paper
IV References

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UNIT I INTRODUCTION & BASIC

ELECTRICALPROPERTIES

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1.1 INTRODUCTION

The invention of the transistor by William B. Shockley, Walter H. Brattain and John
Bardeen of Bell Telephone Laboratories drastically changed the electronics industry and paved
the way for the development of the Integrated Circuit (IC) technology. The first IC was designed
by Jack Kilby at Texas Instruments at the beginning of 1960 and since that time there have
already been four generations of ICs .Viz SSI (small scale integration), MSI (medium scale
integration), LSI (large scale integration), and VLSI (very large scale integration). Now we are
ready to see the emergence of the fifth generation, ULSI (ultra large scale integration) which is
characterized by complexities in excess of 3 million devices on a single IC chip. Further
miniaturization is still to come and more revolutionary advances in the application of this
technology must inevitably occur.

Over the past several years, Silicon CMOS technology has become the dominant
fabrication process for relatively high performance and cost effective VLSI circuits. The
revolutionary nature of this development is understood by the rapid growth in which the number
of transistors integrated in circuits on a single chip.

1.1.1 METAL-OXIDE-SEMICONDUCTOR (MOS) AND RELATED VLSI TECHNOLOGY

The MOS technology is considered as one of the very important and promising
technologies in the VLSI design process. The circuit designs are realized based on pMOS,
nMOS, CMOS and BiCMOS devices.The pMOS devices are based on the p-channel MOS
transistors. Specifically, the pMOS channel is part of a n-type substrate lying between two
heavily doped p+ wells beneath the source and drain electrodes. Generally speaking, a pMOS
transistor is only constructed in consort with an NMOS transistor.The nMOS technology and
design processes provide an excellent background for other technologies. In particular, some
familiarity with nMOS allows a relatively easy transition to CMOS technology and design.

The techniques employed in nMOS technology for logic design are similar to GaAs
technology. Therefore, understanding the basics of nMOS design will help in the layout of GaAs
circuit. With the rapid advances in technology the the size of the ICs is shrinking and the
integration density is increasing.

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The minimum line width of commercial products over the years is shown in the below
Figure 1.1 Moore’s law
.

Figure 1.1 Moore’s law

The graph shows a significant decrease in the size of the chip in recent years which implicitly
indicates the advancements in the VLSI technology.

1.1.2 BASIC MOS TRANSISTORS

The MOS Transistor means, Metal-Oxide-Semiconductor Field Effect Transistor which is
the most basic element in the design of a large scale integrated circuits(IC).
These transistors are formed as a ``sandwich'' consisting of a semiconductor layer, usually a
slice, or wafer, from a single crystal of silicon; a layer of silicon dioxide (the oxide) and a layer
of metal. These layers are patterned in a manner which permits transistors to be formed in the
semiconductor material (the``substrate'') a diagram showing a MOSFET is shown below in Figure 1.2

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Figure 1.2 MOSFET

Silicon dioxide is a very good insulator, so a very thin layer, typically only a few hundred
molecules thick, is used.In fact, the transistors which are used do not use metal for their gate
regions, but instead use polycrystalline silicon (poly). Polysilicon gate FET's have replaced
virtually all of the older devices using metal gates in large scale integrated circuits. (Both metal
and polysilicon FET's are sometimes referred to as IGFET's (insulated gate field effect
transistors), since the silicon dioxide under the gate is an insulator.
MOS Transistors are classified as n-MOS ,p-MOS and c-MOS Transistors based on the
fabrication . nMOS devices are formed in a p-type substrate of moderate doping level. The
source and drain regions are formed by diffusing n- type impurities through suitable masks into
these areas to give the desired n-impurity concentration and give rise to depletion regions which
extend mainly in the more lightly doped p-region . Thus, source and drain are isolated from one
another by two diodes. Connections to the source and drain are made by a deposited metal layer.
In order to make a useful device, there must be the capability for establishing and controlling a
current between source and drain, and .this is commonly achieved in one of two ways, giving
rise to the enhancement mode and depletion mode transistors.

1.1.3 Enhancement Mode Transistors

In an enhancement mode device a polysilicon gate is deposited on a layer of insulation
over the region between source and drain. Shown below in Figure 1.3, channel is not established

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and the device is in a non-conducting condition , i.e VD = Vs = Vgs = 0.

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If this gate is connected to a suitable positive voltage with respect to the source, then the electric
field established between the gate and the substrate gives rise to a charge inversion region in the
substrate under the gate insulation and a conducting path or channel is formed between source and
drain.

Figure 1.3 nMOS Enhancement mode transistor

1.1.4 ENHANCEMENT MODE TRANSISTOR ACTION

To understand the enhancement mechanism, let us consider the enhancement mode device.
In order to establish the channel, a minimum voltage level called threshold voltage (Vt) must be
established between gate and source. Fig. 1.4 (a) Shows the existing situation where a channel is
established but no current flowing between source and drain (Vds = 0 ).

Let us now consider the conditions when current flows in the channel by applying a voltage Vds
between drain and source. The IR drop = Vds along the channel. This develops a voltage
between gate and channel varying with distance along the channel with the voltage being a
maximum of Vgs at the source end. Since the effective gate voltage is Vg= Vgs - Vt, (no current
flows when Vgs < Vt) there will be voltage available to invert the channel at the drain end so
long as Vgs - Vt ~ Vds· The limiting condition comes when Vds= Vgs - Vt. For all voltages Vds
< Vgs - Vt, the device is in the non-saturated region of operation which is the condition shown in
Fig. 1.4 (b) below.
VLSI DESIGN

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Figure 1.4 Enhancement mode transistor for particular values of Vds with (Vgs > Vt)

Let us now consider the situation when Vds is increased to a level greater than Vgs - Vt. In this
case, an IR drop equal to Vgs – Vt occurs over less than the whole length of the channel such that,
near the drain, there is insufficient electric field available to give rise to an inversion layer to
create the channel. The .channel is, therefore, 'pinched off as shown in Fig.1.4 (c). Diffusion
current completes the path from source to drain in this case, causing the channel to exhibit a high
resistance and behave as a constant current source. This region, known as saturation, is
characterized by almost constant current for increase of Vds above Vds = Vgs - Vt. In all cases,
the channel will cease to exist and no current will flow when Vgs < Vt. Typically, for

enhancement mode devices, Vt = 1 volt for VDD = 5 V or, in general terms, Vt = 0.2 VDD.

1.1.5 DEPLETION MODE TSANSISTOR ACTION

n-MOS Depletion mode MOSFETs are built with P-type silicon substrates, and P-channel
versions are built on N-type substrates. In both cases they include a thin gate oxide formed
between the source and drain regions. A conductive channel is deliberately formed below the gate
oxide layer and between the source and drain by using ion-implantation. By implanting the correct
ion polarity in the channel region during fabrication determines the polarity of the threshold
voltage (i.e. -Vt for an N channel transistor, or +Vt for an P-channel transistor). The actual
concentration of ions in the substrate-to-channel region is used to adjust the threshold voltage (Vt)
to the desired value. Depletion-mode devices are a little more difficult to manufacture and their
characteristics harder to control than enhancement types, which do not require ion implantation.
In depletion mode devices the channel is established, due to the implant, even when Vgs = 0, and
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to cause the channel to cease a negative voltage Vtd must be applied between gate and source.

Figure 1.5 nMOS depletion mode transistor

Vtd is typically < - 0.8 VDD, depending on the implant and substrate bias, but, threshold voltage
differences apart, the action is similar to that of the enhancement mode transistor .

1.1.6 nMOS FABRICATION

There are a large number and variety of basic fabrication steps used in the production of modern
MOS ICs. The same process can be used for the designed of NMOS or PMOS or
CMOS devices.The gate material could be either metal or poly-silicon . The most commonly used
substrate is bulk silicon or silicon-on-sapphire (SOS). Inorder to avoid the presence of parasitic
transistors, variations are brought in the techniques that are used to isolate the devices in the wafer.

The fabrication steps and respective diagrams (In Fig 1.6 below) are as follows:

Step1: Processing is carried on single crystal silicon of high purity on which required P impurities
are introduced as crystal is grown. Such wafers are about 75 to 150 mm in diameter and 0.4 mm thick
and they are doped with say boron to impurity concentration of 10 to power 15/cm3 to 10 to the
power 16 /cm3.

Step 2 : A layer of silicon di oxide (SiO2) typically 1 micrometer thick is grown all over the surface
of the wafer to protect the surface, acts as a barrier to the dopant during processing, and provide a
generally insulating substrate on to which other layers may be deposited and patterned.

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Step 3: The surface is now covered with the photo resist which is deposited onto the wafer and spun
to an even distribution of the required thickness.

Step 4: The photo resist layer is then exposed to ultraviolet light through masking which defines
those regions into which diffusion is to take place together with transistor channels. Assume, for
example , that those areas exposed to uv radiations are polymerized (hardened), but that the areas
required for diffusion are shielded by the mask and remain unaffected.

Step 5: These areas are subsequently readily etched away together with the underlying silicon di
oxide so that the wafer surface is exposed in the window defined by the mask.

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Step 6: The remaining photo resist is removed and a thin layer of SiO2 (0.1 micro m typical) is
grown over the entire chip surface and then poly silicon is deposited on the top of this to form the
gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical
vapour deposition (CVD). In the fabrication of fine pattern devices, precise control of thickness,
impurity concentration, and resistivity is necessary

Step 7: Further photo resist coating and masking allows the poly silicon to be patterned and then the
thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the
source and drain. Diffusion is achieved by heating the wafer to a high temperature and passing a gas
containing the desired n-type impurity.
Note: The poly silicon with underlying thin oxide and the thick oxide acts as mask during diffusion
the process is self aligning.

Step 8: Thick oxide (SiO2) is grown over all again and is then masked with photo resist and etched
to expose selected areas of the poly silicon gate and the drain and source areas where connections are
to be made. (contacts cut)

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Step 9: The whole chip then has metal (aluminium) deposited over its surface to a thickness typically
of 1 micro m. This metal layer is then masked and etched to form the required interconnection
pattern.

1.1.7 CMOS FABRICATION

CMOS fabrication is performed based on various methods , including the p-well, the n-
well, the twin-tub, and the silicon-on-insulator processes .Among these methods the p-well
process is widely used in practice and the n-well process is also popular, particularly as it is an
easy retrofit to existing nMOS lines.
(i) The p-well Process
The p-well structure consists of an n-type substrate in which p-devices may be formed by
suitable masking and diffusion and, in order to accommodate n-type devices, a deep p-well is
diffused into the n-type substrate as shown in the Fig.1.7 below.

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Figure 1.7 - 1 p-well Process

This diffusion should be carried out with special care since the p-well doping concentration and
depth will affect the threshold voltages as well as the breakdown voltages of the n-transistors. To
achieve low threshold voltages (0.6 to 1.0 V) either deep-well diffusion or high-well resistivityis
required. However, deep wells require larger spacing between the n- and p-type transistors and
wires due to lateral diffusion and therefore a larger chip area. The p-wells.act as substrates for the
n- devices within the parent n-substrate, and, the two areas are electrically isolated. Except this in
all other respects- like masking, patterning, and diffusion-the process is similar to nMOS
fabrication.

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Figure 1.7 – 2,3 & 4 p-well Process

The Figure 1.7-5 below shows the CMOS p-well inverter showing VDD and Vss
substrate connections
Figure 1.7-5 CMOS p-well inverter

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(ii)The n-well Process : Though the p-well process is widely used in C-MOS fabrication the n-
well fabrication is also very popular because of the lower substrate bias effects on transistor
threshold voltage and also lower parasitic capacitances associated with source and drain regions.
The typical n-well fabrication steps are shown in the Figure 1.8 below.

Fig.n-well fabrication steps

Figure 1.8 CMOS n-well process

The first mask defines the n-well regions. This is followed by a low dose phosphorus implant
driven in by a high temperature diffusion step to form the n-wells. The well depth is optimized to
ensure against-substrate top+ diffusion breakdown without compromising then-wellton+ mask
separation. The next steps are to define the devices and diffusion paths, grow field oxide, deposit
and pattern the polysilicon, carry out the diffusions, make contact cuts, and finally metalize as before. lt will
be seen that an n+ mask and its complement may be used to define the n- and p-diffusion regions
respectively. These same masks also include the V DD and Vss contacts (respectively). It should
be noted that, alternatively, we could have used a p+ mask and its complement since the n + and

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p + masks are generally complementary.

The Figure 1.9 below shows the Cross-sectional view of n-well CMOS Inverter.

Figure 1.9 Cross-sectional view of n-well CMOS Inverter

Due to the differences in charge carrier mobilities, the n-well process creates non-optimum p-
channel characteristics. However, in many CMOS designs (such as domino-logic and dynamic
logic structures), this is relatively unimportant since they contain a preponderance of n-channel
devices. Thus then-channel transistors are mainly those used to form1ogic elements, providing
speed and high density of elements.
However, a factor of the n-well process is that the performance of the already poorly performing
p-transistor is even further degraded. Modern process lines have come to grips with these
problems, and good device performance may be achieved for both p-well and n-well fabrication.

1.1.8 BICMOS Technology

A BiCMOS circuit consist of both bipolar junction transistors and MOS transistors on a
single substrate. The driving capability of MOS transistors is less because of limited current
sourcing and sinking capabilities of the transistors. To drive large capacitive loads Bi-CMOS
technology is used. As this technology combines Bipolar and CMOS transistors in a single
integrated circuit, it has the advantages of both bipolar and CMOS transistors. BiCMOS is able to
achieve VLSI circuits with speed-power-density performance previously not possible with either
technology individually.The diagram given below shows the cross section of the BiCMOS
process which uses an npn transistor

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Figure 1.10 Twin tube structure

The lay-out view of Bic-MOS transistor is shown in the figure below. The fabrication of BiCMOS
is similar to CMOS but with certain additional process steps and additional masks are
considered. They are (i) the p+ base region; (ii) n+ collector area; and (iii) the buried sub collector
(BCCD).

Figure 1.11 Cross section of BiCMOS process

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1.2 Basic electrical properties

1.2.1 ID-VDS Characteristics of MOS Transistor:
The graph below in Fig 1.2 shows the I D Vs VDS characteristics of an n- MOS transistor for
several values of VGS .It is clear that there are two conduction states when the device is ON. The
saturated state and the non-saturated state. The saturated curve is the flat portion and defines the
saturation region. For Vgs < VDS + Vth, the nMOS device is conducting and I D is independent
of VDS. For Vgs > VDS + Vth, the transistor is in the non-saturation region and the curve is a half
parabola. When the transistor is OFF (Vgs < Vth), then ID is zero for any VDS value.

Figure 1.12 (a) Depletion mode Transistor

The boundary of the saturation/non-saturation bias states is a point seen for each curve in the
graph as the intersection of the straight line of the saturated region with the quadratic curve of the
non-saturated region. This intersection point occurs at the channel pinch off voltage called V DSAT.
The diamond symbol marks the pinch-off voltage V DSAT for each value of VGS. VDSAT is defined as
the minimum drain-source voltage that is required to keep the transistor in saturation for a given
VGS .In the non-saturated state, the drain current initially increases almost linearly from the origin
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before bending in a parabolic response. Thus the name ohmic or linear for the non- saturated
region.
The drain current in saturation is virtually independent of V DS and the transistor acts as a current
source. This is because there is no carrier inversion at the drain region of the channel. Carriers are
pulled into the high electric field of the drain/substrate pn junction and ejected out of the drain
terminal.

Figure 1.12 (b) Enhancement mode Transistor

1.2.2 Drain-to-Source Current IDS Versus Voltage VDS Relationships :

The working of a MOS transistor is based on the principle that the use of a voltage on the
gate induce a charge in the channel between source and drain, which may then be caused to
move from source to drain under the influence of an electric field created by voltage Vds applied
between drain and source. Since the charge induced is dependent on the gate to source voltage
Vgs then Ids is dependent on both Vgs and Vds.
Let us consider the diagram below in which electrons will flow source to drain .So,the drain
current is given by

Charge induced in channel (Qc)

Ids =-Isd =

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Electron transit time(τ)

Length of the channel

Where the transit time is given by τsd = ------------------------------
Velocity (v)

But velocity v= µEds

Figure 1.13 MOS transistor

Where µ = electron or hole mobility and Eds = Electric field also,

Eds = Vds/L so,v = µ.Vds/L and τds = L2 / µ.Vds

The typical values of µ at room temperature are given below.

The Non-saturated Region :

Let us consider the Id vs Vd relationships in the non-saturated region .The charge
induced in the channel due to due to the voltage difference between the gate and the channel,
Vgs (assuming substrate connected to source). The voltage along the channel varies linearly with
distance X from the source due to the IR drop in the channel .In the non-saturated state the
average value is Vds/2. Also the effective gate voltage Vg = Vgs – Vt where Vt, is the threshold
voltage needed to invert the charge under the gate and establish the channel.
Hence the induced charge is Qc = Eg εins εoW. L

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where

Eg = average electric field gate to channel

εins = relative permittivity of insulation between gate and channel
εo = permittivity of free space.
So, we can write
that

Here D is the thickness of the oxide layer. Thus

So, by combining the above two equations ,we get

or the above equation can be written as

In the non-saturated or resistive region where Vds < Vgs – Vt and

Generally ,a constant β is defined as

So that ,the expression for drain –source current will become

The gate /channel capacitance is

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Hence we can write another alternative form forthe drain current as

Some time it is also convenient to use gate –capacitance per unit area ,Cg
So,the drain current is

This is the relation between drain current and drain-source voltage in non-saturated region.

The Saturated Region

Saturation begins when Vds = Vgs - V, since at this point the IR drop in the channel
equals the effective gate to channel voltage at the drain and we may assume that the current
remains fairly constant as Vds increases further. Thus

or we can also write that

or it can also be written as

or

The expressions derived above for Ids hold for both enhancement and depletion mode devices.

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Here the threshold voltage for the nMOS depletion mode device (denoted as Vtd) is negative.

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1.2.3 MOS Transistor Threshold Voltage Vt

The gate structure of a MOS transistor consists, of charges stored in the dielectric layers
and in the surface to surface interfaces as well as in the substrate itself. Switching an
enhancement mode MOS transistor from the off to the on state consists in applying sufficient
gate voltage to neutralize these charges and enable the underlying silicon to undergo an inversion
due to the electric field from the gate. Switching a depletion mode nMOS transistor from the on
to the off state consists in applying enough voltage to the gate to add to the stored charge and
invert the 'n' implant region to 'p'.
The threshold voltage Vt may be expressed as:

where QD = the charge per unit area in the depletion layer below the
oxide Qss = charge density at Si: SiO2 interface
Co =Capacitance per unit area.
Φns = work function difference between gate and Si
ΦfN = Fermi level potential between inverted surface and bulk Si
For polynomial gate and silicon substrate, the value of Φns is negative but negligible and the
magnitude and sign of Vt are thus determined by balancing the other terms in the equation.
To evaluate the Vt the other terms are determined as below.

1.2.4 Body Effect

Generally while studying the MOS transistors it is treated as a three terminal device. But ,the
body of the transistor is also an implicit terminal which helps to understand the characteristics of
the transistor. Considering the body of the MOS transistor as a terminal is known as the body

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effect. The potential difference between the source and the body (Vsb) affects the threshold

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voltage of the transistor. In many situations, this Body Effect is relatively insignificant, so we
can (unless otherwise stated) ignore the Body Effect. But it is not always insignificant, in some
cases it can have a tremendous impact on MOSFET circuit performance.

Figure 1.14 Body effect - nMOS device

Increasing Vsb causes the channel to be depleted of charge carriers and thus the threshold
voltage is raised. Change in Vt is given by ΔVt = γ.(Vsb) 1/2 where γ is a constant which depends
on substrate doping so that the more lightly doped the substrate, the smaller will be the body
effect
The threshold voltage can be written as

Where Vt(0) is the threshold voltage for Vsd = 0

For n-MOS depletion mode transistors ,the body voltage values at different V DD voltages are
given below.
VSB = 0 V ; Vsd = -0.7VDD (= - 3.5 V for VDD =+5V ) VSB
= 5 V ; Vsd = -0.6VDD (= - 3.0 V for VDD =+5V )

1.2.5 The nMOS INVERTER

An inverter circuit is a very important circuit for producing a complete range of logic
circuits. This is needed for restoring logic levels, for Nand and Nor gates, and for sequential and
memory circuits of various forms .

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A simple inverter circuit can be constructed using a transistor with source connected to ground
and a load resistor of connected from the drain to the positive supply rail V DD· The output is
taken from the drain and the input applied between gate and ground .

But, during the fabrication resistors are not conveniently produced on the silicon substrate and
even small values of resistors occupy excessively large areas .Hence some other form of load
resistance is used. A more convenient way to solve this problem is to use a depletion mode
transistor as the load, as shown in Fig. below.

Figure 1.15 nMOS Inverter

The salient features of the n-MOS inverter are

For the depletion mode transistor, the gate is connected to the source so it is always on .

In this configuration the depletion mode device is called the pull-up (P.U) and the
enhancement mode device the pull-down (P.D) transistor.

With no current drawn from the output, the currents Ids for both transistors must be
equal.
1.2.5.1 nMOS Inverter transfer characteristic.
The transfer characteristic is drawn by taking Vds on x-axis and Ids on Y-axis for both

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enhancement and depletion mode transistors. So,to obtain the inverter transfer characteristic for

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Vgs = 0 depletion mode characteristic curve is superimposed on the family of curves for the
enhancement mode device and from the graph it can be seen that , maximum voltage across the
enhancement mode device corresponds to minimum voltage across the depletion mode transistor.

Figure 1.16 nMOS Inverter transfer characteristic.

From the graph it is clear that as Vin(=Vgs p.d. transistor) exceeds the Pulldown threshold
voltage current begins to flow. The output voltage Vout thus decreases and the subsequent
increases in Vin will cause the Pull down transistor to come out of saturation and become
resistive.
1.2.6 CMOS Inverter
The inverter is the very important part of all digital designs. Once its operation and
properties are clearly understood, Complex structures like NAND gates, adders, multipliers, and
microprocessors can also be easily done. The electrical behavior of these complex circuits can be
almost completely derived by extrapolating the results obtained for inverters. As shown in the
Figure 1.17 below the CMOS transistor is designed using p-MOS and n-MOS transistors.

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Figure 1.17 CMOS Inverter

In the inverter circuit ,if the input is high .the lower n-MOS device closes to discharge the
capacitive load .Similarly ,if the input is low,the top p-MOS device is turned on to charge the
capacitive load .At no time both the devices are on ,which prevents the DC current flowing from
positive power supply to ground. Qualitatively this circuit acts like the switching circuit, since
the p-channel transistor has exactly the opposite characteristics of the n-channel transistor. In the
transition region both transistors are saturated and the circuit operates with a large voltage gain.

The C-MOS transfer characteristic is shown in the below Figure 1.18. Considering the static
conditions first, it may be Seen that in region 1 for which Vi,. = logic 0, we have the p-transistor
fully turned on while the n-transistor is fully turned off. Thus no current flows through the
inverter and the output is directly connected to VDD through the p-transistor.

Figure 1.18 C-MOS transfer characteristic

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Hence the output voltage is logic 1 . In region 5 , V in = logic 1 and the n-transistor is fully on
while the p-transistor is fully off. So, no current flows and a logic 0 appears at the output.
In region 2 the input voltage has increased to a level which just exceeds the threshold voltage of
the n-transistor. The n-transistor conducts and has a large voltage between source and drain; so it
is in saturation. The p-transistor is also conducting but with only a small voltage across it, it
operates in the unsaturated resistive region. A small current now flows through the inverter from
VDD to VSS. If we wish to analyze the behavior in this region, we equate the p-device resistive
region current with the n-device saturation current and thus obtain the voltage and current
relationships.

Region 4 is similar to region 2 but with the roles of the p- and n-transistors reversed.However,
the current magnitudes in regions 2 and 4 are small and most of the energy consumed in
switching from one state to the other is due to the larger current which flows in region 3.
Region 3 is the region in which the inverter exhibits gain and in which both transistors are in
saturation.

The currents in each device must be the same ,since the transistors are in series. So,we can write
that

Since both transistors are in saturation, they act as current sources so that the equivalent circuit in
this region is two current sources in series between V DD and Vss with the output voltage coming
from their common point. The region is inherently unstable in consequence and the changeover
from one logic level to the other is rapid.

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1.2.7 Determination of Pull-up to Pull –Down Ratio (Zp.u}Zp.d.)for an nMOS

Inverter driven by another nMOS Inverter
Let us consider the arrangement shown in Figure 1.19.in which an inverter is driven from
the output of another similar inverter. Consider the depletion mode transistor for which Vgs = 0
under all conditions, and also assume that in order to cascade inverters without degradation the
condition

Figure 1.19.Inverter driven by another inverter.

For equal margins around the inverter threshold, we set Vinv = 0.5V DD · At this point both
transistors are in saturation and we can write that

where Wp.d , Lp.d , Wp.u. and Lp.u are the widths and lengths of the pull-down and pull-up

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transistors respectively.
So,we can write that

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The typical, values for Vt ,Vinv and Vtd are

Substituting these values in the above equation ,we get

here

So,we get

This is the ratio for pull-up to pull down ratio for an inverter directly driven by another inverter.

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1.2.8 Pull -Up to Pull-Down ratio for an nMOS Inverter driven through one
or more Pass Transistors
Let us consider an arrangement in which the input to inverter 2 comes from the output of
inverter 1 but passes through one or more nMOS transistors as shown in Figure 1.20 below
(These transistors are called pass transistors).

Figure 1.20. nMOS Inverter driven by Pass Transistors

The connection of pass transistors in series will degrade the logic 1 level / into inverter 2 so that
the output will not be a proper logic 0 level. The critical condition is , when point A is at 0 volts
and B is thus at VDD. but the voltage into inverter 2at point C is now reduced from V DD by the
threshold voltage of the series pass transistor. With all pass transistor gates connected to V DD
there is a loss of Vtp, however many are connected in series, since no static current flows
through them and there can be no voltage drop in the channels. Therefore, the input voltage to
inverter 2 is
Vin2 = VDD- Vtp
where Vtp = threshold voltage for a pass transistor.

Let us consider the inverter 1 shown in Fig.(a) with input = V DD· If the input is at VDD , then the
pull-down transistor T2 is conducting but with a low voltage across it; therefore, it is in its
resistive region represented by R1 in Fig.(a) below. Meanwhile, the pull up transistor T1 is in
saturation and is represented as a current source.
For the pull down transistor

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Since Vds is small, Vds/2 can be neglected in the above expression.

So,

Now, for depletion mode pull-up transistor in saturation with Vgs = 0

The product I1R1 = Vout1

So,

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Let us now consider the inverter 2 Fig.b .when input = VDD- Vtp.

Whence,

If inverter 2 is to have the same output voltage under these conditions then Vout1 = Vout2. That is

I1R1=I2R2 , therefore

Considering the typical values

Therefore

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From the above theory it is clear that, for an n-MOS transistor

(i). An inverter driven directly from the output of another should have a Zp.u/ Zpd. ratio
of ≥ 4/1.
(ii).An inverter driven through one or more pass transistors should have a Zp.u./Zp.d ratio of ≥8/1

1.2.9 ALTERNATIVE FORMS OF PULL –UP

Generally the inverter circuit will have a depletion mode pull-up transistor as its load. But
there are also other configurations .Let us consider four such arrangements.
1.Load resistance RL : This arrangement consists of a load resistor as apull-up as shown in the
Figure 1.21 below.But it is not widely used because of the large space requirements of resistors
produced in a silicon substrate.

Figure 1.21
2. nMOS depletion mode transistor pull-up : This arrangement consists of a depletion mode
transistor as pull-up. The arrangement and the transfer characteristic are shown below in Figure
1.22. In this type of arrangement we observe
(a) Dissipation is high , since rail to rail current flows when Vin = logical 1.
(b) Switching of output from 1 to 0 begins when Vin exceeds Vt, of pull-down device.

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Figure 1.22 nMOS depletion mode transistor pull-up

and transfer characteristic
(c) When switching the output from 1 to 0, the pull-up device is non-saturated initially and this
presents lower resistance through which to charge capacitive loads .
3. nMOS enhancement mode pull-up :This arrangement consists of a n-MOS
enhancement mode transistor as pull-up. The arrangement and the transfer characteristic are
shown below in Figure 1.23.

Figure 1.23 nMOS enhancement mode pull-up and transfer

characteristic
The important features of this arrangement are

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(a) Dissipation is high since current flows when Vin =logical 1 (VGG is returned to VDD) .

(b) Vout can never reach VDD (logical I) if VGG = VDD as is normally the case.
(c) VGG may be derived from a switching source, for example, one phase of a clock, so that

dissipation can be greatly reduced.

(d) If VGG is higher than VDD then an extra supply rail is required.
4. Complementary transistor pull-up (CMOS) : This arrangement consists of a C-MOS
arrangement as pull-up. The arrangement and the transfer characteristic are shown below in
Figure 1.24

Figure 1.24

The salient features of this arrangement are

(a) No current flows either for logical 0 or for logical 1 inputs.
(b) Full logical 1 and 0 levels are presented at the output.
(c) For devices of similar dimensions the p-channel is slower than the n-channel device.

1.2.10 THE BiCMOS INVERTER

A BiCMOS inverter, consists of a PMOS and NMOS transistor ( M2 and M1), two NPN

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bipolar junction transistors,( Q2 and Q1), and two impedances which act as loads( Z2 and Z1) as
shown in the circuit below in Figure 1.25.

Figure 1.25 BiCMOS Inverter

When input, Vin, is high (VDD), the NMOS transistor ( M1), turns on, causing Q1 to
conduct,while M2 and Q2 are off, as shown in Figure 1.26 . Hence , a low (GND) voltage is
translated to the output Vout. On the other hand, when the input is low, the M2 and Q2 turns on,
while M1and Q1 turns off, resulting to a high output level at the output as shown in Figure 1.26.
In steady-state operation, Q1 and Q2 never turns on or off simultaneously, resulting to a lower
power consumption. This leads to a push-pull bipolar output stage. Transistors M1and M2, on
the other hand, works as a phase-splitter, which results to a higher input impedance.

Figure 1.26

The impedances Z2 and Z1 are used to bias the base-emitter junction of the bipolar transistor and

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to ensure that base charge is removed when the transistors turn off. For example when the input
voltage makes a high-to-low transition, M1 turns off first. To turn off Q1, the base charge must
be removed, which can be achieved by Z1.With this effect, transition time reduces.
However,there exists a short time when both Q1 and Q2 are on, making a direct path from the
supply (VDD) to the ground. This results to a current spike that is large and has a detrimental
effect on both the noise and power consumption, which makes the turning off of the bipolar
transistor fast .

1.2.11 Comparison of BiCMOS and C-MOS technologies

The BiCMOS gates perform in the same manner as the CMOS inverter in terms of power
consumption, because both gates display almost no static power consumption.
When comparing BiCMOS and CMOS in driving small capacitive loads, their performance are
comparable, however, making BiCMOS consume more power than CMOS. On the other hand,
driving larger capacitive loads makes BiCMOS in the advantage of consuming less power than
CMOS, because the construction of CMOS inverter chains are needed to drive large capacitance
loads, which is not needed in BiCMOS.
The BiCMOS inverter exhibits a substantial speed advantage over CMOS inverters, especially
when driving large capacitive loads. This is due to the bipolar transistor’s capability of
effectively multiplying its current.
For very low capacitive loads, the CMOS gate is faster than its BiCMOS counterpart due to
small values of Cint. This makes BiCMOS ineffective when it comes to the implementation of
internal gates for logic structures such as ALUs, where associated load capacitances are small.
BiCMOS devices have speed degradation in the low supply voltage region and also BiCMOS is
having greater manufacturing complexity than CMOS.

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UNIT II VLSI CIRCUIT DESIGN PROCESS

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2.1 INTRODUCTION
Design processes are always associated with certain concepts like stick diagrams and
symbolic diagrams. But the key element is a set of design rules which forms the communication link
between the designer (specifying requirements) and the fabricator (who materializes them). Design
rules are used to produce workable mask layouts from which the various layers in silicon will be
formed or patterned. Among the design rules Lambda –based rules are important. They are
straightforward and relatively simple to apply. However, they are 'real' and chips can be fabricated
from mask layouts using the lambda-based rule set. Correct and faster designs will be realized if a
fabricator's line is used to its full advantage and such rule sets are needed not only to the fabricator
but also to a specific technology.
2.2 VLSI DESIGN FLOW
The VLSI design cycle starts with a formal specification of a VLSI chip, follows a series of
steps, and eventually produces a packaged chip. A typical design cycle may be represented by the
flow chart shown in Figure 2.1 VLSI design flow.

Figure 2.1 VLSI design flow

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Our emphasis is on the physical design step of the VLSI design cycle. However, to gain a global
perspective, we briefly outline all the steps of the VLSI design cycle.

1. System Specification
 The first step of any design process is to lay down the specifications of the system. System
specification is a high level representation of the system. The factors to be considered in this
process include: performance, functionality, and physical dimensions (size of the die (chip)).
The fabrication technology and design techniques are also considered.
 The specification of a system is a compromise between market requirements, technology and
economical viability. The end results are specifications for the size, speed, power, and
functionality of the VLSI system.

2. Architectural Design
 The basic architecture of the system is designed in this step. This includes, such decisions as
RISC (Reduced Instruction Set Computer) versus CISC (Complex Instruction Set Computer),
number of ALUs, Floating Point units, number and structure of pipelines, and size of caches
among others.
 The outcome of architectural design is a Micro-Architectural Specification (MAS). While
MAS is a textual (English like) description, architects can accurately predict the performance,
power and die size of the design based on such a description.

3. Behavioral or Functional Design

 In this step, main functional units of the system are identified. This also identifies the
interconnect requirements between the units. The area, power, and other parameters of each
unit are estimated.
 The behavioral aspects of the system are considered without implementation specific
information. For example, it may specify that a multiplication is required, but exactly in
which mode such multiplication may be executed is not specified. We may use a variety of
multiplication hardware depending on the speed and word size requirements. The key idea is
to specify behavior, in terms of input, output and timing of each unit, without specifying its
internal structure.

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 The outcome of functional design is usually a timing diagram or other relationships between
units. This information leads to improvement of the overall design process and reduction of
the complexity of subsequent phases. Functional or behavioral design provides quick
emulation of the system and allows fast debugging of the full system. Behavioral design is
largely a manual step with little or no automation help available.
4. Logic Design
 In this step the control flow, word widths, register allocation, arithmetic operations, and logic
operations of the design that represent the functional design are derived and tested.
 This description is called Register Transfer Level (RTL) description. RTL is expressed in a
Hardware Description Language (HDL), such as VHDL or Verilog. This description can be
used in simulation and verification. This description consists of Boolean expressions and
timing information. The Boolean expressions are minimized to achieve the smallest logic
design which conforms to the functional design. This logic design of the system is simulated
and tested to verify its correctness. In some special cases, logic design can be automated
using high level synthesis tools. These tools produce a RTL description from a behavioral
description of the design.

5. Circuit Design
 The purpose of circuit design is to develop a circuit representation based on the logic design.
The Boolean expressions are converted into a circuit representation by taking into
consideration the speed and power requirements of the original design. Circuit Simulation is
used to verify the correctness and timing of each component.
 The circuit design is usually expressed in a detailed circuit diagram. This diagram shows the
circuit elements (cells, macros, gates, transistors) and interconnection between these
elements. This representation is also called a netlist. Tools used to manually enter such
description are called schematic capture tools. In many cases, a netlist can be created
automatically from logic (RTL) description by using logic synthesis tools.

6. Physical Design
 In this step the circuit representation (or netlist) is converted into a geometric representation.
As stated earlier, this geometric representation of a circuit is called a layout. Layout is created

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by converting each logic component (cells, macros, gates, transistors) into a geometric
representation (specific shapes in multiple layers), which perform the intended logic function
of the corresponding component. Connections between different components are also
expressed as geometric patterns typically lines in multiple layers.
 The exact details of the layout also depend on design rules, which are guidelines based on the
limitations of the fabrication process and the electrical properties of the fabrication materials.
Physical design is a very complex process and therefore it is usually broken down into
various sub-steps. Various verification and validation checks are performed on the layout
during physical design.
 In many cases, physical design can be completely or partially automated and layout can be
generated directly from netlist by Layout Synthesis tools. Layout synthesis tools, while fast,
do have an area and performance penalty, which limit their use to some designs. Manual
layout, while slow and manually intensive, does have better area and performance as
compared to synthesized layout. However this advantage may dissipate as larger and larger
designs may undermine human capability to comprehend and obtain globally optimized
solutions.

7. Fabrication
 After layout and verification, the design is ready for fabrication. Since layout data is typically
sent to fabrication on a tape, the event of release of data is called Tape Out. Layout data is
converted (or fractured) into photo-lithographic masks, one for each layer. Masks identify
spaces on the wafer, where certain materials need to be deposited, diffused or even removed.
Silicon crystals are grown and sliced to produce wafers. Extremely small dimensions of VLSI
devices require that the wafers be polished to near perfection. The fabrication process consists
of several steps involving deposition, and diffusion of various materials on the wafer. During
each step one mask is used. Several dozen masks may be used to complete the fabrication
process.
 A large wafer is 20 cm (8 inch) in diameter and can be used to produce hundreds of chips,
depending of the size of the chip. Before the chip is mass produced, a prototype is made and
tested. Industry is rapidly moving towards a 30 cm (12 inch) wafer allowing even more chips
per wafer leading to lower cost per chip.

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8. Packaging, Testing and Debugging

 Finally, the wafer is fabricated and diced into individual chips in a fabrication facility. Each
chip is then packaged and tested to ensure that it meets all the design specifications and that it
functions properly. Chips used in Printed Circuit Boards (PCBs) are packaged in Dual In-line
Package (DIP), Pin Grid Array (PGA), Ball Grid Array (BGA), and Quad Flat Package
(QFP). Chips used in Multi-Chip Modules (MCM) are not packaged, since MCMs use bare or
naked chips.

2.3 MOS Layers

MOS design is aimed at turning a specification into masks for processing silicon to meet the
specification. We have seen that MOS circuits are formed on four basic layers-n-diffusion-
diffusion, polysilicon, and metal, which are isolated from one another by thick or thin(thinox)
silicon dioxide insulating layers. The thin oxide (thinox) mask region includes n-diffusion, p-
diffusion, and transistor channels. Polysilicon and thinox regions interact so that a transistor is
formed where they cross one another. In some processes, there may be a second metal layer and
also, in some processes, a second polysilicon layer. Layers may deliberately joined together
where contacts are formed. It is also clear that the basic MOS transistor properties can be
modified by the use of an implant within the thinox region and this is used in nMOS circuits to
produce depletion mode transistors. The BiCMOS technology is developed by including the
bipolar transistors in this design process by the addition of extra layers to a CMOS process.
2.4 Stick Diagrams

A stick diagram is a diagrammatic representation of a chip layout that helps to abstract a

model for design of full layout from traditional transistor schematic. Stick diagrams are used to
convey the layer information with the help of a color code .For example, in the case of nMOS
design, green color is used for n-diffusion, red for polysilicon, blue for metal, yellow for
implant, and black for contact areas. Monochrome encoding is also used in stick diagrams to
represent the layer information. The monochrome encoding chosen is shown in Figure 2.2
Monochrome encoding. Figure 2.3 shows the Encodings for a Double Metal CMOS Process.

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Figure 2.2 Monochrome encoding

Figure 2.3 Encodings for a Double Metal CMOS

Process

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The layout of stick diagrams faithfully reflects the topology of the actual layout in silicon. The
color encoding is compatible with color terminals, printers, and plotters having quite simple
color palettes. Using color workstations, the mask areas are usually color filled while pen plotters
produce color outlines only. Figure 2.4 shows the Encodings for a simple metal nMOS
process(color)

Figure 2.4 Encodings for a simple metal nMOS process(color)

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Stick diagram for n-MOS transistor is shown in the Figure 2.5. The two parallel rails indicate V DD
and gnd

Figure 2.5 Stick diagram for nMOS transistor

2.4.1 nMOS Design Style

To understand the design rules for nMOS design style , let us consider a single metal, single
polysilicon nMOS technology.
The layout of nMOS is based on the following important features.

• n-diffusion [n-diff.] and other thin oxide regions [thinox] (green) ;

• polysilicon 1 [poly.]-since there is only one polysilicon layer here (red);
• metal 1 [metal]-since we use only one metal layer here (blue);
• implant (yellow);
• contacts (black or brown [buried]).
A transistor is formed wherever poly. crosses n-diff. (red over green) and all diffusion
wires (interconnections) are n-type (green). When starting a layout, the first step normally
taken is to draw the metal (blue) V DD and GND rails in parallel allowing enough space
between them for the other circuit elements which will be required. Next, thinox (green)
paths may be drawn between the rails for inverters and inverter- based logic as shown in
This is illustrated in the Figure 2.6 (a). Inverters and inverter-based logic comprise a pull-up
structure, usually a depletion mode transistor, connected from the output point to V DD and a
pull- down structure of enhancement mode transistors suitably interconnected between the
output point and GND.This is illustrated in the Figure 2.6 (b). Remembering that poly. (red)

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crosses thinox (green) wherever transistors are required. One should consider the implants
(yellow) for depletion mode transistors and also consider the length to width (L : W) ratio
for each transistor. These ratios are important particularly in nMOS and nMOS- like
circuits. This is illustrated in the Figure 2.6 (c).

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Figure 2.6 nMOS stick layout design style

2.4.2 CMOS Design Style

The CMOS design rules are almost similar and extensions of n-MOS design rules except
the implant (yellow) and the buried contact (brown). In CMOS design Yellow is used to identify
p- transistors and wires, as depletion mode devices are not utilized. The two types of transistors
'n' and 'p', are separated by the demarcation line (representing the p-well boundary) above which
all p-type devices are placed (transistors and wires (yellow). The n-devices (green) are
consequently placed below the demarcation line and are thus located in the p-well as shown in
the diagram below.

Figure 2.7 Demarcation line for nMOS and pMOS transistor

Diffusion paths must not cross the demarcation line and n-diffusion and p-diffusion wires must
not join. The 'n' and 'p' features are normally joined by metal where a connection is needed. Their
geometry will appear when the stick diagram is translated to a mask layout. However, one must
not forget to place crosses on VDD and Vss rails to represent the substrate and p-well connection
respectively.
The design style is explained by taking the example the design of a single bit shift register. The
design begins with the drawing of the V DD and Vss rails in parallel and in metal and the creation
of an (imaginary) demarcation line in-between, as shown in Figure 2.8 (a). The n-transistors are
then placed below this line and thus close to Vss, while p-transistors are placed above the line
and below VDD In both cases, the transistors are conveniently placed with their diffusion paths
parallel to the rails (horizontal in the diagram) as shown in Figure 2.8 (b). A similar approach

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can be taken with transistors in symbolic form.

Figure 2.8 CMOS stick layout design style

The n- along with the p-transistors are interconnected to the rails using the metal and connect as
shown in Figure 2.8 (c). It must be remembered that only metal and poly-silicon can cross the
demarcation line but with that restriction, wires can run-in diffusion also. Finally, the remaining
interconnections are made as appropriate and the control signals and data inputs are added as
shown in the Figure 2.8 (d).

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2.5 Design Rules and Layout

The design rules are formed to translate the circuit design concepts , (usually in stick diagram or
symbolic form) into actual geometry in silicon. The design rules are the effective interface between
the circuit/system designer and the fabrication engineer. The design rules also help to provide a
reliable compromise between the circuit/system designer and the fabrication engineer. In general the
circuit designers expect smaller layouts for improved performance and decreased silicon area. On the
other hand, the process engineer like those design rules that result in a controllable and reproducible
process. In fact there is a need of compromise for a competitive circuit to be produced at a reasonable
cost.
One of the important factors associated with design rules is the achievable definition of the process
line. For example, it is found that if a 10: 1 wafer stepper is used instead of a 1: 1 projection mask
aligner; the level-to-level registration will be closer. Design rules can be affected by the maturity of
the process line. For example, if the process is mature, then one can be assured of the process line
capability, allowing tighter designs with fewer constraints on the designer.
The simple and well known design rules that are widely used in the design of multiproject chips are
'lambda (λ)-based' design rules developed by Mead and Conway.

2.5.1 Lambda-based Design Rules

In this Lambda –base design rules all paths in all layers will be dimensioned in λ units and
subsequently λ can be allocated an appropriate value compatible with the feature size of the
fabrication process. These design rules are such that, if correctly obeyed, the mask layouts will
produce working circuits for a range of values allocated to λ. For example, λ can be allocated a value
of 1.0µm so that minimum feature size on chip will be 2 µm (2λ). Design rules, also, specify line
widths, separations, and extensions in terms of λ. Design rules can be conveniently set out in
diagrammatic form as shown in Figure 2.9 (a) for wires, and the Figure 2.9 (b) for extensions and
separations associated with transistor layouts.

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Figure 2.9 (a) Design rules for wires (n-MOS and p-MOS)

Figure 2.9 (b) Design rules for transistors (n-MOS , p-MOS, CMOS)

2.5.2 Contact Cuts

While making contacts between poly-silicon and diffusion in nMOS circuits it should be
remembered that there are three possible approaches--poly. to metal then metal to diff., or a buried
contact poly. to diff. , or a butting contact (poly. to diff. using metal). Among the three the latter two,
the buried contact is the most widely used, because of advantage in space and a reliable contact. At
one time butting contacts were widely used , but now a days they are superseded by buried contacts.

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In CMOS designs, poly. to diff. contacts are always made via metal. A simple process is
followed for making connections between metal and either of the other two layers as shown in Figure
2.10 (a).The 2λ. x 2λ. contact cut indicates an area in which the oxide is to be removed down to the
underlying polysilicon or diffusion surface. When deposition of the metal layer takes place the metal
is deposited through the contact cut areas onto the underlying area so that contact is made between
the layers.
The process is more complex for connecting diffusion to poly-silicon using the butting contact
approach as shown in Figure 2.10 (b). In effect, a 2λ. x 2λ contact cut is made down to each of the
layers to be joined. The layers are butted together in such a way that these two contact cuts become
contiguous. Since the poly-silicon and diffusion outlines overlap and thin oxide under poly- silicon
acts as a mask in the diffusion process, the poly-silicon and diffusion layers are also butted together.
The contact between the two butting layers is then made by a metal overlay as shown in the
Figure 2.10.

Figure 2.10 (a) n-MOS & C-MOS Contacts

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Figure 2.10 (b) Contacts poly-silicon to diffusion

In buried contact basically, layers are joined over a 2λ. x 2λ. area with the buried contact cut
extending by 1λ, in all directions around the contact area except that the contact cut extension is
increased to 2λ. In diffusion paths leaving the contact area. This helps to avoid the formation of
unwanted transistors .So, this buried contact approach is simpler when compared to others. The,
poly-silicon is deposited directly on the underlying crystalline wafer. When diffusion takes place,
impurities will diffuse into the poly-silicon as well as into the diffusion region within the contact
area. Thus a satisfactory connection between poly-silicon and diffusion is ensured. Buried contacts
can be smaller in area than their butting contact counterparts and, since they use no metal layer, they
are subject to fewer design rule restrictions in a layout.

2.5.3 Double metal MOS process rules

In the MOS design rules a powerful design process is achieved by adding a second metal layer.
This gives a much greater degree of freedom, in distributing global V DD and Vss(GND) rails in a
system. From the overall chip inter-connection aspect, the second metal layer in particular is
important and, although the use of such a layer is readily envisaged, its disposition relative to its
connection. to other layers using metal1 to metal 2 contacts, called vias ,can be readily established .

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Usually, second level metal layers are coarser than the first (conventional) layer and the isolation
layer between the layers may also be of relatively greater thickness. To distinguish contacts between
first and second metal layers, they are known as vias rather than contact cuts. The second metal layer
representation is color coded dark blue (or purple).
The important process steps for a two-metal layer process are given below.
The oxide below the first metal layer is deposited by atmospheric chemical vapor deposition (CVD)
and the oxide layer between the metal layers is applied in a similar manner. Depending on the
process, removal of selected areas of the oxide is accomplished by plasma etching, which is designed
to have a high level of vertical ion bombardment to allow for high and uniform etch rates. Similarly,
the bulk of the process steps for a double polysilicon layer process are similar in nature to those
already described, except that a second thin oxide layer is grown after depositing and patterning the
first polysilicon layer (Poly.1) to isolate it from the now to be deposited second poly. layer (Poly.2).
The presence of a second poly. layer gives greater flexibility in interconnections and also allows
Poly.2 transistors to be formed by intersecting Poly. 2 and diffusion.
The important features of double metal process are summarized as follows

Use the second level metal for the global distribution of power buses, that is, V DD and GND
( Vss), and for clock lines.

Use the first level metal for local distribution of power and for signal lines.

Lay out the two metal layers so that the conductors are mutually orthogonal wherever possible.

2.5.4 CMOS Lambda-based Design Rules

The CMOS fabrication process is more complex than nMOS fabrication. In a CMOS process,
there are nearly 100 actual set of industrial design rules. The additional rules are concerned with
those features unique to p-well CMOS, such as the p-well and p+ mask and the special 'substrate'
contacts. The p-well rules are shown in the Figure 2.11.

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 Each of the above arrangements can be merged into single split contacts

 Split contacts may also be made with separate cuts.

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Figure 2.11 Particular rules for p-well CMOS Process

The CMOS rules are designed based on the extensions of the Mead and Conway concepts and also
by excluding the butting and buried contacts the new rules for CMOS design are formed.
2.5.5 2 μm CMOS Design Rules for Wires, Contacts and Transistor

The microscopic dimensions of Silicon circuits always cause some problems in the design
process.The major problem is presented by possible deviation in line widths and in interlayer
registration. If the line widths are too small, it is possible for lines to be discontinuous in places. If
separate paths in a layer are placed too close together, it is possible that they will merge in places or
interfere with each other.
For the lambda-based rules , the design rules are formulated in terms of a length unit λ which
is related to the resolution of the process λ may be viewed as a limit on the width deviation of a
feature from its ideal 'as drawn' size and also as a bound on the maximum misalignment of any one
mask. In the worst case, these effects may combine to cause the relative position of feature edges on
different mask levels to deviate by as much as 2λ in their interrelationship. Inevitably, a
consequence of using the lambda-based concept is that every dimension must be rounded up to
whole λ values and this leads to layouts which do not fully exploit the capabilities of the process.
Similar concepts underlie the establishment of 'micron-based' rule sets, but actual dimensions are

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given so that full advantage can be taken of the fabrication line capabilities and tighter layouts
result.Layout rules, therefore, provide strict guidelines for preparing the geometric layouts which
will be used to configure the actual masks used during fabrication and can be regarded as the main
communication link between circuit/systems designers and the process engineers engaged in
manufacture. The goal of any set of design rules should give optimize yield while keeping the
geometry as small as possible without compromising the reliability of the finished circuit. On the
questions of yield and reliability, even the conservative nature of the lambda based rules can stand
reevaluation when these two factors are of paramount importance. In particular, the rules associated
with contacts can be improved upon in the light of experience. Figure 2.12 (a) sets out aspects that
may be observed for high yield and in high reliability situations. In our proposed scheme of events
in creating stick layouts for CMOS, it is assumed that poly. and metal can both freely cross well
boundaries and this is indeed the case, but we should be careful to try to exclude poly. from areas
which lie within p+ mask areas where possible. The reason for this is that the resistance of the poly.
layer is reduced in current processes by n- type doping. Clearly the p+ doping which takes place
inside the p+ mask will also dope the poly. which is already in place when the p+ doping step takes
place. This results in an increase in the n- doping poly. resistance which may be significant in
certain parts of a system.

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The 3λ. metal width rule is a conservative one but is implemented to allow for the fact that the metal
layer is deposited after the others and on top of them and several layers of silicon dioxide, so that
the surface on which it sits is quite 'mountainous' . The metal layer is also light-reflective and these
factors combine to result in poor edge definition. In double metal the second layer of metal has an
even more uneven terrain on which to be deposited and patterned. Hence metal 2 is often wider than
metal 1.
Metal to metal separation is also large and is brought about mainly by difficulties in defining metal
edges accurately during masking operations on the highly reflective metal. All diffusion processes
are such that lateral diffusion occurs as well as impurity penetration from the surface. Hence the
separation rules for diffusion allow for this and relatively large separations are specified. This is
particularly the case for the p-well diffusions which are deep diffusions and thus have considerable
lateral spread. Transitions from thin gate oxide to thick field oxide in the oxidation process also use

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up space and this is another reason why the lambda-based rules require a minimum separation
between thinox regions of 3λ. In effect, this implies that the minimum feature size for thick oxide is
3λ.The simplicity of the lambda-based rules makes this approach to design an appropriate one for
the novice chip designer and also, perhaps, for those applications in which we are not trying to
achieve the absolute minimum area and the absolute maximum performance. Because lambda-based
rules try 'to be all things to all people', they do suffer from least common denominator effects and
from the upward rounding of all process line dimension parameters into integer values of lambda.
The performance of any fabrication line in this respect clearly comes down to a matter of tolerances
and definitions in terms of microns (or some other suitable unit of length).Thus, expanded sets of
rules often referred to as micron-based rules are available to the more experienced designer to allow
for the use of the full capability of any process. Also, many processes offer additional layers, which
again adds to the possibilities presented to the designer. In order to properly represent these
important aspects, the next section introduces Orbit Semiconductor's 2µm feature size double metal,
double poly. n-well CMOS rules which also offer a BiCMOS capability.
2.6 Transistor layout diagrams for NMOS and CMOS inverters

Figure 2.15 shows the stick diagram and layout diagram of nMOS inverter.

a. Circuit diagram of nMOS inverter b. Stick diagram of nMOS inverter

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c. Layout diagram of nmos inverter

Figure 2.15 Stick diagram and layout diagram of nMOS inverter
2.7 Scaling of MOS circuits

• VLSI technology is constantly evolving towards smaller line widths

• Reduced feature size generally leads to
– better / faster performance
– More gate / chip
• More accurate description of modern technology is ULSI (ultra large scale integration
• In our discussions we will consider 2 scaling factors, α and β
• 1/ β is the scaling factor for VDD and oxide thickness D
• 1/ α is scaling factor for all other linear dimensions
• We will assume electric field is kept constant.
Table 2.1 shows the Scaling of MOS circuits.

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Table 2.1 Scaling of MOS circuit

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UNIT III GATE LEVEL DESIGN

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3.1 INTRODUCTION
The module (integrated circuit) is implemented in terms of logic gates and interconnections
between these gates. Designer should know the gate-level diagram of the design. In general, gate-level
modeling is used for implementing lowest level modules in a design like, full-adder, multiplexers, etc.
Boolean algebra is used to represent logical(combinational logic) functions of digital circuits. A
combinational logic expression is a mathematical formula which is to be interpreted using the laws of
Boolean algebra. Now the goal of logic design or optimization is to find a network of logic gates that
together compute the combinational logic function we want.
For example, given the expression a+b , we can compute its truth value for any given values of a and
b , and also we can evaluate relationships such as a+b = c. but logic design is difficult for many
reasons:
 We may not have a logic gate for every possible function, or even for every function of n
inputs.
 Not all gate networks that compute a given function are alike-networks may differ greatly in
their area and speed.
 Thus combinational logic expressions are the specification,
Logic gate networks are the implementation, Area, delay, and power are the costs.
 A logic gate is an idealized or physical device implementing a Boolean function, that is, it
performs a logical operation on one or more logic inputs and produces a single logic output.
 Logic gates are primarily implemented using diodes or transistors acting as electronic
switches, but can also be constructed using electromagnetic relays (relay logic), fluidic logic,
pneumatic logic, optics, molecules, or even mechanical elements.
 With amplification, logic gates can be cascaded in the same way that Boolean functions can
be composed, allowing the construction of a physical model of all of Boolean logic.
 simplest form of electronic logic is diode logic. This allows AND and OR gates to be built,
but not inverters, and so is an incomplete form of logic. Further, without some kind of
amplification it is not possible to have such basic logic operations cascaded as required for
more complex logic functions.
 To build a functionally complete logic system, relays, valves (vacuum tubes), or transistors
can be used.
 The simplest family of logic gates using bipolar transistors is called resistor-transistor logic
(RTL). Unlike diode logic gates, RTL gates can be cascaded indefinitely to produce more
complex logic functions. These gates were used in early integrated circuits. For higher speed,
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the resistors used in RTL were replaced by diodes, leading to diode- transistor logic (DTL).
 Transistor-transistor logic (TTL) then supplanted DTL with the observation that one
transistor could do the job of two diodes even more quickly, using only half the space.
 In virtually every type of contemporary chip implementation of digital systems, the bipolar
transistors have been replaced by complementary field-effect transistors (MOSFETs) to
reduce size and power consumption still further, thereby resulting in complementary metal–
oxide–semiconductor (CMOS) logic that can be described with Boolean logic.

3.2 CMOS LOGIC GATES AND OTHER COMPLEX GATES

General logic circuit Any Boolean logic function (F) has two possible values, either logic 0 or logic
1. For some of the input combinations, F = 1 and for all other input combinations, F = 0. So in general,
any Boolean logic function can be realized using a structure as shown in Figure 3.1.

Figure 3.1 General structure of any Boolean function

 The switch S1 is closed and switch S2 is open for input combinations that produces F = 1.
 The switch S1 is open and switch S2 is closed for input combinations that produces F = 0.
 The switch S1 is open and switch S2 is open for input combinations that produces F = 0.
Thus the output (F) is either connected to V DD or the ground, where the logic 0 is represented by
the ground and the logic 1 is represented by VDD. So the requirement of digital logic design is to
implement the pull-up switch(S1) and the pull-down switch(S2).

3.2.1 CMOS static logic

A generalized CMOS logic circuit consists of two transistor nets nMOS and pMOS as shown in
Figure 3.2. The pMOS transistor net is connected between the power supply and the logic gate output
called as pull-up network , Whereas the nMOS transistor net is connected between the output and
ground called as pull-down network. Depending on the applied input logic, the PUN connects the

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output node to VDD and PDN connects the output node to the ground.

Figure 3.2 CMOS static logic

The transistor network is related to the Boolean function with a straight forward design procedure:
 Design the pull down network (PDN) by realizing, AND(product) terms using series-
connected nMOSFETs. OR (sum) terms using parallel-connected nMOSFETS.
 Design the pull-up network by realizing,
AND(product) terms using parallel-connected nMOSFETs. OR (sum) terms using series-connected
nMOSFETS.
 Add an inverter to the output to complement the function. Some functions are inherently
negated, such as NAND,NOR gates do not need an inverter at the output terminal.

3.2.2 CMOS inverter

A CMOS inverter is the simplest logic circuit that uses one nMOS and one pMOS transistor. The
nMOS is used in PDN and the pMOS is used in the PUN as shown in Figure 3.3.

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Figure 3.3 Static CMOS inverter

Working operation

1) When the input Vin is logic HIGH, then the nMOS transistor is ON and the pMOS
transistor is OFF. Thus the output Y is pulled down to ground (logic 0) since it is
connected to ground but not to source VDD as shown in Figure 3.4 (a)

2) When the input Vin is logic LOW, then nMOS transistor is OFF and the pMOS transistor
is ON, Thus the output Y is pulled up to VDD(logic 1) since it is connected to source via
pMOS but not to ground as shown in Figure 3.4 (b).

Figure 3.4 Working of static CMOS inverter

3.2.3 CMOS NAND gate

The two input NAND function is expressed by Y=A.B

Step 1 Take complement of Y

Y= A.B = A.B

Step 2 Design the PDN

In this case, there is only one AND term, so there will be two nMOSFETs in series as shown in Figure
3.5 (a).

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Step 3 Design the PUN. In PUN there will be two pMOSFETs in parallel , as shown in Figure 3.5 (b).

Figure 3.5 PDN and PUN of static CMOS NAND gate

Finally join the PUN and PDN as shown in Figure 3.5 (c) which realizes two –input NAND gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the nature of
the CMOS circuit operation

Figure 3.5 (c) Static CMOS NAND gate

Working operation

1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will conduct

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while the corresponding nMOS transistor will turn OFF. Subsequently, the output voltage
will be HIGH.
2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will turn
OFF, and the output voltage will be pulled LOW by the two conducting nMOS transistors.

3.2.4 CMOS NOR gate

The two input NOR function is expressed by Y=A+B

Step 1 Take complement of Y

Y= A+B = A+B

Step 2 Design the PDN

In this case, there is only one OR term, so there will be two nMOSFETs connected in parallel, as
shown in Figure 3.6 (a)
Step 3 Design the PUN

In PUN there will be two pMOSFETs in series , as shown in Figure 3.6 (b)

Figure 3.6 PDN and PUN of static CMOS NOR gate

Finally join the PUN and PDN as shown in Figure 3.6 (c) which realizes two –input NOR gate. Note
that we have realized y, rather tat Y because the inversion is automatically provided by the nature of

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the cMOS circuit operation,

Working operation
1) Whenever at least one of the inputs is LOW, the corresponding pMOS transistor will conduct
while the corresponding nMOS transistor will turn OFF. Subsequently, the output voltage
will be HIGH.

2) Conversely, if both inputs are simultaneously HIGH, then both pMOS transistors will turn
OFF, and the output voltage will be pulled LOW by the two conducting nMOS transistors.

Figure 3.6 (c) Static CMOS NOR gate

3.3 COMPLEX GATES IN CMOS LOGIC

A complex logic gate is one that implements a function that can provide the basic NOT, AND and
OR operation but integrates them into a single circuit. CMOS is ideally suited for creating gates that
have logic equations by exhibiting the following,
1) AND-OR-INVERT - AOI form
2) OR-AND-INVERT - OAI form
An AOI logic equation is equivalent to a complemented SOP from, while an AOI equation is
equivalent to a complemented POS structure. In CMOS, output always produces NOT operation acting
on input variable.
1) AOI Logic Function

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AND-OR-INVERT logic function(AOI) implements operation in the order

AND,OR,NOT. For example , let us consider the function Y = AB+CD i.e., Y = NOT((A AND B)OR
(C AND D)) The AOI logic gate implementation for Y is shown in the Figure 3.6

Figure 3.7 AOI Implementation of Y = AB+CD

CMOS implementation for Y

Step 1: Draw A.B (AND) function first by connecting 2 nMOS transistors in series as shown in Figure
3.8 (a).

Figure 3.8 (a) A.B PDN implementation

Step 2: Draw C.D implementation, by using 2 nMOS transistors in series as shown in the Figure 3.8
(b).

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Figure 3.8 (b) C.D PDN implementation

Step 3: Y = A.B+C.D , In this function A.B and C.D are added, for addition , we have to draw parallel
connection. So, A.B series connected in parallel with C.D as shown in Figure 3.8 (c).

Figure 3.8 (c) PDN implementation of A.B+C.D

Step 4: Draw pMOS connection,
I. In nMOS A,B connected in series. So, in pMOS side, A.B should be connected in
parallel.
II. In nMOS C,D connected in series. So, in pMOS side, C.D should be connected in
parallel.
III. A.B and C.D networks are connected in parallel in nMOS side. So, in pMOS side,
A.B and C.D networks should be connected in series.
IV. In pMOS multiplication should be drawn in parallel, then addition should be drawn in
series as shown in Figure 3.8(d).

Figure 3.8 (d) PUN implementation of A.B+C.D

Step 5: Take output at the point in between nMOS and pMOS networks.

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Figure 3.8 (e) CMOS implementation for Y

OAI Logic Function

OR-AND-INVERT logic function(AOI) implements operation in the order
OR,AND,NOT. For example , let us consider the function Y = (A+B).(C+D) i.e., Y = NOT((A OR
B)AND (C OR D)) The OAI logic gate implementation for Y is shown in the Figure 3.9

Figure 3.9 OAI Implementation of Y = (A+B).(C+D)

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CMOS implementation for Y is shown in the Figure 3.10

Figure 3.10 CMOS implementation for Y

3.4 SWITCH LOGIC
1) Switch logic is mainly based on pass transistor or transmission gate.
2) It is fast for small arrays and takes no static current from the supply, V DD. Hence power
dissipation of such arrays is small since current only flows on switching.
3) Switch (pass transistor) logic is analogous to logic arrays based on relay contacts, where
in path through each switch is isolated from the logic levels activating the switch.
3.4.1 Pass transistor
1) This logic uses transistors as switches to carry logic signals from node to node instead of
connecting output nodes directly to VDD or ground(GND)

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2) If a single transistor is a switch between two nodes, then voltage degradation.equal to v t

(threshold voltage) for high or low level depends up on nMOS or pMOS logic as shown
in Figure 3.11.

Figure 3.11 Properties of nMOS and pMOS

3) When using nMOS switch logic no pass transistor gate input may be driven through one
or more pass transistors as shown in Figure 3.12.

Figure 3.12 Cascading pass transistors

4) Since the signal out of pass transistor T1 does not reach a full logic 1 by threshold voltage
effects signal is degraded by below a tru e logic 1, this degraged voltage would not permit
the output of T2 to reach an acceptable logic 1 level.
Advantages
1) Requires minimum geometry.
2) Do not dissipate standby power, since they do not have a path from supply to ground.
Disadvantages
1) Degradation in the voltage levels due to undesirable threshold voltage effects.
2) Never drive a pass transistor with the output of another pass transistor.
3.4.2 Transmission gate
1) It is an electronic element, good non-mechanical relay built with CMOS technology.
2) It is made by parallel combination of an nMOS and pMOS transistors with the input at
gate of one transistor being complementary to the input at the gate of the other as shown
in figure

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3) Thus current can flow through this element in either direction.

4) Depending on whether or not there is a voltage on the gate, the connection between the
input and output is either low resistance or high-resistance, respectively R on =
100Ω and Roff > 5 MΩ.

Operation

 When the gate input to the nMOS transistor is ‘0’ and the complementary ‘1’ is gate input to
the pMOS , thus both are turned off.
 When gate input to the nMOS is ‘1’ and its complementary ‘0’ is the gate input to the pMOS ,
both are turned on and passes any signal ‘1’ and ‘0’ equally without any degradation.
 The use of transmission gates eliminates the undesirable threshold voltage effects which give
rise to loss of logic levels in pass-transistors as shown in Figure 3.13.
Figure 3.13 Transmission gate

Advantages

1) Transmission gates eliminates the signal degradation in the output logic levels.
2) Transmission gate consists of two transistors in parallel and except near the positive and
negative rails.
Disadvantages

1) Transmission gate requires more area than nMOS pass circuitry.

2) Transmission gate requires complemented control signals.

“ Transmission gate logic can be used to design multiplexers(selector functions)”.

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 Design a 2-input multiplexer using CMOS transmission gates.

Figure 3.14 shows a 2-input multiplexer circuit using CMOS transmission gate.
Figure 3.14 2-input multiplexer circuit using CMOS transmission gate

If the control input S is low, the TG0 conducts and the output F is equal to A. On the other hand, if the
control input S is high the TG1 conducts and the output F is equal to B.

3.5 ALTERNATIVE GATE CIRCUITS

CMOS suffers from increased area and correspondingly increased capacitance and delay, as the logic
gates become more complex. For this reason, designers developed circuits (Alternate gate circuits) that
can be used to supplement the complementary type circuits . These forms are not intended to replace
CMOS but rather to be used in special applications for special purposes.
3.5.1 Pseudo nMOS Logic
Pseudo nMOS logic is one type of alternate gate circuit that is used as a supplement for the
complementary MOS logic circuits. In the pseudo-nMOS logic, the pull up network (PUN) is realized by
a single pMOS transistor. The gate terminal of the pMOS transistor is connected to the ground. It remains
permanently in the ON state. Depending on the input combinations, output goes low through the PDN.
Figure 3.15 shows the general building block of logic circuits that follows pseudo nMOS logic.

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Figure 3.15 Pseudo nMOS logic

Here, only the nMOS logic (Qn) is driven by the input voltage, while the gate of p-transistor(Qp) is
connected to ground or substrate and Qp acts as an active load for Qn. Except for the load device, the
pseudo-nMOS gate circuit is identical to the pull-down network(PDN) of the complementary CMOS gate.

Figure 3.16 Logic circuits using pseudo-nMOS logic

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Figure 3.16 shows the realization of logic circuits using pseudo-nMOS logic.

Advantages

1) Uses less number of transistors as compared to CMOS logic.

2) Geometrical area and delay gets reduced as it requires less transistors.
3) Low power dissipation.

Disadvantages

1) The main drawback of using a pseudo nMOS gate instead of a CMOS gate is that the always on
PMOS load conducts a steady current when the output voltage is lower than VDD.
2) Layout problems are critical.

3.5.2 Dynamic CMOS Logic

A dynamic CMOS logic uses charge storage and clocking properties of MOS transistors to
implement logic operations. Figure 3.17 shows the basic building block of dynamic CMOS logic. Here
the clock ø drives nMOS evaluation transistor and pMOS precharge transistor. A logic is implemented
using an nFET array connected between output node and ground.

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Figure 3.17 Dynamic CMOS logic

The gate (clock ø) defines two phases, evaluation and precharge phase during each clock cycle.

Working

 When clock ø = 0 the circuit is in precharge phase with the pMOS device Mp ON and the
evaluation nMOS Mn OFF. This establishes a conducting path between V DD and the output
allowing Cout to charge to a voltage Vout = VDD. Mp is often called the precharge FET.

 When clock ø = 1 the circuit is in evaluation phase with the pMOS device Mp OFF and the
evaluation nMOS Mn ON. If the logic block acts like a closed switch the C out can discharge
through logic array and Mn, this gives a final result of V out = VDD, logically this is an output of F
= 1. Charge leakage eventually drops the output to V out = 0 Vwhich could be an incorrect logic
value.

The logic formation is formed by three series connected FETs (3-input NAND gate) is shown in Figure
3.18.

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Figure 3.18 Dynamic CMOS NAND gate

The dynamic CMOS logic circuit has a serious problem when they are cascaded. In the precharged phase
(ø = 0) , output of all the stages are pre-charged to logic high. In the evaluation phase (ø = 1), the output
of all stages are evaluated simultaneously. Suppose in the first stage, the inputs are such that the output is
logic low after the evaluation. In the second stage, the output of the first stage is one input and there are
other inputs. If the other inputs of the second stage are such that output of it discharges to logic low, then
the evaluated output of the first stage can never make the output of the second stage logic high. Ths is
because, by the time the first stage is being evaluated, output of the second. Stage is discharged, since
evaluation happens simultaneously. Remember that the output cannot be charged to logic high in the
evaluation phase (ø = 1, pMOSFET in PUN is OFF), it can only be retained in the logic high depending
on the inputs.

Advantages
1) Low power dissipation.
2) Large noise margin.
3) Small area due to less number of transistors.
3.5.3 CMOS domino logic
Standard CMOS logic gates need a PMOS and an NMOS transistor for each logic input. The pMOS

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transistors require a greater area tan the nMOS transistors carrying the same current. So, a large chip area
is necessary to perform complex logic operations. The package density in CMOS is improved if a
dynamic logic circuit, called the domino CMOS logic circuit, is used.
Domino CMOS logic is slightly modified version of the dynamic CMOS logic circuit. In this case, a static
inverter is connected at the output of each dynamic CMOS logic block. The addition of the inverter solves
the problem of cascading of dynamic CMOS logic circuits.
The circuit diagram of domino CMOS logic structures as shown in Figure 3.19 as follows

Figure 3.19 Domino CMOS logic

A domino CMOS AND-OR gate that realizes the function y = AB + CD is depicted in figure . The left
hand part of the circuit containing Mn,Mp, T1,T2,,T3,and T4 forms and AND-OR- INVERTER (AOI)
gate. It derives the static CMOS inverter formed by N2 and P2 in the right-hand part of the circuit. The
domino gate is activated by the single phase clock ø applied to the NMOS (Mn) and the PMOS (Mp)
transistors. The load on the AOI part of the circuits is the parasitic load capacitance.

Working

 When ø = 0, is ON and Mn is OFF, so that no current flows in the AND-OR paths of the AOI.
The capacitor CL is charged to VDD through Mp since the latter is ON. The input to the inverter
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is high, and drives the output voltage V0 to logic-0.

 When ø = 1, Mp is turned OFF and Mn is turned ON. If either (or both) A and B or C and D is
at logic-1, CL discharges through either T2,T1 and Mn or T3,T4 and Mp. So , the inverter input
is driven to logic-0 and hence the output voltage V 0 to logic-1. The Boolean expression for the
output voltage is Y = AB + CD.

Note : Logic input can change only when ø = 0. No changes of the inputs are permitted when ø = 1 since
a discharge path may occur.

Advantages
1) Smaller areas compared to conventional CMOS logic.
2) Parasitic capacitances are smaller so that higher operating speeds are possible.
3) Operation is free of glitches since each gate can make one transition.
Disadvantages
1) Non inverting structures are possible because of the presence of inverting buffer.
2) Charge distribution may be a problem.
3.5.4 Clocked CMOS logic
The clocked CMOS logic is also referred as C 2MOS logic. Figure 3.20 shows the general
arrangement of a clocked CMOS (C2MOS) logic. A pull-up p-block and a complementary n-block pull-
down structure represent p and n-transistors respectively and are used as implement clocked CMOS logic
shown in figure. However, the logic in this case is connected to the output only during the ON period of
the clock. Figure shows a clocked inverter circuit which is also belongs to clocked CMOS logic family.
The slower rise times and fall times can be expected due to owing of extra transistors in series with the
output.

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Figure 3.20 C2MOS logic

Working

 When ø = 1 the circuit acts an inverter , because transistors Q3 and Q4 are ‘ON’ . It is said to be
in the “evaluation mode”. Therefore the output Z changes its previous value.
 When ø = 0 the circuit is in hold mode, because transistors Q3 and Q4 becomes ‘OFF’ . It is
said to be in the “precharge mode”. Therefore the output Z remains its previous value.

3.5.5 n-p CMOS LOGIC

Figure 3.21 shows the another variation of basic dynamic logic arrangement of CMOS logic called
as n-p CMOS logic. In this, logic the actual logic blocks are alternatively ‘n’ and ‘p’ in a cascaded
structure. The clock ø and ø - are used alternatively to fed the precharge and evaluate transistors. However,
the functions of top and bottom transistors are also alternate between precharge and evaluate transistors.

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Figure 3.21 n-p CMOS logic

Working
 During the pre charge phase ø = 0 , the output of the n-tree gate, OUT 1 OUT3 , are charged to
VDD, while the output of the p-tree gate OUT2 is pre discharged to 0V. Since the n-tree gate
connects pMOS pull-up devices, the PUN of the p-tree is turned off at that time.
 During the evaluation phase ø = 1, the outputs (OUT1,OUT3) of the n-tree gate can only make a
1-0 transition, conditionally turning on some transistors in the p-tree. This ensures that no
accidental discharge of OUT 2 can occur.
 Similarly n-tree blocks can follow p-tree gates without any problems, because the inputs to the
n-gate are pre charged to 0.
Disadvantages
Here, the p-tree blocks are slower than the n-tree modules, due to the lower current drive of the pMOS
transistors in the logic network.

3.6 TIME DELAYS

Consider the basic nMOS inverter has the channel length 8λ and width 2λ for pull-up transistor and
channel length of 2λ and width 2λ for pull down transistor. Hence the sheet resistance for pull-up
transistor is Rp.u = 4RS = 40kΩ and sheet resistance for pull-up transistor is Rp.d = 1RS = 10kΩ.
Since (τ = RC) depends upon the values of R & C, the delay associates with the inverter depend up on
whether it is being turned on (or ) off. Now, consider a pair of cascaded inverters as shown in figure, then
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the delay over the pair will be constant irrespective of the sense of the logic level transition of the input to
the first .
In general, the delay through a pair of similar nMOS inverters is
Td = (1 + Zp.u/Zp.d ) τ
Assume that τ = 0.3 n sec.
Then , Td = (1 + 4) 0.3
=5τ
Thus, the inverter pair delay for inverters having 4:1 ration is 5τ.

Figure 3.22 Inverter pair delay

Hence, a single 4:1 inverter exhibits undesirable asymmetric delays, Since the delay in turning ON is τ
and delay in turning OFF is 4τ.

CMOS inverter pair delay

When we consider CMOS inverters, the rules for nMOS inverters are not applicable. But we need to
consider the natural (RS) uneven values for equal size pull up p-transistor and the n-type pull down
transistors.

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Figure 3.23 CMOS inverter pair delay

Figure 3.23 shows CMOS inverter pair delay. The theoretical delay associated with a pair of both n and p
transistors lambda based inverters. Here the gate capacitance is double comparable to nMOS inverter
since the input to a CMOS inverter is connected to both transistor gate.
NOTE: Here the asymmetry (uneven) of resistance
It can be eliminated by increasing the width of the p-device channel by a factor of two or three at the
same time the gate capacitance of p-transistor also increased by the same factor.

Formal estimation of CMOS inverter delay

In CMOS inverter by the charging and discharging of a capacitive load C L , we can estimate the Rise
time and fall time from the following simple analysis.
Rise time estimation
In this analysis we assume that the p-device stays in saturation for the entire charging period of the
load capacitor CL.
Consider the circuit Figure 3.24 ,
Figure 3.24 Estimation of CMOS inverter delay

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Saturation current for the p-transistor is given by

This current charges CL and since its magnitude is approximately constant, we have

Substitute the value of Idsp in above equation and then the rise time is

Assume that t = τr when Vout = VDD then

If Vtp = 0.2VDD, then

Fall time estimation

Consider the circuit for discharge of CL through n-transistor as follows

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Figure 3.25 Fall time estimation

By making similar assumptions we can write for fall-time estimation,

From the above two estimations we can deduce that

We know that and hence

So that the rise time is slower by a factor of 2.5 when using minimum size devices for both n & p.

 In order to achieve symmetrical operation using minimum channel length we need to make Wp
= 2.5 Wn.

From the above equations we can conclude that

1. τr and τf are proportional to 1/VDD
2. τr and τf are proportional to CL
3. τr = 2.5τf for equal n and p- transistor geometries.

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3.7 DRIVING LARGE CAPACITIVE LOADS

When signals are propagated from the chip to off chip destinations we can face problems to drive
large capacitive loads. Generally off chip capacitances may be several orders higher than on chip □c g
values.
CL ≥ 104 □cg

Where, CL denotes offchip load. The capacitances which of this order must be driven through low
resistances, otherwise excessively long delays will occur. Large capacitance is presented at the input,
which in turn slows down the rate of change of voltage at input.

3.7.1 Cascaded Inverters as drivers

Inverters to drive large capacitive loads must be present low pull-up and pull down resistance. For

MOS circuits low resistance values imply low L:W ) . Since length L cannot be reduced
below the minimum feature size, the channels must be made very wide to reduce resistance value.
Consider N cascaded inverters as on increasing the width factor of ‘f’ than the previous stage as shown in
Figure .

Figure 3.26 Cascaded inverters

As the width factor increases, the capacitive load presented at the inverter input increases and the area
occupied increases also. It is observed that as the width increases, the number N of stages are decreased to
drive a particular value of CL. Thus with large f(width), N decreases but delay per stage increases for 4:1
nMOS inverters.

Delay per stage = fτ for ∆Vin

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=4fτ for ∆-Vin

Where ∆Vin indicates logic 0 to 1 transition and

∆-Vin indicates logic 1 to 0 transition of Vin
Toal delay per nMOS pair = 4fτ
Similarly delay per CMOS pair = 7fτ.

Calculation for time delay

Let us assume y = CL/□cg = f N

Determine the value of f which will minimize the overall delay for a given value of y.

Apply logarithms on both sides in the above equation

ln(y) = ln(f N)

ln (y) = N ln (f)
N = ln(y)/ln(f)

For N even

Total delay = N/2 5fτ

= 2.5 Nfτ (nMOS)

(Or) total delay = N/2 7fτ

= 3.5Nfτ (CMOS)

From above relations, we can write

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Delay α Nfτ

= ln(y)/ln(f) . fτ

It can be shown that total delay is minimized if f assumes the value of e for both CMOS and nMOS
inverters.
Assume f = e  N = ln(y)/ln(e)

N = ln(y)

Overall delay td  N even td = 2.5 eNτ (nMOS)

(or) td = 3.5 eNτ(CMOS)

 N odd td = [2.5(N-1) +1] eτ (nMOS)

td = [3.5(N-1) +2] eτ (CMOS) ( for logical transition 0 to 1) ( or) td = [ 2.5(N-1) + 4] eτ (nMOS)

td = [3.5(N-1) +5] eτ (CMOS) (for logical transition 1 to 0)
3.7.2 Super buffers
Generally the pull-up and the pull down transistors are not equally capable to drive capacitive loads.
This asymmetry is avoided in super buffers. Basically, a super buffer is a symmetric inverting or non
inverting driver that can supply (or) remove large currents and is nearly symmetrical in its ability to drive
capacitive load. It can switch large capacitive loads than an inverter. An inverting type nMOS super
buffer as shown in Figure 3.27.

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Figure 3.27 Super buffers

 Consider a positive going (0 to 1) transition at input V in turns ON the inverter formed by T 1 and
T2.
 With a small delay, the gate of T3 is pulled down to 0 volts. Thus, device T3 is cut off. Since
gate of T4 is connected to Vin, it is turned ON and the output is pulled down very fast.

 For the opposite transition of Vin (1 to 0), Vin drops to 0 volts. The gate of transistor T 3 is
allowed to rise to VDD quickly.
 Simultaneously the low Vin turns off T4 very fast. This makes T3 to conduct with its gate voltage
approximately equal to VDD.
 This gate voltage is twice the average voltage that would appear if the gate was connected to the
source as in the conventional nMOS inverter.
Now as Idsα Vgs , doubling the effective Vgs increases the current and there by reduces the delay in
charging at the load capacitor of the output. The result is more symmetrical transition.

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Figure 3.28 Non-inverting nMOS super buffer

Figure 3.28 shows the non-inverting nMOS super buffer where the structures fabricated in 5µm
technology are capable of driving capacitance of 2pF with a rise time of 5nsec.

3.7.3 BiCMOS drivers

1. In BiCMOS technology we use bipolar transistor drivers as the output stage of inverter and
logic gate circuits.
2. In bipolar transistors, there is an exponential dependence of the collector (output) current on the
base to emitter (input) voltage Vbe .
3. Hence, the bipolar transistors can be operated with much smaller input voltage swings than
MOS transistors and still switch large current.
4. Another consideration in bipolar devices is that the temperature effect on input voltage V be.
5. In bipolar transistor, Vbe is logarithmically dependent on collector current I C and also other
parameters such as base width, doping level, electron mobility.
6. Now, the temperature differences across an IC are not very high. Thus the V be values of the
bipolar devices spread over the chip remain same and do not differ by more than a few milli
volts.

The switching performance of a bipolar transistor driving a capacitive load can be analyzed to begin with
the help of equivalent circuit as shown in Figure 3.29.

Figure 3.29 Equivalent circuit bipolar transistor driving a capacitive load

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The time ∆t required to change the output voltage Vout by an amount equal to the input voltage is

∆t = CL/gm
Where,
CL is the load capacitance

gm is the trans conductance of the bipolar transistor.

The value of ∆t is small because the trans conductance of the bipolar transistors is relatively high. There
are two main components which reveals the delay due to the bipolar transistors are T in and TL .
 Tin is the time required to first charge the base emitter junction of the bipolar (npn) transistor.
This time is typically 2ns for the BiCMOS transistor base driver.
 For the CMOS driver the time required to charge the input gate capacitance is 1ns.
 TL is the time required to charge the output load capacitance .
 The combined effect of Tin and TL is represented as shown in Figure 3.30.

Figure 3.30 Combined effect of Tin and TL

 Delay of BiCMOS inverter can be described by

 Delay for BiCMOS inverter s reduced by a factor of hfe as compared with a CMOS inverter.

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 In Bipolar transistors while considering delay another significant parameter is collector

resistance Rc through which the charging current for CL flows.
 For a high value of RC, there is a long propagation delay through the transistor when charging a
capacitive load.
 Figure 3.31 shows the typical delay values at two values of CL as follows.

Figure 3.31 Typical delay values at two values of CL

The devices thus have high β, high gm, high hfe and low RC. The presence of such efficient and
advantageous devices on chip offers a great deal of scope and freedom to the VLSI designer.
Propagation delays

Propagation delay is the delay in the propagation of the signal created by the change of logical status at
the input to create same change at the output.
(i)Cascaded pass transistors

Figure 3.32 shows a chain of four pass transistors driving a capacitive load C L. All the gates are supplied
by

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Figure 3.32 Chain of four pass transistors

VDD so that a signal can propagate to the output. The lamped RC equivalent circuit is shown in figure,
where each transistor is modeled by a series resistance and capacitance representing the gate-to-channel
capacitance and stray capacitances. Then minimum value of R is the turned ON resistance of each
enhancement mode pass transistor.
The current through the capacitance at the node with voltage V2 is

C (dV2 / dt ) ≈ C.∆V2/ ∆t
The current entering at this node is I1 = (V1 – V2)/R and
the current leaving from this node is I2 = (V2 – V3)/R.
By applying KCL at this node
IC = I1 – I2

C . ∆V2/ ∆t = I1 – I2 = ((V1 – V2)- (V2 – V3)) / R

As the number of sections in the network increases, the circuit parameters become distributed. Assume
that R and C as the resistance per unit length and the capacitance per unit length respectively.

C∆* .∆V2/ ∆t = ∆(∆V2)/R.∆X

Where x is the distance along the network from the input.
RC dv/dt = d/dx. (dv/dx) = d2V/dx2
The propagation time τp from a signal to propagate a distance x is
τ p α X2

By simplifying the analysis if all sheet resistance, gate-to-channel capacitance R S and □cg are lumped
together
R total = nr Rs C total = nc□cg
Where r gives relative resistance per section in terms of RS and c gives relative capacitance per section
In terms of □cg . Then the overall delay for n sections is given by

τp = n2rc(τ)

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It can be shown that the signal delay in a section containing N identical pass transistors driving a matched
load (CL = Cg) is
τp = 0.7 * N(N+1)/2 *RCL

For large value of N, the quantity (N + 1) can be replaced by N. Since the delay increases with N, the
number of pass transistors is restricted to 4. A cascade of more pass transistors will produce a very slow
circuit and the signal needs to be restored by an inverter after every three (or) four pass transsitor.

3.8 WIRING CAPACITANCES

The significant sources of capacitance which contribute to the overall wiring capacitance are as
follows

(i) Fringing fields

Capacitance due to fringing field effects can be a major component of the overall capacitance of
interconnect wires. For fine line metallization, the value of fringing field capacitance (C ff) can be of the
same order as that of the area capacitance. Thus , C ff should be taken into account if accurate prediction
of performance is needed.

Where l = wire length

t = thickness of wire

d = wire to substrate separation.

Then, total wire capacitance

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Cw = Carea + Cff

(ii) Interlayer capacitances

From the definition of capacitance itself, it can be said that there exists a capacitance between the layers
due to parallel plate effects. This capacitance will depend upon the layout i.e., where the layers cross or
whether one layer underlies another etc., by the knowledge of these capacitances, the accuracy of circuit
modeling and delay calculations will be improved. It can be readily calculated for regular structures.

(iii) peripheral capacitance

1. The source and drain p-diffusion regions forms junctions with the n-substrate (or n-well) at well
defined and uniform depths.

2. Similarly, the source and drain n-diffusion regions forms junctions with p-substrate (or p-well)
at well defined and uniform depths.

3. Hence, for diffusion regions, each diode thus formed has associated a peripheral (side wall)
capacitance with it.

4. As a whole the peripheral capacitance,C p will be the order of pF/unit length. So its value will be
greater than Carea of the diffusion region to substrate.

Cp increases with reduction in source or drain area. Total diffusion capacitance is

Cdiff = Carea + Cp

However, as the n and p-active regions are formed by impure implants at the surface of the silicon incase
of orbit processes, they have negligible depth. Hence Cp is quite negligible in them.

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Typical values are given in tabular form

Diffusion capacitance Typical values

5µm 2µm 1.2µm

Area C (C area) 1.0 × 10-4pF/µm2 1.75 × 10-4pF/µm2 3.75 × 10-4pF/µm2

Periphery (Cperiph) 8.0 × 10-4pF/µm2 Negligible (assuming negligible

implanted regions of
negligible depth)

Table 3.1 Typical values of wiring capacticances

3.9 FAN – IN AND FAN-OUT
Fan-in: The number of inputs to a gate is called as fan - in.
Fan-out: The maximum number of similar gates that a gate can drive while remaining within the
guaranteed specifications is called as fan-out.

Effects of Fan-in and Fan-out on propagation delay

 An additional input to a CMOS logic gate requires an additional nMOS and pMOS i.e., two
additional transistors, while incase of other MOS logic gates, it requires one additional
transistor.

 In CMOS logic gates, due to these additional transistors, not only the chip area but also the total
effective capacitance per gate also increased and hence propagation delay increases.

 Some of the increase in propagation delay time can be compensated by the size-scaling method.

 By increasing the size of the device, its current driving capability can be preserved.

 Due to increase in both of inputs and devices size, the capacitance increases, Hence propagation
delay will still increase with fan-in.

 An increase in the number of outputs of a logic gate directly adds to its load capacitances.
Hence, the propagation delay increases with fan-out
3.10 CHOICE OF LAYERS

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The following are the constraints which must be considered for the proper choice of layers.

1. Since the polysilicon layer has relatively high specific resistance (R S), it should not be used for
routing VDD and VSS (GND) except for small distances.
2. VDD and GND (VSS) must be distributed only on metal layers, due to the consideration of Rs
value.
3. The capacitive effects will also impose certain restrictions in the choice of layers as follows
(i) where fast signal lines are required, and in relation to signals on wiring which has relatively
higher values of RS.
(ii) The diffusion areas have higher values of capacitance to substrate and are harder to drive.
4. Over small equipotential regions, the signal on a wire can be treated as being identical at all
points.
5. Within each region the propagation delay of the signal will comparably smaller than the gate
delays and signal delays caused in a system connected by wires.

Thus the wires in a MOS system can be modeled as simple capacitors. This concept leads to the
establishment of electrical rules (guidelines) for communication paths(wires) as given in Table 3.2.

Layer Maximum length of communication wire

Lambda based µm based (2µm) µm – based(1.2µm)

5µm
Metal Chip wide Chip wide Chip wide

Silicide 2,000λ NA NA

Polysilicon 200λ 400µm 250µm

Diffusion (active) 20λ 100µm 60µm

Table 3.2 Guidelines for communication paths

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UNIT IV DATAPATH SUBSYSTEMS & ARRAY

SUBSYSTEMS

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4.1 DATA PATH SUBSYSTEM

4.1.1 Subsystem design
Most digital functions can be divided into the following categories:
 Datapath operators
 Memory elements
 Control structures
 Special-purpose cells

CMOS system design consists of partitioning the system into subsystems of the
types listed above. Many options exist that make trade-offs between speed, den- sity,
programmability, ease of design, and other variables. This chapter addresses design
options for common datapath operators. The next chapter addresses arrays, especially
those used for memory. Control structures are most commonly coded in a hardware
description language and synthesized. Datapath operators benefit from the structured
design principles of hierarchy, regularity, modularity, and locality. They may use N
identical circuits to process N-bit data. Related data operators are placed physically
adjacent to each other to reduce wire length and delay. Generally, data is arranged to
flow in one direction, while control signals are introduced in a direction orthogonal to the
dataflow.Common datapath operators considered in this chapter include adders, one/zero
detectors, comparators, counters, shifters, ALUs, and multipliers.

4.1.2 Shifters
Consider a direct MOS switch implementation of a 4X4 crossbar switch as shown in
Figure 4.1.The arrangement is quit general and may be readily expanded to

Figure 4.1 4 x 4 crossbar switch.

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accommodate n-bit inputs/outputs. In fact, this arrangement is an overkill in that any

input line can be connected to any or all output lines-if all switches are closed, then all inputs
are connected to all outputs in one glorious short circuit. Furthermore, 16 control signals
(sw00)-sw15, one for each transistor switch, must be provided to drive the crossbar switch,
and such complexity is highly undesirable. An adaption of this arrangement) Recognizes the
fact that we can couple the switch gates together in groups of four (in this case) and also form
four separate groups corresponding to shifts of zero, one, two, and three bits. The
arrangement is readily adapted so that the inlines also run horizontally (to confirm the
required strategy). The resulting arrangement is known as barrel shifter and a 4X4-bit barrel
shifter circuit diagram is given in Figure 4.2. The interbus switches have their gate inputs
connected in staircase fashion in group of four and there are now four shift control inputs
which must be mutually exclusive in active state. CMOS transmission gates may be used in
place of the simple pass transistor switches if appropriate

Figure 4.2 Barrel shifter

4.1.3 Adders
Addition is one of the basic operation perform in various processing like counting,
multiplication and filtering. Adders can be implemented in various forms to suit different
speed and density requirements. The truth table of a binary full adder is shown in Table
4.1, along with some functions that will be of use during the discussion of adders. Adder

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inputs: A, B

Table 4.1 Full adder truth table

Carry input: SUM

Carry output: CARRY
Generate signal: G(A • B); occurs when CARRY is internally generated within adder
Propagate signal: P (A + B); when it is 1, C is passed to CARRY.
In some adders A ⊕ B is used as the P term because it may be reused to generate the sum
term.

4.1.3.1 Single-bit adders

Probably the simplest approach to designing an adder is to implement gates to
yield the required majority logic functions.
From the truth table these are:

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The direct implementation of the above equations is shown in Figure 4.3.Using the gate
schematic and the transistors is shown in Figure 4.4.

Figure 4.3 Logic gate implementation of 1-Bit adder

Figure 4.4 Transistor implementation of 1-Bit adder

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The full adder employs 32 transistors (6 for the inverters, 10 for the carry circuit, and 16
for the 3-input XOR). A more compact design is based on the observation that S can be
factored to reuse the CARRY term as follows:

Such a design is shown at the transistor levels in Figure 4.5 and uses only 28 transistors.
Note that the pMOS network is complement to the nMOS network.
Here Cin=C

Figure 4.4 Transistor implementation of 1-Bit adder

4.1.3.2 N-bit parallel adder or ripple carry adder

A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascaded, with the carry
output from each full adder connected to the carry input of the next full adder in the
chain. Figure 4.5 shows the interconnection of four full adder (FA) circuits to provide a 4-bit
ripple carry adder. Notice from Figure 4.5 that the input is from the right side because the
first cell traditionally represents the least significant bit (LSB). Bits a0 and b0 in the figure
represent the least significant bits of the numbers to be added. The sum output is
represented by the bits S0-S3.

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Figure 4.5 4-bit ripple carry adder

4.1.3.3 Carry lookahead adder (CLA)

The carry lookahead adder (CLA) solves the carry delay problem by calculating
the carry signals in advance, based on the input signals. It is based on the fact that a carry
signal will be generated in two cases: (1) when both bits ai and bi are 1, or when one of
the two bits is 1 and the carry-in is 1 . Thus, one can write,

ci+1 = ai.bi + (ai ⊕ bi).ci

si = (ai ⊕ bi) ⊕ ci

The above two equations can be written in terms of two new signals Pi and Gi, which are
shown in Figure 4.6.

Figure 4.6 Full adder stage at i with Pi and Gi

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ci+1 = Gi + Pi.ci
si = Pi ⊕ ci

Where,
Gi = ai.bi
Pi = (ai ⊕ bi)

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Pi and Gi are called carry propagate and carry generate terms, respectively. Notice that
the generate and propagate terms only depend on the input bits and thus will be valid
after one and two gate delay, respectively. If one uses the above expression to calculate
the carry signals, one does not need to wait for the carry to ripple through all the
previous stages to find its proper value. Let’s apply this to a 4-bit adder to make it clear.
Putting i = 0, 1, 2, 3 in ci+1 = Gi + Pi.ci we get

c1 = G0 + P0.c0
c2 = G1 + P1.G0 + P1.P0.c0
c3 = G2 + P2.G1 + P2.P1.G0 + P2.P1.P0.c0
c4 = G3 + P3.G2 + P3.P2.G1 + P3..P2.P1.G0 + P3.P2.P1.P0.c0

Notice that the carry-out bit, ci+1, of the last stage will be available after four delays: two
gate delays to calculate the propagate signals and two delays as a result of the gates
required to implement Equation c4.
Figure 4.7 shows that a 4-bit CLA is built using gates to generate the Pi and Gi and
signals and a logic block to generate the carry out signals according to Equations c1 to c4.

Figure 4.7 Bit carry look-ahead adder implementation

Logic gate and transistor level implementation of carry bits are shown in Figure 4.8
The disadvantage of CLA is that the carry logic block gets very complicated for more
than 4-bits. For that reason, CLAs are usually implemented as 4-bit modules and are used
in a hierarchical structure to realize adders that have multiples of 4-bits.

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Figure 4.8 Carry structures of CLA

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4.1.3.4 Manchester carry chain

This implementation can be very performant (20 transistors) depending on the way
the XOR function is built. The carry propagation of the carry is controlled by the output
of the XOR gate. The generation of the carry is directly made by the function at the
bottom. When both input signals are 1, then the inverse output carry is 0. In the
schematic of Figure 4.9, the carry passes through a complete

Figure 4.9 An adder element based on the pass/generate concept

transmission gate. If the carry path is precharged to VDD, the transmission gate is then
reduced to a simple NMOS transistor. In the same way the PMOS transistors of the carry
generation is removed. One gets a Manchester cell as shown in the Figure 4.10.
Figure 4.10 Manchester cell

The Manchester cell is very fast, but a large set of such cascaded cells would be slow.

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This is due to the distributed RC effect and the body effect makin/g the propagation time
grow with the square of the number of cells. Practically, an inverter is added every four

cells, like in Figure 4.11

Figure 4.11 Cascaded Manchester carry-chain elements with buffering

4.1.4 Multipliers
In many digital signal processing operations - such as correlations, convolution,
filtering, and frequency analysis - one needs to perform multiplication. The most basic
form of multiplication consists of forming the product of two positive binary numbers.
This may be accomplished through the traditional technique of successive additions and
shifts, in which each addition is conditional on one of the multiplier bits. Here is an
example of 4-bit multiplication given in the Figure 4.12.

Figure 4.12 4-bit multiplication

The multiplication process may be viewed to consist of the following two steps:

1. Evaluation of partial products.

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2. Accumulation of the shifted partial products.

It should be noted that binary multiplication is equivalent to a logical AND op- eration.
Thus evaluation of partial products consists of the logical ANDing of the multiplicand
and the relevant multiplier bit. Each column of partial products must then be added and,
if necessary, any carry values passed to the next column.
There are a number of techniques that may be used to perform multiplication. In general,
the choice is based on factors such as speed, throughput, numerical accuracy, and area.
As a rule, multipliers may be classified by the format in which data words are accessed,
namely:-
1. Serial form
2. serial/parallel form
3. Parallel form

4.1.4.1 Array multiplication

A parallel multiplier is based on the observation that partial products in the multi-
plication process may be independently computed in parallel. For example, consider the
unsigned binary integers X and Y.

The product is found by

P=X×Y
For 4-bit numbers, the expression above may be expanded as in the table 4.2.

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Table 4.2 4-Bit multiplication

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An nxn multiplier requires

(n − 1)2full adders,
n − 1 half adders, and
n2 AND gates.

The worst-case delay associated with such a multiplier is (2n + l)tg, where tg is the worst-case
adder delay.
Cell shown in Figure 4.13 is a cell that may be used to construct a parallel multiplier.

Figure 4.13 Basic cell to construct a parallel multiplier

The Xi term is propagated diagonally from top right to bottom left, while the yj term is
propagated horizontally. Incoming partial products enter at the top. Incoming CARRY IN
values enter at the top right of the cell. The bit-wise AND is performed in the cell, and
the SUM is passed to the next cell below. The CARRY 0UT is passed to the bottom left
of the cell.
Figure 4.14 depicts the multiplier array with the partial products enumerated. The
Multiplier can be drawn as a square array, as shown here, Figure is the most convenient
for implementation. In this version the degeneration of the first two rows of the multiplier
are shown. The first row of the multiplier adders has been replaced with AND gates
while the second row employs half-adders rather than full adders. This optimization
might not be done if a completely regular multiplier were required (i.e. one array cell). In

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this case the appropriate inputs to the first and second row would be connected to ground,
as shown in the previous slide. An adder with equal carry and sum propagation times is
advantageous, because the worst-case multiply time depends on both paths.

Figure 4.14 Array multiplier

4.1.4.2 Wallace tree multiplication
If the truth table for an adder, is examined, it may be seen that an adder is in effect
a “one’s counter” that counts the number of l’s on the A, B, and C inputs and encodes
them on the SUM and CARRY outputs. A l-bit adder provides a 3:2 (3 inputs, 2 outputs)
compression in the number of bits. The addition of partial products in a column of an
array multiplier may be thought of as totaling up the number of l’s in that column, with
any carry being passed to the next column to the left as shown in Table 4.3.

Table 4.3 Wallace tree multiplication

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Figure 4.15 Most convenient way for implementation of array multiplier

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Example for implementation of 4x4 multiplier(4-bit) using Wallace Tree Multi- plication
methods is given in Figure 4.16
Figure 4.16 Product terms

Considering the product P3, it may be seen that it requires the summation of four partial
products and a possible column carry from the summation of P2 as shown in Figure 4.17
Figure 4.17 Wallace Tree Multiplication for 4-bits

Example for implementation of 6X6 multiplier(4-bit) using Wallace Tree Multiplication

methods Figure 4.18.

Consider the 6 x 6 multiplication table. Considering the product P5, it may be seen that it
requires the summation of six partial products and a possible column carry from the
summation of P4. Here we can see the adders required in a multiplier based on this style
of addition.
The adders have been arranged vertically into ranks that indicate the time at which the adder
output becomes available. While this small example shows the general Wallace addition
technique, it does not show the real speed advantage of a Wallace tree. There is an
identifiable “array part”, and a CPA part, which is at the top right. While this has been
shown as a ripple-carry adder, any fast CPA
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Figure 4.19 Product terms

Figure 4.20 Wallace Tree Multiplication for 6-bits

can be used here. The delay through the array addition (not including the CPA) is
proportional to log1.5(n), where n is the width of the Wallace tree. Wallace Tree
Multiplication for 6-bits is shown in Figure 4.20.

4.1.5 Parity generator

Parity is a very useful tool in information processing in digital computers to indicate any

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presence of error in bit information. External noise and loss of signal strength cause loss
of data bit information while transporting data from one device to other device,
located inside the computer or externally. To indicate any occurrence of error, an extra bit
is included with the message according to the total number of 1s in a set of data, which is
called parity. If the extra bit is considered 0 if the total number of 1s is even and 1 for odd
quantities of 1s in a set of data, then it is called even parity.
On the other hand, if the extra bit is 1 for even quantities of 1s and 0 for an odd
number of 1s, then it is called odd parity. A parity generator is a combination logic
system to generate the parity bit at the transmitting side. Table 4.4 shows the Truth table
for generating even and odd parity bit

Four bit message Even parity Odd parity

D3D2D1D0
0000 0 1
0001 1 0
0010 1 0
0011 0 1
01000 1 0
0101 0 1
0110 0 1
0111 1 0
1000 1 0
1001 0 1
1010 0 1
1011 1 0
1100 0 1
1101 1 0
1110 1 0
1111 0 1

Table 4.4 Truth table for generating even and odd parity bit

If the message bit combination is designated as, D3D2D1D0 and Pe, Po are the even and
odd parity respectively, then it is obvious from the table that the Boolean expressions of
even parity and odd parity are

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Pe=D3D2D1D0

Po =(D3D2D1D0)

The above illustration is given for a message with four bits of information. However, the
logic diagrams can be expanded with more XOR gates for any number of bits. Figure 4.21
shows the Even parity generator using logic gates. Figure 4.22 shows the Odd parity
generator logic gates

Figure 4.21 Even parity generator using logic gates

Figure 4.22 Odd parity generator logic gates

4.1.6 Zero/one detector

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Detecting all ones or zeros on wide N-bit words requires large fan-in AND or NOR
gates. Recall that by DeMorgan’s law, AND, OR, NAND, and NOR are funda- mentally the
same operation except for possible inversions of the inputs and/or outputs. You can build a
tree of AND gates, as shown in Figure 4.23. Here, alternate NAND and NOR gates have
been used. The path has log N stages.
Figure 4.23 One/zero detectors (a) All one detector (b) All zero detector (c) All zero detector

transistor level representation

4.1.7 Comparators
Another common and very useful combinational logic circuit is that of the Digital
Comparator circuit. Digital or Binary Comparators are made up from standard AND,
NOR and NOT gates that compare the digital signals present at their input terminals and
produce an output depending upon the condition of those inputs.
For example, along with being able to add and subtract binary numbers we need to be
able to compare them and determine whether the value of input A is greater than, smaller
than or equal to the value at input B etc. The digital comparator accomplishes this using
several logic gates that operate on the principles of Boolean Algebra. There are two main
types of Digital Comparator available and these are.
Identity Comparator: An Identity Comparator is a digital comparator that has only one output
terminal for when A = B either “HIGH” A = B = 1or “LOW” A = B = 0
Magnitude Comparator: A Magnitude Comparator is a type of digital com- parator that

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has three output terminals, one each for equality, A = B greater than,A > B and less than
A<B
The purpose of a Digital Comparator is to compare a set of variables or unknown numbers,
for example A (A1, A2, A3, An, etc) against that of a constant or unknown value such as B
(B1, B2, B3 Bn, etc) and produce an output condition or flag depending upon the result of
the comparison. For example, a magnitude comparator of two 1-bits, (A and B) inputs would
produce the following three output conditions when compared to each other.

A > B, A + B, A < B

Which means: A is greater than B, A is equal to B, and A is less than B

This is useful if we want to compare two variables and want to produce an output when
any of the above three conditions are achieved. For example, produce an output from a
counter when a certain count number is reached. Consider the simple 1-bit comparator
below.
Then the operation of a 1-bit digital comparator is given in the following Truth Table 4.4.

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Inputs Outputs
B A A>B A=B A<B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 0 0

Table 4.4 Truth table of 1-bit digital comparator

From the above table the obtained expressions for magnitude comparator using K-map are
as follows

The logic diagram of 1-bit comparator using basic gates is shown below in Figure 4.24.

Figure 4.24 1-bit Digital Comparator

*** Draw separate diagrams for greater, equality and less than expressions.

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4.1.8 Counters
Counters can be implemented using the adder/subtractor circuits and registers (or
equivalently, D flip- flops).The simplest counter circuits can be built using T flip-flops
because the tog- gle feature is naturally suited for the implementation of the counting
operation.

Counters are available in two categories

 Asynchronous(Ripple counters): Asynchronous counters, also known as
ripple counters, are not clocked by a common pulse and hence every flip-flop in
the counter changes at different times. The flip-flops in an asynchronous
counter is usually clocked by the output pulse of the preceding flip-flop. The
first flip-flop is clocked by an external event. The flip-flop output transition
serves as a source for triggering other flip-flops i.e the C input (clock input) of
some or all flip-flops are triggered NOT by the common clock pulses. Eg:-
Binary ripple counters, BCD ripple counters
 Synchronous counters: A synchronous counter however, has an internal clock,
and the external event is used to produce a pulse which is synchronized with
this internal clock.
C input (clock input) of all flip-flops receive the common clock pulses.
E.g.:- Binary counter, Up-down Binary counter, BCD Binary counter, Ring counter,
Johnson counter,

4.1.8.1 Asynchronous up-counter with t flip-flops

Figure 4.9.1 shows a 3-bit counter capable of counting from 0 to 7. The clock
inputs of the three flip-flops are connected in cascade. The T input of each flip- flop is
connected to a constant 1, which means that the state of the flip-flop will be toggled
at each active edge (here, it is positive edge) of its clock. We assume that the purpose
of this circuit is to count the number of pulses that occur on the primary input called
Clock. Thus the clock input of the first flip-flop is connected to the Clock line. The

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other two flip-flops have their clock inputs driven by the Q output of the preceding flip-
flop. Therefore, they toggle their states whenever the preceding flip-flop changes its state
from Q = 1 to Q = 0, which results in a positive edge of the Q signal.
Note here the value of the count is the indicated by the 3-bit binary number
Q2Q1Q0. Since the second flip-flop is clocked by Q0 , the value of Q1 changes shortly
after the change of the Q0 signal. Similarly, the value of Q2 changes shortly after the
change of the Q1 signal. This circuit is a modulo-8 counter. Because it counts in the
upward direction, we call it an up-counter. This behavior is similar to the rippling of
carries in a ripple-carry adder. The circuit is therefore called an asynchronous counter, or
a ripple counter.

Figure 4.25 A 3-bit up-counter.

4.1.8.2 Asynchronous down-counter with T flip-flops

Some modifications of the circuit in Figure 4.25 lead to a down-counter which
counts in the sequence 0, 7, 6, 5, 4, 3, 2, 1, 0, 7, and so on. The modified circuit is
shown in Figure 4.26. Here the clock inputs of the second and third flip-flops are
driven by the Q outputs of the preceding stages, rather than by the Q outputs.

Figure 4.26 A 3-bit down-counter.

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Although the asynchronous counter is easier to construct, it has some major

disadvantages over the synchronous counter. First of all, the asynchronous counter is
slow. In a synchronous counter, all the flip-flops will change states simultaneously
while for an asynchronous counter, the propagation delays of the flip-flops add
together to produce the overall delay. Hence, the more bits or number of flip-flops in
an asynchronous counter, the slower it will be.
Secondly, there are certain ”risks” when using an asynchronous counter. In a
complex system, many state changes occur on each clock edge and some ICs respond
faster than others. If an external event is allowed to affect a system whenever it occurs
(unsynchronized), there is a small chance that it will occur near a clock transition,
after some IC’s have responded, but before others have. This intermingling of
transitions often causes erroneous operations. And the worse this is that these
problems are difficult to foresee and test for because of the random time difference
between the events.

4.1.8.3 Synchronous counters

A synchronous counter usually consists of two parts: the memory element and
the combinational element. The memory element is implemented using flip-flops
while the combinational element can be implemented in a number of ways. Using
logic gates is the traditional method of implementing combinational logic and has
been applied for decades.

4.1.8.4 Synchronous up-counter with T flip-flops

An example of a 4-bit synchronous up-counter is shown in Figure 4.27.

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Figure 4.27 A 4bit synchronous upcounter

Table 4.5 Contents of a 4bit upcounter for 16 consecutive clock cycles

Observing the pattern of bits in each row of the Table 4.5, it is apparent that bit Q0
changes on each clock cycle. Bit QQ1 changes only when Q0 = 1. Bit Q2 changes only
when both Q1 and Q0 are equal to 1. Bit Q3 changes only when Q2 = Q1 = Q0 = 1. In
general, for an n-bit up-counter, a give flip-flop changes its state only when all the
preceding flip-flops are in the state Q = 1. Therefore, if we use T flip-flops to realize
the 4-bit counter, then the T inputs should be defined as

T0 = 1
T1 = Q0
T2 = Q0Q1
T3 = Q0Q1Q2

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In Figure 4.28, instead of using AND gates of increased size for each stage, we use a
factored arrangement. This arrangement does not slow down the response of the
counter, because all flip-flops change their states after a propagation delay from the
positive edge of the clock. Note that a change in the value of Q0 may have to
propagate through several AND gates to reach the flip-flops in the higher stages of the
counter, which requires a certain amount of time. This time must not exceed the clock
period. Actually, it must be 3less than the clock period minus the setup time of the
flip-flops. It shows that the circuit behaves as a modulo-16 up-counter. Because all
changes take place with the same delay after the active edge of the Clock signal, the
circuit is called a synchronous counter.

Figure 4.28 Design of synchronous counter using adders and registers

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4.2 ARRAY SUBSYSTEMS

Semiconductor based electronics is the foundation to the information technology society
we live in today. Ever since the first transistor was invented way back in 1948, the
semiconductor industry has been growing at a tremendous pace. Semiconductor memories and
microprocessors are two major fields, which are benefited by the growth in semiconductor
technology.

Figure 4.29 Increasing memory capacity over the years

The technological advancement has improved performance as well as packing density of these
devices over the years Gordon Moore made his famous observation in 1965, just four years
after the first planar integrated circuit was discovered. He observed an exponential growth in
the number of transistors per integrated circuit in which the number of transistors nearly
doubled every couple of years as shown in Figure 4.29. This observation, popularly known as

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Moore's Law, has been maintained and still holds true today. Keeping up with this law, the
semiconductor memory capacity also increases by a factor of two every year.
4.2.1 Memory Classification

Size: Depending upon the level of abstraction, different means are used to express the size of
the memory unit. A circuit designer usually expresses memory in terms of bits, which are
equivalent to the number of individual cells need to store the data. Going up one level in the
hierarchy to the chip design level, it is common to express memory in terms of bytes, which is
a group of 8 bits. And on a system level, it can be expressed in terms of words or pages, which
are in turn collection of bytes.
Function: Semiconductor memories are most often classified on the basis of access patterns,
memory functionality and the nature of the storage mechanism. Based on the access patterns,
they can be classified into random access and serial access memories. A random access
memory can be accessed for read/write in a random fashion. On the other hand, in serial access
memories, the data can be accessed only in a serial fashion. FIFO (First In First Out) and LIFO
(Last In Last Out) are examples of serial memories. Most of the memories fall under the
random access types. Based on their functionalities, memory can be broadly classified into
Read/Write memories and Read-only memories.
As the name suggests, Read/Write memory offers both read and write operations and
hence is more flexible. SRAM (Static RAM) and DRAM (Dynamic RAM) come under this
category. A Read-only memory on the other hand encodes the information into the circuit
topology. Since the topology is hardwired, the data cannot be modified; it can only be read.
However, ROM structures belong to the class of the nonvolatile memories.
Removal of the supply voltage does not result in a loss of the stored data. Examples of such
structures include PROMs, ROMs and PLDs. The most recent entry in the filed are memory
modules that can be classified as nonvolatile, yet offer both read and write functionality.
Typically, their write operation takes substantially longer time than the read operation. An
EPROM, EEPROM and Flash memory fall under this category. Figure 4.30 Classification of
memories

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Figure 4.30 Classification of memories

Timing Parameters: The timing properties of a memory are illustrated in Figure 4.31. The time
it takes to retrieve data from the memory is called the read- access time. This is equal to the
delay between the read request and the moment the data is available at the output. Similarly,
write-access time is the time elapsed between a write request and the final writing of the input
data into the memory. Finally, there is another important parameter, which is the cycle time
(read or write), which is the minimum time required between two successive read or write
cycles. This time is normally greater than the access time.
Figure 4.30 Timing properties of a memory

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4.2.2 Memory Architecture and Building Blocks

The straightforward way of implementing a N-word memory is to stack the words in a
linear fashion and select one word at a time for reading or writing operation by means of a
select bit. Only one such select signal can be high at a time. Though this approach as shown in
Figure 4.31 is quite simple, one runs into a number of problems when trying to use it for larger
memories. The number of interface pins in the memory module varies linearly with the size of
the memory and this can easily run into huge values.

Figure 4.31 Basic Memory Organization

To overcome this problem, the address provided to the memory module is generally encoded
as shown in Figure 4.32. A decoder is used internally to decode this address and make the
appropriate select line high. With 'k' address pins, 2K number of select pins can be driven and
hence the number of interface pins will get reduced by a factor of log2N.

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Figure 4.32 Memory with decoder logic

Though this approach resolves the select problem, it does not address the issues of the memory
aspect ratio. For an N-word memory, with a word length of M, the aspect ratio will be nearly
N:M, which is very difficult to implement for large values of N. Also such sort of a design
slows down the circuit very much.
This is because, the vertical wires connecting the storage cells to the inputs/outputs become
excessively long. To address this problem, memory arrays are organized so that the vertical
and horizontal dimensions are of the same order of magnitude, making the aspect ratio close to
unity. To route the correct word to the input/output terminals, an extra circuit called column
decoder is needed as shown in the Figure 4.33.
The address word is partitioned into column address (A0 to AK-1) and row address (AK-1 to
AL-1). The row address enables one row of the memory for read/write, while the column
address picks one particular word from the selected row.

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Figure 4.34 Memory with row and column decoders

4.2.3 Static and Dynamic RAMs

RAMs are of two types, static and dynamic. Circuits similar to basic D flip-flop are used
to construct static RAMs (SRAMs) internally. A typical SRAM cell consists of six transistors
which are connected in such a way as to form a regenerative feedback. In contrast to DRAM,
the information stored is stable and does not require clocking or refresh cycles to sustain it.
Compared to DRAMs, SRAMs are much faster having typical access times in the order of a
few nanoseconds. Hence SRAMs are used as level 2 cache memory.
Dynamic RAMs do not use flip-flops, but instead are an array of cells, each containing a
transistor and a tiny capacitor. '0's and '1's can be stored by charging or discharging the
capacitors. The electric charge tends to leak out and hence each bit in a DRAM must be
refreshed every few milliseconds to prevent loss of data. This requires external logic to take
care of refreshing which makes interfacing of DRAMs more complex than SRAMs. This

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disadvantage is compensated by their larger capacities. A high packing density is achieved

since DRAMs require only one transistor and one capacitor per bit. This makes them ideal to
build main memories. But DRAMs are slower having delays in the order tens of nanoseconds.
Thus the combination of static RAM cache and a dynamic RAM main memory attempts to
combine the good properties of each.

4.2.3.1 SRAM Basics

The memory circuit is said to be static if the stored data can be retained indefinitely, as
long as the power supply is on, without any need for periodic refresh operation. The data
storage cell, i.e., the one-bit memory cell in the static RAM arrays, invariably consists of a
simple latch circuit with two stable operating points.
Depending on the preserved state of the two inverter latch circuit, the data being held in
the memory cell will be interpreted either as logic '0' or as logic '1'. To access the data
contained in the memory cell via a bit line, we need atleast one switch, which is controlled by
the corresponding word line as shown in Figure 4.35.

Figure 4.35 SRAM Cell

CMOS SRAM Cell

A low power SRAM cell may be designed by using cross-coupled CMOS inverters. The
most important advantage of this circuit topology is that the static power dissipation is very
small; essentially, it is limited by small leakage current. Other advantages of this design are
high noise immunity due to larger noise margins, and the ability to operate at lower power
supply voltage. The major disadvantage of this topology is larger cell size. The circuit
structure of the full CMOS static RAM cell is shown in Figure 4.36 . The memory cell consists
of simple CMOS inverters connected back to back, and two access transistors. The access
transistors are turned on whenever a word line is activated for read or write operation,
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connecting the cell to the complementary bit line columns.

Figure 4.36 Full CMOS SRAM cell

CMOS SRAM Cell Design

To determine W/L ratios of the transistors, a number of design criteria must be taken
into consideration. The two basic requirements, which dictate W/L ratios, are that the data read
operation should not destroy the stored information in the cell. The cell should allow stored
information modification during write operation. In order to consider operations of SRAM,

we have to take into account, the relatively large parasitic column capacitance and
and column pull-up transistors as shown in Figure 4.37 .

Figure 4.37 CMOS SRAM cell with precharge transistors

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When none of the word lines is selected, the pass transistors M3 and M4 are turned off and the
data is retained in all memory cells. The column capacitances are charged by the pull-up
transistors P1 and P2. The voltages across the column capacitors reach VDD - VT.

READ Operation
Consider a data read operation, shown in Figure 28.41, assuming that logic '0' is stored
in the cell. The transistors M2 and M5 are turned off, while the transistors M1 and M6 operate
in linear mode. Thus internal node voltages are V 1 = 0 and V2 = VDD before the cell access
transistors are turned on. The active transistors at the beginning of data read operation are
shown in Figure 4.38.

Figure 4.38 Read Operation

After the pass transistors M3 and M4 are turned on by the row selection circuitry, the voltage
CBb of will not change any significant variation since no current flows through M4. On the
other hand M1 and M3 will conduct a nonzero current and the voltage level of C B will begin to
drop slightly. The node voltage V1 will increase from its initial value of '0'V. The node voltage
V1 may exceed the threshold voltage of M2 during this process, forcing an unintended change
of the stored state. Therefore voltage must not exceed the threshold voltage of M2, so the
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transistor M2 remains turned off during read phase, i.e.,

(Eq 1)
The transistor M3 is in saturation whereas M1 is linear, equating the current equations we get

(Eq 2)
Substituting Eq 1 in Eq.2 we get

(Eq .3)

WRITE Operation
Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell
initially. Figure 4.39 shows the voltage levels in the CMOS SRAM cell at the beginning of the
data write operation. The transistors M1 and M6 are turned off, while M2 and M5 are
operating in the linear mode. Thus the internal node voltage V 1 = VDD and V2 = 0 before the
access transistors are turned on. The column voltage V b is forced to '0' by the write circuitry.
Once M3 and M4 are turned on, we expect the nodal voltage V 2 to remain below the threshold
voltage of M1, since M2 and M4 are designed according to Eq. 1.

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Figure 4.39 SRAM start of write '0'

The voltage at node 2 would not be sufficient to turn on M1. To change the stored information,
i.e., to force V1 = 0 and V2 = VDD, the node voltage V1 must be reduced below the threshold

voltage of M2, so that M2 turns off. When the transistor M3 operates in linear
region while M5 operates in saturation region. Equating their current equations we get

(Eq 4)
Rearranging the condition of in the result we get

(Eq 5)

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WRITE Circuit
The principle of write circuit is to assert voltage of one of the columns to a low level. This

can be achieved by connecting either BIT or to ground through transistor M3 and

either of M2 or M1. The transistor M3 is driven by the column decoder selecting the specified

column. The transistor M1 is on only in the presence of the write enable signal and
when the data bit to be written is '0'. The transistor M2 is on only in the presence of the write

signal and when the data bit to be written is '1'. The circuit for write operation is
shown in Figure 4.40

Figure 4.41 Circuit for write operation

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4.2.3.2 DRAM Basics

A typical 1-bit DRAM cell is shown in Figure 4.42

Figure 4.42 DRAM Cell

The C S capacitor stores the charge for the cell. Transistor M1 gives the R/W access to
the cell. CB is the capacitance of the bit line per unit length.
Memory cells are etched onto a silicon wafer in an array of columns (bit lines) and
rows (word lines). The intersection of a bit line and word line constitutes the address of the
memory cell.
DRAM works by sending a charge through the appropriate column (CAS) to activate the
transistor at each bit in the column. When writing, the row lines contain the state the capacitor
should take on.
When reading, the sense amplifier determines the level of charge in the capacitor. If it is
more than 50%, it reads it as "1”; otherwise it reads it as "0". The counter tracks the refresh
sequence based on which rows have been accessed in what order. The length of time necessary
to do all this is so short that it is expressed in nanoseconds (billionths of a second). e.g. a
memory chip rating of 70ns means that it takes 70 nanoseconds to completely read and
recharge each cell.
The capacitor in a dynamic RAM memory cell is like a leaky bucket. Dynamic RAM
has to be dynamically refreshed all of the time or it forgets what it is holding. This refreshing
takes time and slows down the memory.
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4.2.4 ROM (Read Only Memory)

Based on the programmability of the devices non-volatile memories are categorized as
follows. Writing data into ROMs is possible only at the time of manufacturing the devices and
used only for reading the data stored. Even though these devices are less in cost the constraint
that they are to be programmed at the time of manufacturing is an inconvenience. PROM
devices are one time programmable ROM. At the time of device manufacturing every cell is
stored with "1" and can be programmed by customer once. But, single write phase makes them
unattractive. For instance, a single error in the programming process or application makes the
device unusable.
EPROM is Erasable PROM. Multiple times programming feature is added in EPROM.
In this case, first whole memory is to be erased by shining ultraviolet light. The erase process
is slow and can take from seconds to several minutes, depending on the intensity of the UV
source. Programming takes several (5-10) /word. EPROM cell is extremely simple and
dense, making it possible to fabricate large memories at a low cost. EPROMs were therefore
attractive in applications that not require frequent programming. Electrically-Erasable PROM
(EEPROM) can be erased without removing from board, unlike in UV erasable where memory
must be removed from the board. The voltage approximately applied for programming is 18V.
In addition, it is a reverse process; means by applying high negative voltage at gate can
erase the cell. Another advantage over EPROM is that EEPROM can be programmed for
105cycles. Flash Electrically Erasable PROM Technically the Flash EEPROM is a
combination of the EPROM and EEPROM approaches. The main difference is that erasure can
be performed for the complete chip, or for a sub-section of the memory. The control circuits
on the memory chip can be regularly checked for the value of the threshold during erasure, and
the erasure time can be adjusted dynamically. Flash technology has three basic weaknesses.
First, its bulk erase nature prevents the use of normal byte-oriented update. Second, Based on
the architecture used write and erase operations take different time and consume more power
than read. Finally, each flash-memory block has a limitation on the erase cycle count.
Although transistors are used for realization of Read Only Memory, the functioning of
Rom can be easily understood by diode matrix network depicted in Figure 4.43. In this

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network, whichever switch is closed, those diodes will conduct and the output will be high
(logic 1), sections where there is no diode connected there will be no current flowing and the
output will be low (logic 0). For instance, when switch S5 is closed, the diodes D6 and D7 are
on and therefore both output 1 and output 3 are at logic 1 and both output 2 and output 4 are at
logic 0.
Hence the corresponding binary number is 0101 and its decimal value is 5.The disadvantage of
a diode cell is that it does not isolate the bit line from the word line. For better isolation the
diode can be replaced by gate-source connection of a NMOS transistor.
Moreover, in order to achieve the programmability i.e. for multiple read write
capability a modified transistor known as Floating Gate (FG) Transistor is employed. The
structure is similar to a traditional MOS device, except that an extra gate is inserted between
gate and channel. The threshold voltage of the FG is programmable and corresponding to its
different values the level 0 and level 1 can be identified.

Figure 4.43 Diode matrix

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UNIT V PROGRAMMABLE LOGIC DEVICES &

CMOS TESTING

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5.1 PROGRAMMABLE LOGIC DEVICES

5.1.1 Introduction The need of programmable devices was realized in early 70s itself with the
design of PLD by Ron Cline from Signetics . The digital ICs like TTL or CMOS have fixed
functionality and the user has no option to change or modify their functionality .i.e they work
according to the design given by the manufacturer. So,to change this people started thinking of a
methodology by which the functionality of an IC can be modified or changed. Then the concept of
using Fuses in ICs entered and gained momentum. This method of changing or modifying the
functionality of an IC using the Fuses was appreciated and this method of blowing a Fuse between
two contacts or keeping the Fuse intact was done by using a software and hence these devices
were called Programmable Logic Devices(PLDs). Many digital chips were considered under the
category of PLDs .But the most fundamental and primitive was the Memories like ROM or PROM
etc.
The realization of Digital circuits by PLDs can be classified as shown in the diagram below.

PLAs were introduced in the early 1970s, by Philips, but their main drawbacks were that they were
expensive to manufacture and offered somewhat poor speed-performance. Both disadvantages were
due to the two levels of configurable logic, because programmable logic planes were difficult to
manufacture and introduced significant propagation delays. To overcome these problems ,
Programmable Array Logic (PAL) devices were developed.
Memory : Memory is used to store, provide access to, and allow modification of data and program
code for use within a processor-based electronic circuit or system. The two basic types of memory

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are ROM (read-only memory) and RAM (random access memory).

ROM is used for holding program code that must be retained when the memory power is
removed. It is considered to provide nonvolatile storage. The code can either be fixed when the
memory is fabricated (mask programmable ROM) or electrically programmed once (PROM,
Programmable ROM) or multiple times. Multiple programming capacity requires the ability to
erase prior programming, which is available with EPROM (electrically programmable ROM,
erased using ultraviolet [UV] light), EEPROM or EEPROM (electrically erasable PROM), or flash
(also electrically erased). PROM is sometimes considered to be in the same category of circuit as
programmable logic, although in this text, PROM is considered in the memory category only.
RAM is used for holding data and program code that require fast access and the ability to modify
the contents during normal operation. RAM differs from read-only memory (ROM) in that it can be
both read from and written to in the normal circuit application. However, flash memory can also be
referred to as nonvolatile RAM (NVRAM). RAM is considered to provide a volatile storage,
because unlike ROM, the contents of RAM will be lost when the power is removed. There are two
main types of RAM: static RAM (SRAM) and dynamic RAM (DRAM).
ROM- READ ONLY MEMORY : A ROM is essentially a memory device for storage purpose in
which a fixed set of binary information is stored. The user must first specify the binary information
to be stored and then it is embedded in the unit to form the required interconnection pattern. ROM
contains special internal links that can be fused or broken. Certain links are to be broken or blown
out to realize the desired interconnections for a particular application and to form the required
circuit path. Once a pattern is established for a ROM, it remained fixed even if the power supply to
the circuit is switched off and then switched on again.
The block diagram of ROM is shown below. It consists of n input lines and m-output lines. Each
bit combination of input variables is called an address and each bit combination that is formed at
output lines is called a word. Thus, an address is essentially binary number that denotes one of the
min-terms of n variables and the number of bits per word is equal to the number of output lines m.
It is possible to generate p = 2n number of distinct addresses from n number of input variables.
Since there are 2n distinct addresses in a ROM, there are 2 n distinct words which are said to be
stored in the device and an output word can be selected by a unique address. The address value
applied to the input lines specifies the word at output lines at any given time. A ROM is
characterized by the number of words 2 n and number of bits per word m and denoted as 2n × m

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ROM.
For example a 32 × 8 ROM contains 32 words of 8 bits each. This means there are eight output
lines and there are 32 numbers of distinct words stored in that unit, each of which is applied to the
output lines. The particular word selected from the presently available output lines is determined by
five input variables, as there are five input lines for a 32 × 8 ROM, because 2 5 = 32. Five input
variables can specify 32 addresses or min-terms and for each address input there is a unique
selected word. Thus, if the input address is 0000, word number 0 is selected. For address 0001,
word number 1 is selected and so on.

A ROM is sometimes specified by the total number of bits it contains, which is 2 n × m. For
example, a 4,096-bit ROM may be organized as 512 words of 8 bits each. That means the device
has 9 input lines (29 × m = 512) and 8 output lines.
In Figure below, the block consisting of an AND array with buffers or inverters is equivalent to a
decoder. The decoder basically is a combinational circuit that generates 2n numbers of minterms
from n number of input lines. 2n or p numbers of minterms are realized from n number of input
variables with the help of n numbers of buffers, n numbers of inverters, and 2n numbers of AND
gates.

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Each of the minterms is applied to the inputs of m number of OR gates through fusible links. Thus,
m numbers of output functions can be produced after blowing of some selected fuses. The
equivalent logic diagram of a 2n×m ROM is shown below

ROM has many important applications in the design of digital computer systems. Realization of
complex combinational circuits, code conversions, generating bit patterns, performing arithmetic
functions like multipliers, forming look-up tables for arithmetic functions, and bit patterns for
characters are some of its applications. They are particularly useful for the realization of multiple
output combinational circuits with the same set of inputs. As such, they are used to store fixed bit
patterns that represent the sequence of control variables needed to enable the various operations in
the system. They are also used in association with microprocessors and microcontrollers.
5.1.2 Programmable logic device-(PLD)

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The logic devices other than TTL ,CMOS families whose logical operation is specified by the
user through a process called programming are called Programmable Logic Devices. So, the
programmable logic device is the IC that contain digital logic cells and programmable interconnect
. The idea of PLD was first conceived by Ron Cline from Signetics in 1975 with programmable
AND and OR planes. The basic idea with these devices is to enable the designer to configure the
logic cells and interconnect to form a digital electronic circuit within a single IC package. Here, the
hardware resources will be configured to implement a required functionality. By changing the
hardware configuration, the PLD will operate a different function. The functioning and basic
working principle of PLD is explained below through the diagrams.

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There are three types of PLD available. The simple programmable logic device (SPLD), the
Complex programmable logic device(CPLD), and the Field programmable gate array (FPGA).

Device Type AND Array OR Array

ROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed

Simple Programmable Logic Device (SPLD)

The PLD with simple architectural features can be called as SPLD or Simple programmable
Logic Device. The SPLD was introduced prior to the CPLD and FPGA. Based on the architecture
the SPLDs are classified into three types. Programmable logic array (PLA), Programmable array of
logic (PAL), and Generic Array of Logic (GAL).

5.1.3 PLA-Programmable Logic Array

PLA, Programmable Logic Array is a type of LSI device and conceptually similar to a ROM.
However, a PLA does not contain all AND gates to form the decoder or does not generate all the
minterms like ROM. In the PLA, the decoder is replaced by a group of AND gates with
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buffers/inverters, each of which can be programmed to generate some product terms of input
variable combinations that are essential to realize the output functions. The AND and OR gates
inside the PLA are initially fabricated with the fusible links among them. The required Boolean
functions are implemented in sum of the products form by opening the appropriate links and
retaining the desired connections.
So, the PLA consists of two programmable planes AND and OR planes . The AND plane consists
of programmable interconnect along with AND gates. The OR plane consists of programmable
interconnect along with OR gates. In this view, there are four inputs to the PLA and four outputs
from the PLA. Each of the inputs can be connected to an AND gate with any of the other inputs by
connecting the crossover point of the vertical and horizontal interconnect lines in the AND gate
programmable interconnect. Initially, the crossover points are not electrically connected, but
configuring the PLA will connect particular cross over points together. In this view, the AND gate
is seen with a single line to the input. This view is by convention, but this also means that any of
the inputs (vertical lines) can be connected. Hence, for four PLA inputs, the AND gate also has four
inputs. The single output from each of the AND gates is applied to an OR gate programmable inter
connect.

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Again, the crossover points are initially not electrically connected, but configuring the PLA will
connect particular crossover points together. In this view, the OR gate is seen with a single line to
the input. This view is by convention, but this also means that any of AND gate outputs can be
connected to the OR gate inputs. Hence, for four AND gates, the OR gate also has four inputs

Therefore, the function is implemented in either AND-OR form when the output link across
INVERTER is in place, or in AND-OR-INVERT form when the link is blown off. The general
structure of a PLA with internal connections is shown in figure below.

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The size of a PLA is specified by the number of inputs, the number of product terms,and the
number of outputs. The number of sum terms is equal to the number of outputs. The PLA described
in figure above is specified as n × p × m PLA. The number of programmable links is 2n × p + p ×
m + m, whereas that of ROM is 2n × m. A typical PLA of 16 × 48 × 8 has 16 input variables, 48
product terms, and 8 output lines.
To implement the same combinational circuit, a 216 × 8 ROM is needed, which consists of 2 16 =
65536 minterms or product terms. So there is a drastic reduction in number of AND gates within
the PAL chip, thus reducing the fabrication time and cost.
5.1.4 Programmable Array Logic (PAL)
The first programmable device was the programmable array logic (PAL) developed by Monolithic
Memories Inc(MMI). The Programmable Array Logic or PAL is similar to PLA, but in a PAL
device only AND gates are programmable. The OR array is fixed by the manufacturer. This
makes PAL devices easier to program and less expensive than PLA. On the other hand, since the
OR array is fixed, it is less flexible than a PLA device.

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The PAL device. has n input lines which are fed to buffers/inverters. Buffers/inverters are
connected to inputs of AND gates through programmable links. Outputs of AND gates are then fed
to the OR array with fixed connections. It should be noted that, all the outputs of an AND array are
not connected to an OR array. In contrast to that, only some of the AND outputs are connected to
an OR array which is at the manufacturer's discretion. This can be clarified by above, which
illustrates the internal connection of a four-input, eight AND-gates and three-output PAL device
before programming. Note that while every buffer/inverter is connected to AND gates through
links, F1-related OR gates are connected to only three AND outputs, F2 with three AND gates, and
F3 with two AND gates. So this particular device can generate only eight product terms, out of
which two of the three OR gates may have three product terms each and the
rest of the OR gates will have only two product terms. Therefore, while designing with PAL,
particular attention is to be given to the fixed OR array.
GAL-Generic Array Logic

PAL and PLA devices are one-time programmable (OTP) based on PROM, so the PAL or PLA
configuration cannot be changed after it has been configured. This limitation means that the
configured device would have to be discarded and a new device configured. The GAL, although
similar to the PAL architecture, uses EEPROM and can be reconfigured.
The Generic Array Logic (GAL) device was invented by Lattice Semiconductor. The GAL was an
improvement on the PAL because one device was able to take the place of many PAL devices or
could even have functionality not covered by the original range. Its primary benefit, however, was
that it was erasable and re-programmable making prototyping and design changes easier for
engineers. The GAL is very useful in the prototyping stage of a design, when any bugs in the logic
can be corrected by reprogramming.

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5.1.5 Complex Programmable Logic Device (CPLD)

CPLDs were pioneered by Altera, first in their family of chips called Classic EPLDs, and then
in three additional series, called MAX 5000, MAX 7000 and MAX 9000. The CPLD is the
complex programmable Logic Device which is more complex than the SPLD. This is build on
SPLD architecture and creates a much larger design. Consequently, the SPLD can be used to
integrate the functions of a number of discrete digital ICs into a single device and the CPLD can be
used to integrate the functions of a number of SPLDs into a single device.
So, the CPLD architecture is based on a small number of logic blocks and a global programmable
interconnect. Instead of relying on a programming unit to configure chip , it is advantageous to be
able to perform the programming while the chip is still attached to its circuit board. This method of
programming is known is called In-System programming (ISP). It is not usually provided for
PLAs (or) PALs , but it is available for the more sophisticated chips known as Complex
programmable logic device.

The CPLD consists of a number of logic blocks or functional blocks, each of which contains a
macrocell and either a PLA or PAL circuit arrangement. In this view, eight logic blocks are shown.
The building block of the CPLD is the macro-cell, which contains logic implementing disjunctive
normal form expressions and more specialized logic operations. The macro cell provides additional
circuitry to accommodate registered or nonregistered outputs, along with signal polarity control.
Polarity control provides an output that is a true signal or a complement of the true signal. The

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actual number of logic blocks within a CPLD varies; the more logic blocks available, the larger the
design that can be configured.
In the center of the design is a global programmable interconnect. This interconnect allows
connections to the logic block macrocells and the I/O cell arrays (the digital I/O cells of the CPLD
connecting to the pins of the CPLD package).The programmable interconnect is usually based on
either array-based interconnect or multiplexer-based interconnect:• Array-based interconnect allows
any signal within the programmable interconnect to connect to any logic block within the CPLD.

This is achieved by allowing horizontal and vertical routing within the programmable interconnect
and allowing the crossover points to be connected or unconnected (the same idea as with the PLA
and PAL), depending on the CPLD configuration.

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• Multiplexer-based interconnect uses digital multiplexers connected to each of the macrocell

inputs within the logic blocks. Specific signals within the programmable interconnect are connected
to specific inputs of the multiplexers. It would not be practical to connect all internal signals within
the programmable interconnect to the inputs of all multiplexers due to size
and speed of operation considerations.

5.1.6 FPGAs – Field Programmable Gate Arrays

The FPGA concept emerged in 1985 with the XC2064TM FPGA family from Xilinx . The
“FPGA is an integrated circuit that contains many (64 to over 10,000) identical logic cells that can
be viewed as standard components.” The individual cells are interconnected by a matrix of wires
and programmable switches. A user's design is implemented by specifying the simple logic
function for each cell and selectively closing the switches in the interconnect matrix. The array of
logic cells and interconnect form a fabric of basic building blocks for logic circuits. Complex
designs are created by combining these basic blocks to create the desired circuit.
Unlike CPLDs (Complex Programmable Logic Devices) FPGAs contain neither AND nor OR
planes.The FPGA architecture consists of configurable logic blocks, configurable I/O blocks, and
programmable interconnect. Also, there will be clock circuitry for driving the clock signals to
each logic block, and additional logic resources such as ALUs, memory, and decoders may be
available. The two basic types of programmable elements for an FPGA are Static RAM and anti-
fuses.
Each logic block in an FPGA has a small number of inputs and one output. A look up
table (LUT) is the most commonly used type of logic block used within FPGAs.
There are two types of FPGAs.(i) SRAM based FPGAs and (ii) Antifuse technology based(OTP)
Every FPGA consists of the following elements
 Configurable logic blocks(CLBs)
 Configurable input output blocks(IOBs)
 Two layer metal network of vertical and horizontal lines for interconnecting the CLBS
Configurable logic blocks(CLBs):
The configurable logic block is the basic logic cell and it is either RAM based or PLD based . It
consists of registers (memory), Muxes and combinatorial functional unit. An array of CLBS are
embedded within a set of vertical and horizontal channels that contain routing which can be

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personalized to interconnect CLBs.

Configurable Input / Output logic locks (IOBs):

CLBs and routing channels are surrounded by a set of programmable I/Os which is an
arrangement of transistors for configurable I/O drivers.
Programmable interconnects:
These are un programmed interconnection resources on the chip which have channeled
routing with fuse links. Four types of interconnect architectures are available. They are
 Row-Column Architecture
 Island Style Architecture
 Sea-of-Gates Architecture
Advantages of FPGAs:
 Design cycle is significantly reduced. A user can program an FPGA design in a few
minutes or seconds rather than weeks or months required for mask programmed parts.
 High gate density i.e, it offers large gate counts.
 No custom masks tooling is required (Low cost).
 Low risk and highly flexible.
 Reprogram ability for some FPGAs (design can be altered easily).

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 Suitable for prototyping.

 Parallelism
Allows for system-level extraction of parallelism to match input data
at design time
 Huge computational capability
 Fast development and Dynamic reconfiguration
 Updating new pattern matching rules (or simply rules)
 Device should not stop when updating new rules
 Update time for new rules
 To provide fast response to new attacks, the compilation and updating
time for new rules needs to be short
 In case of a hardwired FPGA architecture, the update time is mostly dependent on
place & route time
 Memory-based units can provide near instantaneous updates
Limitations:
 Speed is comparatively less.
 The circuit delay depends on the performance of the design implementation tools.
 The mapping of the logic design into FPGA architecture requires sophisticated design
implementation (CAD) tools than PLDs.
FPGA Programming Technologies:
(a) Antifuse Technology:
An antifuse is a two terminal device that when un-programmed has a very high resistance between
the two terminals and when programmed, or “blown”, creates a very low resistance or permanent
connection. The application of a high voltage from 11 V to 21 V will create the low resistive
permanent connection. Antifuse technologies come in two types. The first is oxide-nitride-oxide
(ONO) dielectric based and the other is amorphous silicon or metal-to-metal antifuse structures .
Dielectric based antifuses consist of a dielectric material between N+ diffusion and polysilicon
which breaks down when a high voltage is applied. Early dielectrics were a single-layered oxide
dielectric until Actel came out with the programmable low impedance circuit element (PLICE),
which is a multi-layer oxide-nitride-oxide (ONO) dielectric fuse. A high voltage across the PLICE
melts the dielectric and creates polycrystalline silicon between the terminals. When the PLICE is
blown, it adds three layers rather than the double metal CMOS process. The layers are a thin layer

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of oxide an top off the N+ surface, Low-pressure Chemical Vapor Deposition (LPCVD) nitride and
the reoxidized top oxide. The programming current has an important effect because the higher the
current during programming, the lower the link resistance, resulting in smaller thickness for the
antifuse material. Programming circuits for antifuses need to supply high currents (15 ma for Actel)
to insure high reliability and performance.
Amorphous silicon antifuse technology is the alternative to dielectric antifuse. It consists of
amorphous silicon between two layers of metal that changes phases when current is applied. When
the antifuse is not programmed the amorphous silicon has a resistance of 1 Giga ohm. When a high
current (about 20 mA) is applied to the anitfuse the amorphous silicon changes into a conductive
polysilicon link. Quick Logic pASIC FPGA is a perfect example of an amorphous silicon antifuse
technology.
(b). SRAM-based Technology:
SRAM FPGA architecture consists of static RAM cells to control pass gates or multiplexers. The
FPGA speed is determined by the delay introduced by the logic cells and the routing channels.
Multiplexers, look-up tables and output drivers affect the speed of signals through the logic cells.
An FPGA with more PIPs is easier to route but introducing more routing delay. The size of the
look-up table plays an important role depending on the design. Smaller LUTs provide higher
density but larger ones are preferred for high-speed applications.
Distinguish between SRAM and Antifuse Technologies: The following points explains the
differences between the two technologies.
1. Antifuse programming technology is faster than SRAM programming technology due to the RC
delays introduced by the interconnect structure.
2. Antifuse technology has more silicon area per gate and is easier to route than SRAM technology.
3. A disadvantage of antifuse FPGA is that they require more process layers and mask steps and
also contain high voltage programming transistors.
4. SRAM-based technology contains higher capacity than antifuse technologies.
5. SRAM based technology is very flexible with in-system programmability and the ability to
reconfigure the design during the debugging stage while antifuse technology is one-time
programmable (OTP). This ability reduces design and development, which reduces overall cost
of the design. Another advantage to this is that SRAM technology can be programmed at the

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factory through complete verification test where the antifuse are tested as “blanks” and require
programming by the user to verify design requirements and operation.
6. A disadvantage of SRAM technology is that it is volatile meaning it has to be reprogrammed
every time power is turned off and on again. The SRAM usually require an extra memory
element to program the chip which occupies board space .

5.1.7 Standard cells

In semiconductor design, standard cell methodology is a method of designing application-
specific integrated circuits (ASICs) with mostly digital-logic features. Standard cell methodology is
an example of design abstraction, whereby a low-level very-large-scale integration is encapsulated
into an abstract logic representation . Cell-based methodology — the general class to which
standard cells belong — makes it possible for one designer to focus on the high-level (logical
function) aspect of digital design, while another designer focuses on the implementation (physical)
aspect. Along with semiconductor manufacturing advances, standard cell methodology has helped
designers scale ASICs from comparatively simple single-function ICs (of several thousand gates),
to complex multi-million gate system-on-a-chip (SoC) devices.

A standard cell is a group of transistor and interconnect structures that provides a boolean
logic function or a storage function (flipflop or latch). The simplest cells are direct representations
of the elemental NAND, NOR, and XOR boolean function, although cells of much greater
complexity are commonly used (such as a 2-bit full-adder, or muxed D-input flipflop.) The cell's
boolean logic function is called its logical view: functional behavior is captured in the form of
a truth table or Boolean algebraequation (for combinational logic), or a state transition
table (for sequential logic).

Usually, the initial design of a standard cell is developed at the transistor level, in the form of
a transistor netlist or schematic view. The netlist is a nodal description of transistors, of their
connections to each other, and of their terminals (ports) to the external environment. A schematic
view may be generated with a number of different Computer Aided Design(CAD) or Electronic
Design Automation(EDA) programs that provide a Graphical User Interface (GUI) for this netlist
generation process. Designers use additional CAD programs such as SPICE or Spectre to simulate
the electronic behavior of the netlist, by declaring input stimulus (voltage or current waveforms)
and then calculating the circuit's time domain (analogue) response. The simulations verify whether

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the netlist implements the desired function and predict other pertinent parameters, such as power
consumption or signal propagation delay.

Since the logical and netlist views are only useful for abstract (algebraic) simulation, and not device
fabrication, the physical representation of the standard cell must be designed too. Also called
the layout view, this is the lowest level of design abstraction in common design practice. From a
manufacturing perspective, the standard cell's VLSI layout is the most important view, as it is
closest to an actual "manufacturing blueprint" of the standard cell. The layout is organized into base
layers, which correspond to the different structures of the transistor devices, and interconnect
wiring layers and via layers, which join together the terminals of the transistor formations.
The interconnect wiring layers are usually numbered and have specific via layers representing
specific connections between each sequential layer. Non-manufacturing layers may be also be
present in a layout for purposes of Design Automation, but many layers used explicitly for Place
and route (PNR) CAD programs are often included in a separate but similar abstract view. The
abstract view often contains much less information than the layout and may be recognizable as
a Layout Extraction Format (LEF) file or an equivalent.

After a layout is created, additional CAD tools are often used to perform a number of common
validations. A Design Rule Check (DRC) is done to verify that the design meets foundry and other
layout requirements. A Parasitic Extraction (PEX) then is performed to generate a PEX-net list with
parasitic properties from the layout. The nodal connections of that net list are then compared to
those of the schematic net list with a Layout Vs Schematic (LVS) procedure to verify that the
connectivity models are equivalent.

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Application of Standard cell

Strictly speaking, a 2-input NAND or NOR function is sufficient to form any arbitrary Boolean
function set. But in modern ASIC design, standard-cell methodology is practiced with a sizable
library (or libraries) of cells. The library usually contains multiple implementations of the same
logic function, differing in area and speed. This variety enhances the efficiency of automated
synthesis, place, and route (SPR) tools. Indirectly, it also gives the designer greater freedom to
perform implementation trade-offs (area vs. speed vs. power consumption). A complete group of
standard-cell descriptions is commonly called a technology library.
Commercially available Electronic Design Automation (EDA) tools use the technology libraries to
automate synthesis, placement, and routing of a digital ASIC. The technology library is developed
and distributed by the foundry operator. The library (along with a design netlist format) is the basis
for exchanging design information between different phases of the SPR process.
Programmable Array logic

The PAL device is a special case of PLA which has a programmable AND arrayand a fixed OR
array. The basic structure of Rom is same as PLA. It is cheap comparedto PLA as only the AND
array is programmable. It is also easy to program a PALcompared to PLA as only AND must be
programmed.

The figure 1 below shows a segment of an unprogrammed PAL. The input bufferwith non inverted
and inverted outputs is used, since each PAL must drive many ANDGates inputs. When the PAL is
programmed, the fusible links (F1, F2, F3…F8) areselectively blown to leave the desired
connections to the AND Gate inputs. Connectionsto the AND Gate inputs in a PAL are represented
byXs, as shown here:

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Figure 1: segment of an un programmed and programmed PAL.

As an example, we will use the PAL segment of figure 1 to realize the function I1I2‘+I1I2. The Xs
indicate that the I1 and I2‘ lines are connected to the first AND Gate, and the I1‘ and I2 lines are
connected to the other Gate. Typical combinational PAL have 10 to 20 inputs and from 2 to 10
outputs with 2to 8 AND gates driving each OR gate. PALs are also available which contain D flip-
flop switch inputs driven from the programming array logic. Such PAL provides a convenient way
of realizing sequential networks. Figure 2 below shows a segment of a sequential PAL. The D flip-
flop is driven from the OR gate, which is fed by two AND gates. The flip-flop output is fed back to
the programmable AND array through a buffer. Thus the AND gate inputs can be connected to A,
A‘, B, B‘, Q, or Q‘. The Xs on the diagram show the realization of the next-state equation.

Q+ = D = A‘BQ‘ + AB‘Q

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The flip-flop output is connected to an inverting tristate buffer, which is enabled when

EN = 1

Figure 3 below shows a logic diagram for a typical sequential PAL, the 16R4.This PAL has an
AND gate array with 16 input variables, and it has 4 D flip-flops. Each flip-flop output goes
through a tri state-inverting buffer (output pins 14-17). One input(pin 11) is used to enable these
buffers. The rising edge of a common clock (pin 1) causes the flip-flops to change the state. Each D
flip-flop input is driven from an OR gate, and each OR gate is fed from 8 AND gates. The AND
gate inputs can come from the external PAL inputs (pins2-9) or from the flip-flop outputs, which
are fed back internally. In addition there are four input/output (i/o) terminals (pins 12,13,18 and
19), which can be used as either network outputs or as inputs to the AND gates. Thus each AND
gate can have a maximum of 16 inputs (8 external inputs, 4 inputs fed back from the flip-flop
outputs, and 4 inputs from the i/o terminals). When used as an output, each I/O terminals driven
from an inverting tri state buffer. Each of these buffers is fed from an OR gate and each OR gate is
fed from 7 AND gates. An eighth AND gate is used to enable the output.

5.1.8 Design Approach

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n CMOS integrated circuit design there is a trade-off between static power consumption and
technology scaling. Recently, the power density has increased due to combination of higher clock
speeds, greater functional integration, and smaller process geometries. As a result static power
consumption is becoming more dominant. This is a challenge for the circuit designers. However,
the designers do have a few methods which they can use to reduce this static power consumption.
But all of these methods have some drawbacks. In order to achieve lower static power
consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a
new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing
technique without being penalized in area requirement and circuit performance
5.2 CMOS TESTING
Testing is one of the most expensive parts of chips
1) Logic verification accounts for > 50% of design effort for many chips
2) Debug time after fabrication has enormous opportunity cost
3) Shipping defective parts can sink a company

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5.2.1 Need for testing

The need of testing is to find out errors in the application.
The good reasons of testing are
1) Quality Assurance.
2) Verification and validating the product/application before it goes live in the market.
3) Defect free and user friendly.
4) Meets the requirements.
5.2.2 Test principles
Logic Verification:
1) Does the chip simulate correctly?
2) Usually done at HDL level
3) Verification engineers write test bench for HDL
• Can’t test all cases
• Look for corner cases
• Try to break logic design
Ex: 32-bit adder
Test all combinations of corner cases as inputs:
• 0, 1, 2, 231-1, -1, -231, a few random numbers Good tests require ingenuity.
5.2.3 Design strategies of testing
Manufacturing Test: A speck of dust on a wafer is sufficient to kill chip Yield of any chip is <
100%
Must test chips after manufacturing before delivery to customers to only ship good parts.
1) Manufacturing testers are very expensive
2) Minimize time on tester
3) Careful selection of test vectors

Observability & Controllability

Observability: ease of observing a node by watching external output pins of the chip
Controllability: ease of forcing a node to 0 or 1 by driving input pins of the chip
Combinational logic is usually easy to observe and control. Finite state machines can be very

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difficult, requiring many cycles to enter desired state especially if state transition diagram is not
known to the test engineer.

5.2.4 Chip level test techniques

Test Pattern Generation:
Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the
smallest sequence of test vectors necessary to prove each node is not stuck.
Good observability and controllability reduces number of test vectors required for manufacturing
test.
1) Reduces the cost of testing
2) Motivates design-for-test.

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TUTORIAL SHEETS

1 Explain lithography process with sketches

2 Explain diffusion process in IC fabrication
3 Discuss the purpose of metallization in IC manufacturing? Explain the
methods employed for metallization
4 How integrated passive components are fabricated in ICs? Explain
5 Mention the properties of oxidation. Explain about thermal oxidation process
6 Explain how a bipolar NPN transistor is included in n-well CMOS

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processing. Draw the cross section of BiCMOS transistor.

7 Consider an nMOS transistor in a 65 nm process with a minimum drawn channel length
of 50 nm (λ = 25 nm). Let W/L = 4/2 λ (i.e., 0.1/0.05 µm). In this process, the gate oxide
thickness is 10.5 A. Estimate the high-field mobility of electrons to be 80cm2/V· s at 70 o
C. The threshold voltage is 0.3V. Plot Ids vs. Vdsfor Vgs= 0, 0.2, 0.4, 0.6, 0.8, and 1.0 V
using the long- channel model.
8 Calculate the diffusion parasitic Cdbof the drain of a unit-sized contacted nMOS transistor
in a 65 nm process when the drain is at 0 V and again at VDD = 1.0 V. Assume the
substrate is grounded. The diffusion region conforms to the design rules from Figure 2.8
with λ = 25 nm. The transistor characteristics are CJ = 1.2 fF/µm2, MJ = 0.33, CJSW =
0.1 fF/µm, CJSWG =0.36 fF/µm, MJSW = MJSWG = 0.10, and 0 = 0.7 V at room
temperature.
9 Consider the nMOS transistor in a 65 nm process with a nominal threshold voltage of 0.3
V and a doping level of 8 × 1017 cm–3. The body is tied to ground with a substrate
contact. How much does the threshold change at room temperature if the source is at 0.6
V instead of 0?
10 What is the minimum threshold voltage for which the leakage current through an OFF
transistor (Vgs= 0) is 103 times less than that of a transistor that is barely ON (Vgs= Vt) at
room temperature if n = 1.5. One of the advantages of silicon-on insulator (SOI)
processes is that they have smaller n. What threshold is required for SOI if n = 1.3.
11 Consider an nMOS transistor in a 0.6 µm process with W/L = 4/2 λ (i.e., 1.2/0.6 µm). In
this process, the gate oxide thickness is 100 A and the mobility of electrons is 350
cm2/V· s. The threshold voltage is 0.7 V. Plot Idsvs. Vdsfor Vgs= 0, 1, 2, 3, 4, and 5 V.
12 Derive an equation for Idc of an n channel process of twin well MOSFET operating in
saturation region.
13 AN nMOS transistor is operating in saturation region with the following parameters.
Vgs=5V, Vth=1.2V.(W/L)=10, µCox=110µA/V2. Find
transconductance of the device.
14 For a CMOS inverter, calculate the shift in the transfer characteristic curve when βn/ βp
ratio is varied from 1/1 to 10/1.
15 Find gm and rdsfor an n-channel transistor with Vgs=1.2V,Vth=0.8V.(W/L)=10, µCox=92µ
A/V2and VDS = Veff +0.5V. The output impedance constant=0.0953V-1.
1 Draw the pass transistor arrangement for the logic X=ABC.
6
17 Sketch a stick diagram for a CMOS gate computing Y  A  B  C ·D and estimate
the cell width and height.
18 Design a layout diagram for the CMOS logic shown below
Y  A  B.C
19
Design a stick diagram for the CMOS logic shown below Y  A  B  C.
20 Design a stick diagram for two input pMOS NAND and NOR gates.

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21
Design a stick diagram for the CMOS logic for AB  CD
22
Design a layout diagram for the pMOS logic Y  A(B  C)
23 Design a layout diagram for two input nMOS NAND gate.
24 Design a stick diagram and layout for two input CMOS NAND gate indicating all the
regions and layers.
25 Draw the stick diagram and mask layout for a CMOS two input NOR gate.
26 Calculate the gate capacitance value of 5mm technology minimum size transistor with
gate to channel capacitance value is 0.0004 pF/mm2.
27 What is the problem of driving large capacitive loads? Explain a method to drive such
load.
28 Calculate the rise time and fall time of the CMOS inverter (W/L)n=6 and
' 2 '
(W/L)p=8. k  150A / V , V  0.7V, k  62A / V ,
n tn p 2

V  0.85V, V  3.3V. Total output capacitance =150Ff

Tp DD

29 Realize the function f=AB+CD using pseudo-nMOS logic.

30 Realize the function f  (A  BC)bar using pseudo-nMOS logic
31 Derive the expression for rise and fall time of CMOS inverter. Comment on the
expression derived.
32 State the problem that arises when comparatively large capacitive loads are driven by
inverters. Explain how super buffers can solve the problem.
33 Explain 2:1 multiplexer using transmission gate and tristate inverter.
34 Draw circuit diagram of one transistor with capacitor dynamic RAM and also draw its
layout.
35 Draw the circuit diagram for 4X4 barrel sifter using complementary transmission gates
and explain its shifting operation.
36 Design an incrementer circuit using counter.
37 Design ripple structure for one-zero detector circuit.
38 Design a comparator using XNOR gates.
39 Design sum and carry expressions of carry look ahead adder using Nmos logic.
40 Design a 4-bit array multiplier and implement using basic gates.
41 Design a 1-bit full adder and implement the sum and carry expressions using PLA.
42 Draw the basic structure of parallel scan and explain how it reduces the long scan chains.
43 Explain how an improved layout can reduces faults in CMOS circuits
44 Draw the state diagram of TAP controller and explain how it provides the control signals
for test data and instruction register.
45 Implement Y  ABAR.CBAR  AB  (ACD)BAR using programmable logic array
(PLA) and (PAL).
46 Implement Y  ABAR.CBAR  AB  (ACD)BAR using programmable logic array
(PLA) and (PAL).

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47 A sequential circuit with n inputs and m storage devices. To test this circuit how many
test vectors are required?
48 How IDDQ testing is used to test the bridge faults?
49 What is ATPG? Explain a method of generation of test vector.
50 Draw the stick and layout diagram of nMOS inverter

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MODEL QUESTIONS

(DESCRIPTIVE AND OBJECTIVE)

DESCRIPTIVE QUESTIONS
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UNIT- I(A)
PART-A

1. What is Moore’s law and define an IC.

2. Define thershold voltage(Vt).
3. List out the types of oxidations & explain.
4. What are the advantages of IC technology.
5. What is Ion Implementation & explain its mechanism.
6. What is metallization ? Give its requirements.
7. List out the factors of transistor modeling.
8. Write a short note on system design cycle.
9. What do you mean by an integrated resistor & capacitor?
10. Define the terms: Lithography & Diffusion.

Part-B
1. Describe the NMOS fabrication process with neat sketch.
2. Write about the CMOS fabrication using N-well process with neat diagrams.
3. Explicate the NMOS Enhancement & depletion mode fabrication process with neat sketch.
4. Describe the CMOS fabrication using P-well process with neat sketch.
5. Draw the flow diagram of CMOS fabrication using Berkley N-well process.
6. Write notes on CMOS fabrication using Silicon-On-Insulator(SOI) process with neat
diagrams.
7. Write the comparisions between CMOS ,Bipolar and GaAs technology.
8. Draw and write about the CMOS fabrication using Twin-Tub process.
9. Write in detail about dry and wet oxidation with neat diagrams.
10. What is BiCMOS Technology & give its advantages over CMOS technology.

UNIT – I(B)
PART-A
1. What is saturation region and write its expression for IDS.
2. What is non-saturation region and write its expression for IDS.
3. Draw the IDS and VDS graph for depletion mode.
4. Draw the IDS and VDS graph for Enhancement mode.
5. Define Transconductance (gm) & Output conductance(gds) with expressions.
6. What is pass transistor?
7. List out the advantages of Bi-CMOS Inverter.
8. Draw the transfer characteristics of Bi-CMOS Inverter.
9. What is NMOS and CMOS Inverter?
10. Define Figure of merit of MOS transistor(ω0).

PART-B
1. Derive the relationship between drain to source current versus drain to source

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voltage (IDSVs VDS) in non-saturated and saturated regions.

2. Determine the pull-up to pull-down ratio of an NMOS inverter, driven through
one or more Pass transistors.
3. Write about MOS transistor Thershold voltage.
4. Write the characteristics of NMOS inverter with neat diagram.
5. Determine the pull-up to pull-down ratio of an NMOS inverter, driven by
another NMOS transistor.
6. Draw the circuit for CMOS inverter and write the characteristics.
7. Explicate the alternative forms of pull-ups .
8. Elucidate the operation of Bi-CMOS inverter and specify its characteristics.
9. Find gm and rds for an n-channel transistor with vGS=1.2V, vtn=0.8v, W/L=10, µncox=92µA/V2
and VDS=Vef + 0.5v. The output impedance constant(λ) =95.3*10-3v-1.
10. A PMOS transistor is operated in the triode region with following parameters: vtp= -1v and
W/L=95, vGS= -4.5V and VDS=-2.2v, µpcox =95µA/V2. Find IDS & RDS.

UNIT -2
PART-A
1. What is full custom design?
2. What is semi custom design?
3. What is top-down & bottom-up approach?
4. What is layout?
5. List out the MOS layers.
6. List out the models of scaling.
7. What is stick diagram.
8. Mention any few λ based design rules for transistors?
9. List out any six scaling parameters.
10. List out the limitations of scaling.
PART-B
1. Elucidate the VLSI Design flow & write clearly about design processes.
2. Explicate the guidelines & design rules for stick diagram and layout diagram .
3. Design the stick diagram for two input NMOS NAND and NOR gates.
4. Draw the stick diagram & layout for two input NMOS Ex-OR gates.
5. Design the stick diagram for two input PMOS NAND and NOR Gates.
6. Draw the layout diagram for NMOS inverter.
7. Write the merits & demerits of scaling.
8. Write about design rules for wires in detail (orbit 2µm CMOS).
9. Write the scaling factors for different types of device parameters.
10. Design the circuit diagram,stick diagram & lay out for given Boolean function using
CMOS.F=(A+B+C)1

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UNIT-3
PART-A
1. What is switch logic?
2. What is sheet resistance (RS)?
3. Define pass transistor?
4. What are transmission gates?
5. List out the types of alternative gate circuits.
6. What is propagation delay?
7. What is wiring capacitance?
8. Define Fan-in and Fan-out.
9. What is Rise time(tr) & Fall time (tf).
10. What is gate capacitance (Cg).

PART-B

1. Write the operation of a CMOS Inverter with sketches.

2. Explicate the working of complex gates with neat diagrams.
3. Draw the logic diagram of dynamic and domino CMOS logic and explain in detail.
4. Elucidate briefly C2MOS and n-p-MOS logic with neat diagrams.
5. Describe the propagation delay in a cascaded pass transistor.
6. What is the problem of driving large capacitive loads? Explain a method to drive such load.
7. Write about the constraints of choice of layers.
8. What are the sources of wiring capacitances& write about the performance of VLSI
Circuits.
9. Explicate different series & parallel combinations of pull up & pull down networks.
10. Derive an equation for propagation delay in pass transistor chain.

UNIT-4(A)
PART-A

1. What is a shifter & list out its types?

2. What is serial adder?
3. What is carry -ripple adder?
4. What is carry-skip adder?
5. What is unsigned array multiplier?
6. What is one/zero detectors?
7. What is counter?
8. List out the properties of input/output subsystem?
9. What is data path subsystem?

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10. What is memory array subsystem?

PART-B
1. Draw the circuit diagram for 4x4 barrel shifter using complementary transmission gates &
explain its shifting operation.
2. Draw & explicate the structure of carry look ahead adder.
3. Explicate n- bit parallel adder?
4. Write a short notes on the following.
a) Shifter b) Parity generator
5. What is a magnitude comparator & design a magnitude comparator based on the data path
operators.
6. Draw the logic diagram of zero/one detector & explicate its operation with help of diagram.
7. Describe about data path organization & Discuss in detail about serial adder.
8. Draw & explicate the asynchronous counter in detail.
9. Elucidate about synchronous up/down counter using adder & register with neat diagram.
10. Give the classifications of multipliers &write in detail .

UNIT-4(B)
PART-A

1. Draw 6-transistor SRAM cell.

2. Difference between array & sub array.
3. Abbreviate PROM, EEPROM, LIFO, and FIFO.
4. Abbreviate SRAM, DRAM, SAM, and CAM.
5. Write about memory cell organization.
6. What is DRAM ?How it differs from SRAM.
7. Give construction & various operation with DRAM.
8. What is FLASH EPROM.
9. Write different types of memories.
10. Draw the levels of memory hierarchy with capacity access time & its speed.

PART-B
1. Elucidate basic memory chip architecture?
2. Explicate the principle of SRAM with neat sketch?
3. What is the principle of DRAM using 1- transistor with neat diagram?
4. Illustrate the following in detail.
(i) Flash memory
(ii) LIFO, FIFO
5. Write about shift registers & their types.
6. ExplicateSynchronous DRAM (SDRAM) with neat diagram.
7. Write in detail about CAM.
8. Write the different types of sequential memory access.
9. Explicate ROM cell organization & implement with an example.
10. Write about memory element parameters.

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UNIT-5(A)
PART-A

1. What is semi-custom ASIC?

2. What is full-custom ASIC?
3. What is programmable ASIC?
4. What is an ASIC?
5. Difference between channeled & channel less gate arrays.
6. Abbreviate CLB, VHDL, LUT, and FPGA,CPLD..
7. List out the advantages of antifuse technology.
8. List out the advantages of Gate arrays..
9. What are the similarities between CPLD & FPGA?
10. What are the different types of PLD’s.

PART-B
1. Explain the following in detail with neat diagram
i. Channeled Gate array
ii. Channel less Gate array
iii. Structured Gate array
2. a) Draw the schematic structure of PLA & explain its principle.
b) Using PLA implement JK flip flop circuit.
3. Sketch a diagram for two input XOR gate using PLA & explain its operation with the help
of truth tables.
4. Draw the structure of PAL & explain its principle.
5. Implement JK flip flop using PROM.
6. a) Describe about the principle & operation of FPGA
b) list out the applications of FPGA.
7. a)Write about Complex Programmable Logic Device. & draw its basic structure.
b) Give the applications and advantages of CPLD.
8. Compare PLA’s, PAL’s, CPLD’s, FPGA’s, & standard cells.
9. Clearly write each step of high level design flow of an ASIC.
UNIT-5(B)
PART-A

1. What is manufacturing testing?

2. What is functionality testing?
3. What is parametric fault & time of delay?
4. Write shortly about stuck-at-faults.
5. What is physical & logical fault?
6. What is BIST& mention its advantages.
7. What are the steps involved in Fault coverage .
8. What is an Open and Short circuit fault.
9. What is JTAG?

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10. What is Fault coverage .

PART-B

1. Write in detail about need for testing and the two groups of testing.
2. Explain what is meant by short and open circuit faults in detail.
3. Illustrate the following
i. Observability
ii. Fault Coverage
iii. Fault Simulation
iv. Controllability
4. Illustrate the following
i. Stuck- at faults
ii. Stuck- open & stuck- short faults
iii. Stuck- open fault.
5. a)What are the design strategies for test(DST).
b)Explicate the scan-based test techniques.
6. With neat diagram explain about the internal structure of BIST
7. Draw the architecture and the state diagram of TAP controller.
8. What are the chip level & system level test techniques.
9. How layout design can be done for improved testability? Explain.

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OBJECTIVE QUESTIONS

UNIT – 1A
1. Which of the material used as gate [ ]
a. Photo resistive b. polysilicon c. metal d. glass
2. The ---------- of the VLSI chip ranges from pre-assembly wafer preparation to fabrication techniques
for the packages that provide electrical connections and mechanical and environmental protection [ ]
a. Placement b. Floor planning c. Packaging d. None
3. ------------------ is the electrical consideration for VLSI packages [ ]
a. low ground resistance b. short signal leads c. minimum power supply spiking d.All
4. A MOS transistor which has conducting channel region at zero gate bias is called [ ]
a. Depletion mode b. Enhancement mode c. Saturated mode d. Non- saturated mode
5. If packing density area and performance are the constraints, power dissipation is not a constraint, the
technology you prefer [ ]
a. .BJT b. CMOS c. NMOS d. PMOS
6. The speed of the CMOS logic is less, when compared to other technologies due to [ ]
a. High noise immunity b. High input capacitance c. High driven current d. All
7. A. sink current is obtained under which condition. [ ]
a. Logic high input b. Logic low input c. Logic high output d. Logic low output
8. Which logic family has highest speed of operation [ ]
a. TTL b. DTL c. ECL d. All the above
9. The partial current flowing through p and n channels is called [ ]
a. Voltage spikes b. current spikes c. both a and b d. none of the above
10. -------------- is the non-saturated digital logic family [ ]
a. TTL b. ECL c. MOS d. RTL
11. Which logic family has very good noise immunity? [ ]
a. RTC b. DTL c. TTL d. ECL
12. The different integrator resistance is
13. The different integrator capacitance is
14. The fabrication of CMOS is done by
15. Diffusion process is carried out in a
16. Ion implantation is performed at temperature
17. The ions in ion implementation process are accelerated _
18. Ion implantation is other technique is
19. Abbreviation of CMOS is
20. Aluminum is used for metallization of most IC because
21. The body effect will be if the substrate is DC
22. The equation of Gm is
23. The output conductance Gds is
24. The polarities of voltage and current in PMOS circuits
25. The polarities of voltage and current in NMOS circuits
26. Charge moves from to when Vds is applied

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UNIT – 1B

1. Ids is dependent on and

2. When voltage is applied on the gate of a MOS transistor channel between source and drain
3. Electron transit time is denoted by
4. The equation for velocity V is
5. In a NMOS Inverter the depletion mode transistor
6. The depletion mode transistor is called in NMOS inverter
7. The enhancement mode transistor is called in NMOS inverter
8. Slope of the transistor characteristic determines the
9. When Vin the P.D threshold voltage current
10. The equation for Ids in saturation mode is
11. The equation for Ids in non-saturation mode is
12. The condition in saturated region is
13. The condition in non-saturated region is
14. In CMOS inverter the pull up transistor is

UNIT - 2

1. MOS circuits are formed from the following basic layers

2. The layers of the MOS circuits are isolated from each other by
3. When Polysilicon and thinox regions cross each other forms
4. Green colour is used in Stick diagrams in NMOS design for
5. Red colour is used in stick diagrams in NMOS design for
6. Blue colour is used in stick diagrams in NMOS design for
7. Brown colour is used in stick diagrams in NMOS design for
8. In 2ųM CMOS design rules for Bi cmos buried n-sub collector is
9. In 2ųM CMOS design rules for Bi cmos p-base the colour is
10. Scaling means to the feature size and to achieve p-circuitry chip
11. 1/ß is used as scaling factor
12. Gate area Ag is scaled by
13. gate capacitance per Unit area is scaled by
14. Gate capacitance Cg is given by the equation
15. Parastic capacitance is proportional to
16. The intrinsic and extrinsic delay of submicron logic circuits [ ]
17. What is the color code of metal-I ? [ ]
18. What is the colour code of n-diffusion? [ ]
19. What is the colour code of p-well? [ ]
20. ----------------- is required to connect two metal lines

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UNIT – 3

1. Switch logic is based on

2. Gate logic is based on
3. The sheet resistance Rs is
4. Area capacitance is given by
5. Permittivity of frees space
6. Standard unit of capacitance is denoted by
7. Sheet resistance is
8. Unit of sheet resistance is
9. Typical value of Rs for n-channel transistor for 5ųm technology
10. For 2ųm technology Rs is
11. For p-transistor channel Rs for 5ųm is
12. For 5ųm technology
13. For 2ųm technology
14. For 1.2ųm technology
15. Inter layers capacitance is highly dependent on
16. The no. of gates that can be connected at the input is
17. Fan-out is the no. of inputs that the gate can drive with out worst case is
18. The ability of an output to charge or discharge stray capacitance the input is
19. While considering choice of layers Vdd and Vss should be
20. The value of gate capacitance for CMOS inverter is

UNIT – 4A

1. For the 4X4 bit barrel shifter, the regularity factor is given by
a. 8 b . 4 c.2 d 16
2. The level of any particular design can be measured by
a. SNR b .Ratio of amplitudes c. regularity d. quality
3. In tackling the design of system the more significant property is
a. logical operations b . test ability c . topological properties d .nature of architecture
4. Any bit shifted out at one end of data word will be shifted in at the other end of the word is called
a. end-around b. end-off c. end-less d. end-on
5. In the VLSI design the data and control signals of a shift register flow in
a. horizontally and vertically b. vertically and horizontally c. both horizontally d .both vertically
6. The subsystem design is classified as
a. first level b. top level c. bottom level d. leaf-cell level
7. The larger system design must be partition into a sub systems design such that
a. minimum interdependence and inter conection
b. complexity of interconnection
c. maximum interdependence
d. arbitarily chosen
8. To simplify the subsystem design, we generally used the
a. interdependence b. complex interconnections c. regular structures d. standard cells
9. System design is generally in the manner of
a. down-top b. top-down c. bottom level only d. top level only
10. Structured design begins with the concept of
a. hierarchy b. down-top design c. bottom level design d. complex function design
11. Any general purpose n-bit shifter should be able to shift incoming data by up to number of places
are

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a. n b. 2n c. n-1 d. 2n-1
12. For a four bit word, a one-bit shift right is equivalent to a
a. two bit shift left b. three-bit shift left c. one bit shift left d. four-bit shift left

13. The type of switch used in shifters is

a. line switch b. transistor type switch c. crossbar switch d. gate switch
14. The carry chain in adder is consist with
a. cross-bar swith b. transmission gate c. bus interconncection d. pass transistors
15. VLSI design of adder element basically requires
a. EX-OR gate, Not and OR gates
b. multiplexers, inverter circuit and communication paths
c. multiplexers, EX-OR and NAND gates
d. inverter circuits and communication paths
16. The heart of the ALU is
a. Register b. adder c. control bus d. I/O port
17. Carry line in adder must be buffered after or before each adder element because
a. slow response of series pass transistors
b. slow response of parallel line
c. fast response of parallel pass transistors
d. fast response of series line
18. The ALU logical functions can be obtained by a suitable switching of the
a. carry line between adder elements
b. sum line between adder elements
c. carry line between shifter & buffer
d. sum line between shifter & buffer
19. To fast an arithmetic operations, the multipliers and dividers is to use architecture of
a. parallel b. serial c. pipelined d. switched

UNIT – 4B

1. Proper placement of memory elements makes maximum use of the

a. available clock period b. cost of area c. power dessipation d. parasitics
2. A design that requires high density memory is usually
a single ship b. on chip c. partitioned into several chips d. DRAMS
3. Random access memory at the chip level is classed as memory that has
a. an access time dependent of the physical location of the data
b. an access time independent of the physical loction of the data
c. reading or writing of a particular datum with address
d. examines a data word and compares this data with internally stored data
4. The following memory examines data word and compares this data with internally stored data
a. serial access memory
b. random access memory
c. content addressable memory
d. shift registers memory
5. The main characteristics of on chip memory is
a. small and slow
b. large and slow
c. small and faster
d. large and faster

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6. DRAM has a
a. smaller layout and uses large power
b. smaller layout and uses less power
c. more power and slower
d. more power and faster
7. SRAM has a
a. faster, more power and larger
b. slower, more power and larger
c. faster, less power and smaller
d. faster less power and larger
8. On chip memory is comes under the category of
a. high density memory
b. medium density memory
c. low density memory
d. large density memory
9. On chip memory usually in the order of
a. 10k bytes
b. 50k bytes
c. 1k bytes
d. 100 k bytes
10. The simplest and safest way to use memory in a system is to treat it as a
a. sequential component
b. combinational component
c. decoders
d. NOR gates
11. Serial access memory at the chip level is classed as memory that has
a. shift registers
b. counters
c. accesstime is independent of location of data
d. internally stored data is used

UNIT – 5A

1. The PLA provides a systematic and regular way of implementing multiple output functions of n
variables in
a. POS form
b. SOP form
c. complex form
d. simple form
2. V(input variables) X P(product terms) PLA is to maintain generality within the constraints of its
dimensions then for
a. AND gate have n inputs and output OR gate must have P inputs
b. AND gate have P inputs and output OR gate must have n inputs
c. Both AND gate and OR gate have n inputs
d. both AND and or gates have P inputs
3. A MOS PLA is realized by using the gate of
a. AND
b. OR
c. AND-OR

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d. NOR
4. A CMOS PLA is realized by
a. pseudo nmos NOR gate
b. CMOS NOR gate
c. pseudo nmos NAND gate
d. CMOS NAND gate
5. The mapping of irregular combinational logic functions into regular structures is provided by the
a. FPGA
b. CPCD
c. standard cells
d. PLA
6. The general arrangement of PLA is
a. AND/OR structure
b. OR/AND structure
c. NAND/NOR structure
d. EX-OR/OR structure
7. V XP X Z PLA represents as
a. V-no.of input variables P-no.of output functions Z-no.of gates
b. V-no.of gatesP-no.of OR gates Z- no.of AND gates
c. V-no.of input variables P-no.of product terms Z-no.of output functions
d. V-no.of gates P-no.of AND gates Z-no.of output functions
8. To realize any finite state machine requirements, the PLA along with
a. NOR gate is used
b. feed back links is used
c. NAND gate is used
d. NOT gate is used
9. To reduce the PLA dimensions, the simplification must be done on a
a. individual output basis
b. multi-output basis
c. individual product term
d. individual input basis
10. The advantage of pre-charge evaluate logic is .
11. Standard cells can be placed on silicon chip.
12. DRAM is widely used because
13. Pre designed logic cells are known as _
14. Standard cell areas in CBIC area
15. Power busses are also known as
16. Inter connections are in FPGA.
17. Device sizes in gate array are .
18. The small squares on the edge of the cell are raised for
19. Connecting data path element to form a data path results in and
layout than using standard cells
20. Cross talk results from
21. Silicon circuitry is connected to outside world by
22. LUT is used in
23. In full custom ASIC design all the layers are
24. FPGA is a
25. PAL and PLA are known as _
26. The output of a physical design is
27. IN a PLA are programmable
28. The size of an IC is generally measured by

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29. CLB are used In

UNIT – 5B

1. The example of physical defect is

2. technology is not used in FPGA.
3. The important design points about SOC are .
4. Design quality of chip is measured on
5. The example of electrical fault is
6. In a post silicon validation testing is done on
7. In structured gate array _ is customized?
8. The objectives of floor planning are
9. Some VLSI test procedures used are _
10. To increase observability techniques used are
11. Typical manufacturing defects in IC fabrication are
12. Logical faults generated by electrical faults are
13. is no used for testing of combinational logic.
14. Timing failure resulting from delay faults arises due to
15. The disadvantage of the scan based techniques are
16. Boundary scan techniques used for
17. The scan based technique is race and hazard free.
18. Signature analysis is used In
19. BIST techniques suffers from
20. In a BIST technique ORA and PSBRG uses

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REFERENCES:

1. Essentials of VLSI circuits and systems – Kamran Eshraghian, EshraghianDougles

and A. Pucknell, PHI, 2005 Edition.
2. CMOS VLSI Design- Neil H.E Weste, David Harris, AyanBanerjee, Pearson Education,
1999.

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